int_mon_cyccnt 

         Interrupt monitor cycle count value
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10050

Size: 32

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

value

RW 0x1F4

int_mon_cyccnt Fields

Bit Name Description Access Reset
15:0 value 
In polling mode, sets the number of cycles Cadence Flash Controller
                                 must wait before checking the status register. This register is
                                 only used when R/B pins are not available to Cadence NAND Flash
                                 Controller.
RW 0x1F4