SMMU_SCR1

         Provides top-level Secure control of the SMMU.
      
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA000004

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

NSCAFRO

RO 0x0

SPMEN

RW 0x0

SIF

RW 0x0

GEFRO

RW 0x1

GASRAE

RW 0x0

NSNUMIRPTO

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

NSNUMSMRGO

RW 0x40

Reserved

NSNUMCBO

RW 0x20