onfi_device_features

         Features supported by the connected ONFI device
      
Module Instance Base Address Register Address
sdm_i_nand_param 0xFFA10300 0xFFA10380

Size: 32

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

value

RO 0x0

onfi_device_features Fields

Bit Name Description Access Reset
15:0 value
The values in the field should be interpreted as follows[list]
                                  [*]Bit 0 - Supports 16 bit data bus width.
                                  [*]Bit 1 - Supports multiple LUN operations.
                                  [*]Bit 2 - Supports non-sequential page programming.
                                  [*]Bit 3 - Supports interleaved program and erase operations.
                                  [*]Bit 4 - Supports odd to even page copyback.
                                  [*]Bit 5 - Supports source synchronous.
                                  [*]Bit 6 - Supports interleaved read operations.
                                  [*]Bit 7 - Supports extended parameter page.
                                  [*]Bit 8 - Supports program page register clear enhancement.
                                  [*]Bit 9 - Supports EZNAND.
                                  [*]Bit 10 - Supports NV-DDR2.
                                  [*]Bit 11 - Supports Volume Addressing.
                                  [*]Bit 12 - Supports External Vpp.
                                  [*]Bit 13-15 - Reserved.[/list]
RO 0x0