DIEPCTL0 

         Device Control IN Endpoint 0 Control Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00900
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40900

Size: 32

Offset: 0x900

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EPEna

RW 0x0

EPDis

RW 0x0

RESERVED

RO 0x0

SNAK

WO 0x0

CNAK

WO 0x0

TxFNum

RW 0x0

Stall

RW 0x0

RESERVED1

RO 0x0

EPType

RO 0x0

NAKSts

RO 0x0

RESERVED2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USBActEP

RO 0x1

Reserved

RESERVED3

RO 0x0

MPS

RW 0x0

DIEPCTL0 Fields

Bit Name Description Access Reset
31 EPEna 
Endpoint Enable (EPEna)
 When Scatter/Gather DMA mode is enabled, For IN endpoints this bit
indicates that the descriptor structure and data buffer with data ready
to transmit is setup.
 When Scatter/Gather DMA mode is disabled such as in buffer pointer
based DMA mode this bit indicates that data is ready to be
transmitted on the endpoint.
The core clears this bit before setting the following interrupts on this
endpoint:
 Endpoint Disabled
 Transfer Completed
Value Description
0x0 No action
0x1 Enable Endpoint
RW 0x0
30 EPDis 
Endpoint Disable (EPDis)
The application sets this bit to stop transmitting data on an endpoint,
even before the transfer For that endpoint is complete. The application
must wait For the Endpoint Disabled interrupt before treating the endpoint
as disabled. The core clears this bit before setting the Endpoint Disabled
Interrupt. The application must Set this bit only If Endpoint Enable is
already Set For this endpoint.
Value Description
0x0 No action
0x1 Disabled Endpoint
RW 0x0
29:28 RESERVED 
RESERVED
 RO 0x0
27 SNAK 
Set NAK (SNAK)
A write to this bit sets the NAK bit For the endpoint.
Using this bit, the application can control the transmission of NAK
handshakes on an endpoint. The core can also Set this bit For an
endpoint after a SETUP packet is received on that endpoint.
Value Description
0x0 No action
0x1 Set NAK
WO 0x0
26 CNAK 
Clear NAK (CNAK)
A write to this bit clears the NAK bit For the endpoint.
Value Description
0x0 No action
0x1 Clear NAK
WO 0x0
25:22 TxFNum 
TxFIFO Number (TxFNum)
 For Shared FIFO operation, this value is always Set to 0, indicating
that control IN endpoint 0 data is always written in the Non-Periodic
Transmit FIFO.
 For Dedicated FIFO operation, this value is Set to the FIFO number
that is assigned to IN Endpoint 0.
Value Description
0xa Tx FIFO 10
0xb Tx FIFO 11
0xc Tx FIFO 12
0xd Tx FIFO 13
0xe Tx FIFO 14
0xf Tx FIFO 15
0x0 Tx FIFO 0
0x1 Tx FIFO 1
0x2 Tx FIFO 2
0x3 Tx FIFO 3
0x4 Tx FIFO 4
0x5 Tx FIFO 5
0x6 Tx FIFO 6
0x7 Tx FIFO 7
0x8 Tx FIFO 8
0x9 Tx FIFO 9
RW 0x0
21 Stall 
STALL Handshake (Stall)
The application can only Set this bit, and the core clears it, when a
SETUP token is received For this endpoint. If a NAK bit, Global Nonperiodic
IN NAK, or Global OUT NAK is Set along with this bit, the STALL
bit takes priority.
Value Description
0x0 No Stall
0x1 Stall Handshake
RW 0x0
20 RESERVED1 
RESERVED
 RO 0x0
19:18 EPType 
Endpoint Type (EPType)
Hardcoded to 00 for control.
Value Description
0x0 Endpoint Control 0
RO 0x0
17 NAKSts 
NAK Status (NAKSts)
Indicates the following:
 1'b0: The core is transmitting non-NAK handshakes based on the
FIFO status
 1'b1: The core is transmitting NAK handshakes on this endpoint.
When this bit is Set, either by the application or core, the core stops
transmitting data, even If there is data available in the TxFIFO.
Irrespective of this bit's setting, the core always responds to SETUP data
packets with an ACK handshake.
Value Description
0x0 The core is transmitting non-NAK handshakes based on the FIFO status
0x1 The core is transmitting NAK handshakes on this endpoint
RO 0x0
16 RESERVED2 
RESERVED
 RO 0x0
15 USBActEP 
USB Active Endpoint (USBActEP)
This bit is always SET to 1, indicating that control endpoint 0 is always
active in all configurations and interfaces.
Value Description
0x1 Control endpoint is always active
RO 0x1
10:2 RESERVED3 
RESERVED
 RO 0x0
1:0 MPS 
Maximum Packet Size (MPS)
Applies to IN and OUT endpoints.
The application must program this field with the maximum packet size For
the current logical endpoint.
 2'b00: 64 bytes
 2'b01: 32 bytes
 2'b10: 16 bytes
 2'b11: 8 bytes
Value Description
0x0 64 bytes
0x1 32 bytes
0x2 16 bytes
0x3 8 bytes
RW 0x0