two_row_addr_cycles

         Attached device has only 2 ROW address cycles 
      
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10190

Size: 32

Offset: 0x190

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

four

RW 0x0

Reserved

flag

RW 0x0

two_row_addr_cycles Fields

Bit Name Description Access Reset
4 four
This flag must be set for devices which allow for 4 ROW address cycles instead
                                      of the usual 3.
RW 0x0
0 flag
This flag must be set for devices which allow for 2 ROW address cycles instead
                                     of the usual 3. Alternatively, bootstrap_two_row_addr_cycles when asserted will
                                     set this flag.
RW 0x0