coh_mem00_bypass_I_main_QosGenerator_ExtControl 

         External inputs control.
Module Instance Base Address Register Address
CCU_coh_cpu0_bypass_coh_mem00_bypass_I_main_QosGenerator 0xF7100480 0xF7100498

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

EXTLIMITEN

RW 0x0

INTCLKEN

RW 0x0

EXTTHREN

RW 0x0

SOCKETQOSEN

RW 0x0

coh_mem00_bypass_I_main_QosGenerator_ExtControl Fields

Bit Name Description Access Reset
3 EXTLIMITEN 
When register field ExtLimitEn is set, the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted, the limiter is disabled: bandwidth is not limited, and the counter is stuck to 0. When the bit is cleared, the limiter operates normally and ignores ExtThr.
 RW 0x0
2 INTCLKEN 
When set to 1, register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0, and if configuration parameter useExternalReference is set to True, an external reference clock at the socket is used for bandwidth calculation.
 RW 0x0
1 EXTTHREN 
When register field ExtThrEn is set, internal signals Urgency, Press and Hurry are driven, when input signal ExtThr is low, by the value in register Priority field P0. When ExtThr is high, they are drven by the value in register Priority field P1.
 RW 0x0
0 SOCKETQOSEN 
Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency, Pressure, and Hurry signals: When set to 0, the QoS generator drives the levels. When set to 1, internal signals Pressure and Hurry are driven by the greater of the two levels from the socket interface or the QoS generator.
 RW 0x0