CMIUCMCIDR
CMIU Coherent Memory Cache Identification Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| CCU_iospace10 | 0xF70C5000 | 0xF70C5FF8 |
Size: 32
Offset: 0xFF8
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
rsvd1 RO 0x0 |
Type RO 0x0 |
NumWays RO 0x0 |
NumSets RO 0x0 |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NumSets RO 0x0 |
|||||||||||||||
CMIUCMCIDR Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:29 | rsvd1 |
Reserved (RAZ/WI) |
RO | 0x0 |
| 28:26 | Type |
Coherent Memory Cache Type |
RO | 0x0 |
| 25:20 | NumWays |
Number of Coherent Memory Cache Ways |
RO | 0x0 |
| 19:0 | NumSets |
Number of Coherent Memory Cache Sets |
RO | 0x0 |