gmacgrp_mmc_receive_interrupt

         <b> Register 65 (MMC Receive Interrupt Register) </b>

The MMC Receive Interrupt register maintains the interrupts that are generated when the following happens:
 * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter).
 * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). 
When the Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800104
i_emac_emac1 0xFF802000 0xFF802104
i_emac_emac2 0xFF804000 0xFF804104

Size: 32

Offset: 0x104

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_26

RO 0x0

rxctrlfis

RO 0x0

rxrcverrfis

RO 0x0

rxwdogfis

RO 0x0

rxvlangbfis

RO 0x0

rxfovfis

RO 0x0

rxpausfis

RO 0x0

rxorangefis

RO 0x0

rxlenerfis

RO 0x0

rxucgfis

RO 0x0

rx1024tmaxoctgbfis

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rx512t1023octgbfis

RO 0x0

rx256t511octgbfis

RO 0x0

rx128t255octgbfis

RO 0x0

rx65t127octgbfis

RO 0x0

rx64octgbfis

RO 0x0

rxosizegfis

RO 0x0

rxusizegfis

RO 0x0

rxjaberfis

RO 0x0

rxruntfis

RO 0x0

rxalgnerfis

RO 0x0

rxcrcerfis

RO 0x0

rxmcgfis

RO 0x0

rxbcgfis

RO 0x0

rxgoctis

RO 0x0

rxgboctis

RO 0x0

rxgbfrmis

RO 0x0

gmacgrp_mmc_receive_interrupt Fields

Bit Name Description Access Reset
31:26 reserved_31_26
Reserved
RO 0x0
25 rxctrlfis
MMC Receive Control Frame Counter Interrupt Status

This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value.
RO 0x0
24 rxrcverrfis
MMC Receive Error Frame Counter Interrupt Status

This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value.
RO 0x0
23 rxwdogfis
MMC Receive Watchdog Error Frame Counter Interrupt Status

This bit is set when the rxwatchdogerror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
22 rxvlangbfis
MMC Receive VLAN Good Bad Frame Counter Interrupt Status

This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
21 rxfovfis
MMC Receive FIFO Overflow Frame Counter Interrupt Status

This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
20 rxpausfis
MMC Receive Pause Frame Counter Interrupt Status

This bit is set when the rxpauseframe counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
19 rxorangefis
MMC Receive Out Of Range Error Frame Counter Interrupt Status

This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
18 rxlenerfis
MMC Receive Length Error Frame Counter Interrupt Status

This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
17 rxucgfis
MMC Receive Unicast Good Frame Counter Interrupt Status

This bit is set when the rxunicastframes_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
16 rx1024tmaxoctgbfis
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status

This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
15 rx512t1023octgbfis
MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status

This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
14 rx256t511octgbfis
MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status

This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
13 rx128t255octgbfis
MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status

This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
12 rx65t127octgbfis
MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status

This is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
11 rx64octgbfis
MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status

This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
10 rxosizegfis
MMC Receive Oversize Good Frame Counter Interrupt Status

This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
9 rxusizegfis
MMC Receive Undersize Good Frame Counter Interrupt Status

This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
8 rxjaberfis
MMC Receive Jabber Error Frame Counter Interrupt Status

This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
7 rxruntfis
MMC Receive Runt Frame Counter Interrupt Status

This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
6 rxalgnerfis
MMC Receive Alignment Error Frame Counter Interrupt Status

This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
5 rxcrcerfis
MMC Receive CRC Error Frame Counter Interrupt Status

This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
4 rxmcgfis
MMC Receive Multicast Good Frame Counter Interrupt Status

This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
3 rxbcgfis
MMC Receive Broadcast Good Frame Counter Interrupt Status.

This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value.
RO 0x0
2 rxgoctis
MMC Receive Good Octet Counter Interrupt Status.

This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
1 rxgboctis
MMC Receive Good Bad Octet Counter Interrupt Status

This bit is set when the rxoctetcount_bg counter reaches half of the maximum value or the maximum value.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
0 rxgbfrmis
MMC Receive Good Bad Frame Counter Interrupt Status

This bit is set when the rxframecount_bg counter reaches half of the maximum value or the maximum value.
Value Description
0x0 ALMOSTHALF
0x1 ALMOSTFULL
RO 0x0