CAIUCESAR

         CAIU Correctable Error Status Alias Register

Module Instance	Base Address	Register Address
`CCU_fpga10`	`0xF7001000`	`0xF7001124`

Size: 32

Offset: 0x124

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rsvd2` `RO 0x0`								`ErrInfo` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ErrType` `RW 0x0`				`ErrCount` `RW 0x0`								`rsvd1` `RO 0x0`		`ErrOvf` `RW 0x0`	`ErrVld` `RW 0x0`

CAIUCESAR Fields

Bit	Name	Description	Access	Reset
31:24	`rsvd2`	Reserved (RAZ/WI)	`RO`	`0x0`
23:16	`ErrInfo`	Error Info	`RW`	`0x0`
15:12	`ErrType`	Error Type	`RW`	`0x0`
11:4	`ErrCount`	Error Count	`RW`	`0x0`
3:2	`rsvd1`	Reserved (RAZ/WI)	`RO`	`0x0`
1	`ErrOvf`	Error Overflow	`RW`	`0x0`
0	`ErrVld`	Error Valid	`RW`	`0x0`