SMMU_CB11_TLBIVAAL_high

         Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
      
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA02B62C

Size: 32

Offset: 0x2B62C

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ASID

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Address

WO 0x0