PLDMND

         
Name: Poll Demand Register
Size: 32 bits
Address Offset: 0x84
Read/Write access: write
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D1084

Size: 32

Offset: 0x84

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PD

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD

WO 0x0

PLDMND Fields

Bit Name Description Access Reset
31:0 PD
Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal 
descriptor fetch operation. This is a write only register.
PD bit is write-only.
WO 0x0