reg_sideband10

         Sideband 10 Register
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF80100D4

Size: 32

Offset: 0xD4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_dpd_mps_ack

RO 0x0

reg_sideband10 Fields

Bit Name Description Access Reset
0 mmr_dpd_mps_ack
iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_ack
Name:Deep Power Down/Max Power Saving Acknowlege
Description:Acknowledge to indicate deep power down/max power saving is in progress.
RO 0x0