ECC_RDECCDATA2BREGBUS_BEAT0

         ECC of data[Upper] from DRAM will be written to register
 - x64:         full data
 - x32, x16: beat-0 data
      
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF80112D4

Size: 32

Offset: 0x2D4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ECC7BUS

0x0

ECC6BUS

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECC5BUS

0x0

ECC4BUS

0x0

ECC_RDECCDATA2BREGBUS_BEAT0 Fields

Bit Name Description Access Reset
31:24 ECC7BUS
ECC of data [511:448] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
RO 0x0
23:16 ECC6BUS
ECC of data [447:384] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
RO 0x0
15:8 ECC5BUS
ECC of data [383:320] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
RO 0x0
7:0 ECC4BUS
ECC of data [319:256] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
RO 0x0