O-RAN Intel FPGA IP Design Example User Guide

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UG-20317 | 2020.11.30

Version Information

Updated for:
Intel® Quartus® Prime Design Suite 20.3
IP Version 1.2.0

1. About the O-RAN Intel FPGA IP Design Example

The design example allows you to simulate, compile, and test your O-RAN IP instance on various development boards. The design example includes Ethernet IP, eCPRI IP, eCPRI IOPLL, PTP IOPLL, and a test wrapper.

The compiled hardware design example runs on the:

Intel^® Arria^® 10 GX Signal Integrity Development Kit
Intel^® Stratix^® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples

2. Getting Started with the O-RAN Intel FPGA IP Design Example

2.1. Generating the O-RAN IP Design Example

Quickly configure your custom IP variation in the IP Parameter Editor and generate a design example.

Create an Intel^® Quartus^® Prime Pro Edition project in which to integrate your IP.
1. In the Intel^® Quartus^® Prime Pro Edition, click File > New Project Wizard to create a new Intel Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
2. Specify the device family that meets the speed grade requirements for the IP.
3. Click Finish.
In the IP Catalog, select O-RAN Intel FPGA IP.
The New IP Variation window appears.
Specify a top-level name for your new custom IP variation.
The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
Click OK. The parameter editor appears.

Figure 1. O-RAN IP Parameter Editor
Specify the parameters for your IP variation. Refer to Parameters for information about specific IP parameters.
Click the Design Example tab and specify the parameters for your design example.

Figure 2. Design Example Parameter Editor
Click Generate HDL.
The Generation dialog box appears.
Specify output file generation options, and then click Generate.
The IP variation files generate according to your specifications.
Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.

2.1.1. O-RAN IP Design Example Parameters

Table 1. O-RAN IP Design Example Parameters
Parameter	Values	Description
Generate Example Design for	Simulation	Select to generate the simulation files.
	Synthesis	Select to generate the synthesis files
	Synthesis & Simulation	Select to generate the synthesis and simulation files.
Generate File Format	Verilog VHDL	Select either Verilog HDL or VHDL as the format for generated RTL files simulation and synthesis. Some submodules are generated in mixed (both Verilog HDL and VHDL) formats.
Select board	Arria Signal Integrity Development Kit	Select to allow you to test the design example on the selected Intel development kit. The wizard automatically selects the target device to match the device on the selected Intel development kit. Select 10AX115S2F45I1SG for an Intel^® Arria^® 10 device. If your board revision has a different speed grade of these devices above, you can correct it.
	Stratix 10 Signal Integrity Development Kit	Select to allow you to test the design example on the selected Intel development kit. The wizard automatically selects the target device to match the device on the selected Intel development kit. Select 1SX280HU2F50E2VG for Intel^® Stratix^® 10 H-Tile and 1ST280EY2F55E2VG for Intel^® Stratix^® 10 E-Tile. If your board revision has a different speed grade of these devices above, you can correct it.
	No Development Kit	Select to exclude hardware for the design example.

2.2. Simulating the O-RAN IP Design Example

Turn on Example Design > Files Types Generated > Simulation.

Run the script to simulate the testbench in the ModelSim, VCS, or VCS MX simulators.

Table 2. Simulation Scripts
Simulator	File Directory	Script
Modelsim Altera SE	<variation name> oran_testbench/simulation/setup_scripts/mentor	run_vsim.do
VCS	<variation name> oran _testbench/simulation/setup_scripts/synopsys/vcs	run_vcs.sh
VCSMX	<variation name> oran _testbench/simulation/setup_scripts/synopsys/vcsmx	run_vcsmx.sh

Figure 3. Transmitter Top-Level Simulation

Figure 4. Transmitter Top-Level Simulation (Zoomed)

Figure 5. Receiver Top-Level Simulation

Figure 6. Receiver Top-Level Simulation (Zoomed)

2.2.1. Enabling Dynamic Reconfiguation to the Ethernet IP

By default, the dynamic reconfiguration is disabled in the O-RAN IP design example.

Look for the following line in the test_wrapper.sv from the generated <design_example_path>/simulation/testbench directory:

parameter ETHERNET_DR_EN = 0,
Change the value from 0 to 1:
parameter ETHERNET_DR_EN = 1
Rerun the simulation using the same generated example design directory.

2.2.2. O-RAN IP Design Example Testbench

The generated simulation testbench is dynamic and has the same configuration as the IP.

Figure 7. Testbench Block Diagram

2.3. Operating the O-RAN IP Design Example

After you download the design example to an FPGA:

For Intel^® Stratix^® 10 designs, program the nios_system.elf software into the FPGA. Refer to Generating and Downloading the Programming File.
Change the directory to <variation name>/synthesis/quartus/hardware_test/ and find the relevant system console script: .
- oran_a10.tcl for Intel^® Arria^® 10 designs
- oran_s10.tcl for Intel^® Stratix^® 10 designs
For E-tile, you must perform either an internal or external loopback command once first after programming the SOF file for proper transceiver calibration.
Change the TEST_MODE variable value in flow.c for the testing condition:
- 0 - for simulation only, serial loopback enable
- 1 - serial loopback enable
- 2 - serial loopback + calibration
- 3 - calibration only
Whenever you change flow.c, recompile and regenerate the Nios II software, then reprogram the design into the FPGA before reprogramming the Nios II software application.

Test the design operation through the commands supported in the system console script. The system console script provides useful commands for reading statistics and features enabling in the design.

Table 3. System Console Script Commands
Command	Description
`link_init_int_lpbk`	Enable transmitter to receiver internal serial loopback within the transceiver and perform the transceiver calibration flow. Ethernet Hard Intel FPGA IP (E-tile) only.
`link_init_ext_lpbk`	Enable transmitter to receiver external loopback and perform the transceiver calibration flow. Ethernet Hard Intel FPGA IP (E-tile) only.
`loop_off`	Disable transmitter to receiver internal serial loopback. 25G Ethernet Intel^® Stratix^® 10 FPGA IP (H-tile) and Low Latency Ethernet 10G MAC IP ( Intel^® Arria^® 10) only.
`loop_on`	Enable transmitter to receiver internal serial loopback. 25G Ethernet Intel^® Stratix^® 10 FPGA IP (H-tile) and Low Latency Ethernet 10G MAC IP ( Intel^® Arria^® 10) only.
`dr_25g_to_10g_etile`	Switch the data rate of the Ethernet MAC from 25G to 10G. Use for E-tile devices.
`dr_10g_to_25g_etile`	Switch the data rate of the Ethernet MAC from 10G to 25G. Use for E-tile devices.
`traffic_gen_enable`	Resets the entire design system, enables the traffic generator and checker.
`chkmac_stats`	Displays the statistics for Ethernet MAC.
`ext_continuous_mode_en`	Resets the entire design system, enables the traffic generator to generate continuous traffic packets.
`dr_25g_to_10g_htile`	Switch the data rate of the Ethernet MAC from 25G to 10G. Use for H-tile device.
`dr_10g_to_25g_htile`	Switch the data rate of the Ethernet MAC from 10G to 25G. Use for H-tile device.
`traffic_gen_disable`	Disables the traffic generators and checkers, resets the entire design system.
`read_test_statistics`	Displays the error statistics for traffic generators and checkers.

Figure 8. System Console Printout

==========================================================================================
 		     	      STATISTICS FOR BASE 0x20200000 (Tx) 		    
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 26112 
65 - 127 Byte Frames             : 0 
128 - 255 Byte Frames            : 2905577051 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Tx Frame Starts                  : 2905603162 
Multicast data  OK  Frame        : 2905603163 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Payload Octets OK                : 322109835482 
Frame Octets OK                  : 381042682938

Figure 9. System Console Printout

==========================================================================================
 		     	      STATISTICS FOR BASE 0x20200000 (Rx) 		    
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 26112 
65 - 127 Byte Frames             : 0 
128 - 255 Byte Frames            : 2909837973 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Rx Frame Starts                  : 2909864084 
Multicast data  OK  Frame        : 2909864085 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Payload Octets OK                : 322582196012 
Frame Octets OK                  : 381601465532 
TX U SOP Count: 34115144
TX U EOP Count: 36028887
RX U SOP Count: 37909557
RX U EOP Count: 39819450
U Checker Errors: 0
U Checker Error Counts: 0
EXT PTP TX SOP Count: 128
EXT PTP TX EOP Count: 128
EXT MISC TX SOP Count: 65735351
EXT MISC TX EOP Count: 68289340
EXT RX SOP Count: 70844347
EXT RX EOP Count: 73428779
EXT Checker Errors: 0
EXT Checker Error Counts: 0

2.3.1. Generating and Downloading the Programming File

Generate and download the .elf file for the O-RAN IP design example to the development board. For Intel^® Stratix^® 10 designs only.

Change the directory to <design_example_dir>/synthesis/quartus.
In the Intel^® Quartus^® Prime Pro Edition software, click Open Project and open <design_example_dir>/synthesis/quartus/oran_ed.qpf.
Select Tools > Nios II Software Build Tools for Eclipse.
The Workspace Launcher window prompt appears.
In the workspace specify the path as <design_example_dir>/synthesis/quartus to store your Eclipse project. A new Nios II - Eclipse window appears.
In the Nios II - Eclipse window, right-click under Project Explorer tab, and select New > Nios II Board Support Package.

Figure 10. Project Explorer Window
In the Nios II Board Support Package window:
1. In the Project name parameter, specify your desired project name.
2. In the SOPC Information File name parameter, browse to the location of <design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo file.
3. Click Finish.
Figure 11. Nios II Board Support Package Window

The newly created project appears under Project Explorer tab in Nios II - Eclipse window.
Right-click under Project Explorer tab and select Nios II > Nios II Command Shell.

Figure 12. Project Explorer - Nios II Command Shell
In the Nios^® II Command Shell, type the three following commands:
nios2-bsp hal bsp ../../nios_system/nios_system.sopcinfo

nios2-app-generate-makefile --app-dir app --bsp-dir bsp --elf-name nios_system.elf --src-dir ../../../ed_fw

make --directory=app
Type the following command in the Nios^® II Command Shell to download the .elf software application to the board:
nios2-download -g -r -c 1 -d 2 --accept-bad-sysid app/nios_system.elf

3. O-RAN Intel FPGA IP Design Example Functional Description

Figure 13. Block Diagram

Signal	Direction	Comments
`clk100`	Input	Input clock for reconfiguration. For Intel^® Arria^® 10 designs, a 156.25 MHz oscillator on the board drives this clock. For Intel^® Stratix^® 10 designs, a 100 MHz oscillator on the board drives this clock.
`mgmt_reset_n`	Input	Input reset for the Nios^® II system.
`clk_ref`	Input	For Intel^® Arria^® 10 designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 1G/10GbE and 10GBase-KR PHY IP . Connect to `pll_refclk0[0]`in the Transceiver ATX PLL and `rx_cdr_ref_clk_10g[0]` in the 1G/10GbE and 10GBase-KR PHY IP. For Intel^® Stratix^® 10 E-tile designs, 156.25 MHz clock input for the E-tile Ethernet Hard IP core. Connect to `i_clk_ref[0]` in the Ethernet Hard IP. For Intel^® Stratix^® 10 H-tile designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 25G Ethernet IP. Connect to `pll_refclk0[0]`in the Transceiver ATX PLL and `clk_ref[0]` in 25G Ethernet IP.
`tod_sync_sampling_clk`	Input	For Intel^® Arria^® 10 designs, a 250 MHz clock input for TOD subsystem.
`tx_serial`	Output	Transmitter serial data.
`rx_serial`	Input	Receiver serial data.

O-RAN IP

The O-RAN IP receives and transmits data at the transmitter and receiver application interfaces (the traffic components instantiated within the test wrapper).

eCPRI IP

The eCPRI IP receives and transmits data at the Avalon^® streaming source and sink interfaces (from the O-RAN transmitter, and receiver transport interfaces) and the external source and sink interfaces (the external traffic components instantiated within the test wrapper). The eCPRI IP prioritizes the data for transmission to the Ethernet IP.

eCPRI IOPLLL

For design examples targetting Intel^® Stratix^® 10 devices only, the eCPRI IOPLL generates the clock output of 390.625 MHz to feed into the transmitter and receiver data path of the eCPRI IP, the O-RAN IP, and the traffic generator and checker components.

PTP IOPLL

For Intel^® Arria^® 10 devices the PTP IOPLL generates the 312.5 MHz and 156.25 MHz clock inputs for the Low Latency Ethernet 10G MAC, eCPRI, O-RAN, 1G/10GbE and 10GBase-KR PHY IPs.

For Intel^® Stratix^® 10 devices, the PTP IOPLL generates the latency measurement input reference clock for the 25G Ethernet Intel FPGA IP and the sampling clock for TOD subsystem. For the 25G Ethernet Intel FPGA IP with the IEEE 1588v2 feature, Intel recommends that you set the frequency of this clock to 156.25 MHz.

For more information, refer to the 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide and the Intel Stratix 10 H-Tile Transceiver PHY User Guide.

Nios II subsystem

The Nios II subsystem consists of the:

Avalon memory-mapped bridge, which allows Avalon memory-mapped data arbitration between traffic from the Nios II processor and the test wrapper
A Nios II processor
An Avalon memory-mapped address decoder

For design examples targetting Intel^® Stratix^® 10 devices only, the Nios II processor performs the data rate switching based on the output from the test wrapper's rate_switch register value. The Nios II processor programs the necessary register after the command from the test wrapper. Design examples targetting Intel^® Arria^® 10 devices do not support data rate switching.

Ethernet IP

The design example instantiates one of the following Ethernet IP to interface with the eCPRI IP:

Low Latency Ethernet 10G MAC IP and 1G/10GbE and 10GBase-KR PHY IP ( Intel^® Arria^® 10 designs)
Ethernet Hard IP ( Intel^® Stratix^® 10 E-tile designs)
25G Ethernet Stratix 10 IP ( Intel^® Stratix^® 10 H-tile designs)

TOD Subsystem

The time of day (TOD) subsystem consists of two IEEE 1588 TOD modules for both transmitter and receiver, and one IEEE 1588 TOD synchronizer module.

System Console Access through JTAG Interface

The system console provides an interface for you to debug and monitor the status of the IP and the traffic generators and checkers.

Test Wrapper

The test wrapper consists of numerous traffic generators and checkers that generate different types of data packets to the O-RAN IP and the eCPRI IP.

Test Wrapper O-RAN IP Data Packets

The traffic generator supports O-RAN packets to the Avalon streaming source and sink interfaces of the O-RAN IP with configurations for C-plane, C-plane extension, and U-plane.

Table 4. C-Plane Configurations
Parameter	Description
`rtcid` `seqid`	Transport header fixed parameter value.
`dataDirection` `Filterindex`	Common Header fixed parameter value.
`frameId`	Fixed initial value (configured with parameter).
`subframeId`	Fixed initial value (configured with parameter).
`slotId`	Fixed initial value (configured with parameter).
`symbolId`	Fixed initial value (configured with parameter).
`NumberofSections`	6 for `Sectiontype`. 1, 2 for `Sectiontype` 3.
`Sectiontype`	1, 3.
`Timeoffset`	Fixed parameter value.
`frameStructure`	Fixed parameter value.
`cpLength`	Fixed parameter value.
`udCompHdr`	Applicable only when compression is enabled: `udCompMeth` = 0001 or 0011, and `udIqWidth` = 1000 or 1100
`sectionId`	Section header fixed parameter value.
`Sectiontype`	Section extension.
`ExtType`	3 (DL precoding).
`Rb`	Fixed parameter value.
`StartPrb`	Fixed parameter value.
`numPrb`	Fixed parameter value.
`reMask`	Fixed parameter value.
`numSymbol`	Fixed parameter value.
`Ef`	0 for Sectiontype 1, 1 for Sectiontype 3.
`frequencyOffset`	Fixed parameter value.

Table 5. C-Plane Extension Configurations
Parameter	Description
`NumberofSections`	2.
`ExtType`	3 (DL Precoding).
`Payload Size`	32 bytes (16 bytes for each section).

Table 6. U-Plane Configurations

Incremental pattern mode generation with some interpacket gaps.

Configurable via CSR to run in either non-continuous or continuous mode.

Transmitter and receiver packet statistic status available to access via CSR.
Parameter	Description
`dataDirection` `Filterindex`	Common header fixed parameter value.
`frameId`	Fixed initial counter value (configured from parameter).
`subframeId`	Fixed initial counter value (configured from parameter).
`slotId`	Fixed initial counter value (configured from parameter).
`symbolId`	Fixed initial counter value (configured from parameter).
`udCompHdr`	Applicable only when compression is enabled. `udCompMeth` = 0001 or 0011 and `udIqWidth` = 1000 or 1100
`sectionId`	Section header fixed parameter value.
`Rb`	Fixed parameter value.
`StartPrb`	Fixed parameter value.
`numPrb`	Fixed parameter value.

Table 7. Supported C and U-plane Traffic Configurations
The table shows specific configuration settings supported in the design example. You may modify these parameters in the generated oran_ed_top.sv and oran_tb.sv files to run the design example successfully.
ENABLE_COMPRESSION¹ ³	ENABLE_CPLANE²	ENABLE_UPLANE	udCompMeth ³	udIqWidth³	C_Sectiontype⁴
1	1	0	0,1,3	8,12,16	1,3
1	1	1	1,3	8,12	1,3
0	0	1	0	16	1,3
0	1	1	0	16	1,3
0	1	0	0	16	1,3

Test Wrapper ECPRI IP IP Data Packets

For PTP synchronization packets and non-PTP miscellaneous packets to the external source and sink interfaces:

External PTP packets:
- Static Ethernet header generation with predefined parameters: EtherType = 0x88F7, or Message Type = Opcode 0 (sync), or PTP version = 0
- Predefined pattern mode generation with interpacket gap of two cycles and payload size of 57 bytes for each packet.
- 128 packets generate every second.
- CSR configurable to run either non-continuous or continuous.
- Transmitter or receiver packet statistic status available via CSR.

External non-PTP miscellaneous packets:
- Static Ethernet header generation with predefined parameters: EtherType = 0x8100 (non-PTP)
- PRBS pattern mode generation with interpacket gap of two cycles and payload size of 128 bytes for each packet.
- CSR configurable to run either non-continuous or continuous.
- Transmitter or receiver packet statistic status available via CSR.

Design Example Address Mapping

Table 8. JTAG to Avalon Memory-mapped Bridge Address Mapping
Address	Target
0x20100000 – 0x201fffff ⁵	IOPLL reconfiguration Avalon memory-mapped register.
0x20200000 – 0x203fffff	Ethernet MAC Avalon memory-mapped register.
0x20400000 – 0x205fffff	Ethernet MAC Native PHY Avalon memory-mapped register..
0x20600000 – 0x207fffff ⁵	Native PHY RSFEC Avalon memory-mapped register.
0x40000000 – 0x5fffffff	eCPRI IP Avalon memory-mapped register.
0x80000000 – 0x9fffffff	Design example test generator and verifier Avalon memory-mapped register.

Table 9. Address mapping when accessing through the Nios II processorOnly available for Intel^® Stratix^® 10 designs.
Address	Target
0x00100000 – 0x001fffff	IOPLL Re-configuration Avalon memory-mapped register
0x00200000 – 0x003fffff	Ethernet MAC Avalon memory-mapped register
0x00400000 – 0x005fffff	Ethernet MAC Native PHY Avalon memory-mapped register.
0x00600000 – 0x007fffff	Native PHY Reed-Solomon FEC Avalon memory-mapped register.

Access the Ethernet MAC and the Ethernet MAC Native PHY Avalon memory-mapped register using word offset instead of byte offset.

For more information on the Ethernet MAC, Ethernet MAC Native PHY Avalon memory-mapped, and eCPRI IP Avalon memory-mapped registers, refer to the respective user guides.

Table 10. Test generator and verifier Avalon memory-mapped register
Word Offset	Description	Default	Attribute
0x0001	Start send data Bit 1: PTP, non-PTP type Bit 0: O-RAN C-plane, U-plane, C-plane extension	0x00000000	RW
0x0002	Continuous packet enable	0x00000000	RW
0x0003	Clear error	0x00000000	RW
0x0004	External packets error	0x00000000	RO
0x0005	External PTP packets transmitter SOP count	0x00000000	RO
0x0006	External PTP packets transmitter EOP count	0x00000000	RO
0x0007	External miscellaneous packets transmitter SOP count	0x00000000	RO
0x0008	External miscellaneous packets transmitter EOP count	0x00000000	RO
0x0009	External receiver packets SOP count	0x00000000	RO
0x000A	External receiver packets EOP count	0x00000000	RO
0x000B	External error count	0x00000000	RO
0x000C	C-plane checker errors	0x00000000	RO
0x000D	Transmitter C-plane SOP count	0x00000000	RO
0x000E	Transmitter C-plane EOP count	0x00000000	RO
0x000F	Receiver C-plane SOP count	0x00000000	RO
0x0010	Receiver C-plane EOP count	0x00000000	RO
0x0011	Total C-plane error count	0x00000000	RO
0x0012 ⁶	Rate switch Bit 7: tile 1’b0: H-Tile 1’b1: E-Tile Bit 6:4: Ethernet rate 3’b0: 25G to 10G 3’b1: 10G to 25G Bit 0: switch rate enable You must set bit 0 and poll until bit 0 is clear for rate switching	E-tile: 0x00000080 Non E-tile: 0x00000000	RW
0x0013 ⁶	Rate switch done Bit 1: rate switch done	0x00000000	RO
0x0014	U-plane checker errors0	0x00000000	RO
0x0015	Transmitter U-plane SOP count0	0x00000000	RO
0x0016	Transmitter U-plane EOP count0	0x00000000	RO
0x0017	Receiver U-plane SOP count0	0x00000000	RO
0x0018	Receiver U-plane EOP count0	0x00000000	RO
0x0019	Total U-plane error count0	0x00000000	RO
0x001A	C-plane extension checker errors	0x00000000	RO
0x001B	Transmitter C-plane extension SOP count	0x00000000	RO
0x001C	Transmitter C-plane extension EOP count	0x00000000	RO
0x001D	Receiver C-plane extension SOP count	0x00000000	RO
0x001E	Receiver C-plane extension EOP count	0x00000000	RO
0x001F	Total C-plane extension error count	0x00000000	RO
0x0020	System configuration status Bit 31: System ready Bit 30-13: Reserved Bit 12-5: UDCOMPPARAM Bit 4: COMP_EN Bit 3: EXT_PACKET_EN Bit 2: CPLANE_EXT_EN Bit 1: CPLANE_EN Bit 0: UPLANE_EN	0x00000000	RO
0x0021 ⁷	U-plane checker errors1	0x00000000	RO
0x0022⁷	Receiver U-plane SOP count1	0x00000000	RO
0x0023 ⁷	Receiver U-plane EOP count1	0x00000000	RO
0x0024 ⁷	Total U-plane error count1	0x00000000	RO
0x0025 ⁷	eCPRI error interrupt Bit 0: eCPRI error interrupt	0x00000000	RO
0x0026	O-RAN error interrupt Bit 0: O-RAN error interrupt	0x00000000	RO
0x0027	Avalon streaming receiver U-plane error status Bit 0: Avalon streaming receiver U-plane error status	0x00000000	RO
0x0028	Avalon streaming receiver C-plane error status Bit 0: Avalon streaming receiver C-plane error status	0x00000000	RO
0x0029	Avalon streaming receiver C-plane extension error status Bit 0: Avalon streaming receiver C-plane extension error status	0x00000000	RO
0x002A	External receiver error status Bit 0: external receiver error status	0x00000000	RO

¹ This parameter setting must match Enable companding in the O-RAN IP GUI.

² These parameter settings are only applicable when you turn on Enable C-plane in the O-RAN IP GUI. When you turn off Enable C-Plane, you must set the following configuration:

ENABLE_CPLANE = 0

³ These parameter settings are only applicable when you turn on Enable companding in the O-RAN IP GUI. when you turn off Enable companding, you must set the following configurations:

ENABLE_COMPRESSION = 0
udCompMeth = 0
udIqWidth = 16

⁴ The design example ignores the C_Sectiontype parameter when yoiu turn off Enable C-plane in the O-RAN IP GUI

For C_Sectiontype = 1, the example design only supports C_NumberofSections = 6.
For C_Sectiontype = 3, the example design only supports C_NumberofSections = 2.

⁵ Only available for Intel^® Stratix^® 10 designs.

⁶ Only available for Intel^® Stratix^® 10 designs.

⁷ Only available in the example design when you turn on Enable Companding in the O-RAN IP GUI. The data width for avst_sink_u_data and avst_source_u_data ports of O-RAN IP are 128 bits when you turn on Enable Companding. For the transmitter traffic generation, the identical lower 64 bits and upper 64 bits of data are transmitted to the O-RAN IP. Then two separate checker modules validate the received output.

4. Document Revision History for the O-RAN Intel FPGA IP Design Example User Guide

Document Version	Intel^® Quartus^® Prime Version	IP Version	Changes
2020.11.30	20.3	1.1.0	Initial release.