F-Series FPGA Development Kit is a
complete design environment that includes both hardware and software you need to develop
FPGA designs. The board provides a wide range of
peripherals and memory interfaces to facilitate the development of
F-Series FPGA designs.
Table 1. Ordering Information
Development Kit Version
Device Part Number
Serial Number Identifier
Agilex F-Series FPGA Development Kit (ES -3V)
Agilex F-Series FPGA Development Kit (ES -2V)
Note: The -3V and -2V versions of the
F-Series FPGA Development Kits use different power
solutions for VCC core. Refer to the power tree diagrams in Power for additional information.
1.1. Block Diagram
Development Kit Block Diagram
Note: Golden Software Reference Design for HPS (GSRD) is unavailable for this
1.2. Box Contents
F-Series FPGA Development board,
DDR4 DIMM module, USB2.0 Micro cable, Ethernet cable, 240W power adapter and
NA/EU/JP/UK cords, ATX power convert cable - 24pin to
Note: Only 2 DIMM modules are provided with each development kit.
1.3. Operating Conditions
Table 2. Recommended Operating Conditions
Ambient operating temperature range
0 °C to 45 °C
ICC load current
ICC load transient percentage
FPGA maximum power supported by active heatsink/fan
When handling the board, it is important to observe static discharge precautions.
Note: Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Note: This development kit should not be operated in a vibration environment.
2. Getting Started
2.1. Software and Driver Installation
Quartus® Prime design software is a
multiplatform design environment that easily adapts to your specific needs in all
phases of FPGA, CPLD and SoC designs. The
software delivers the highest performance and productivity for Intel FPGAs, CPLDs,
Quartus® Prime Pro Edition software is optimized
to support the advanced features in next-generation FPGAs and SoCs with the
Arria® 10 and
Cyclone® 10 GX device families.
F-Series FPGA Development Kit
Intel® FPGA Download Cable circuits for FPGA
MAX® 10 programming. However, for the
host computer and board to communicate, you must install the
Intel® FPGA Download Cable driver on the host computer. Installation
instructions for the
Intel® FPGA Download Cable driver for your
operating system are available on the
Intel® SoC EDS is a
comprehensive software tool suite for embedded software development on
Intel® SoC devices. It contains development
tools, utility programs, run-time software, and application examples to expedite
firmware and application software of SoC embedded systems.
Note: Please use
Quartus® Prime 19.4 Pro Edition or later for this
development kit test and debug.
For more information and steps to install the
Intel® SoC EDS Tool Suite refer to the links
Refer to the
F-Series FPGA Development Kit Quick Start Guide to learn how the
development kit works by default after power up.
2.3. Design Examples
Unzip the install package which includes board design files, documents
and examples directories. The table below lists the file directory names and a
description of their contents.
Table 3. Installed Development Kit Directory Structure
Description of Directory Contents
Contains schematics, layout, assembly and
bill of material board design files. Use these files as a
starting point for a new prototype board design
Contains the development kit documentation –
quick start guides and user guide
Board Test System: BTS GUI, Power
GUI and Clock GUI
Golden Top project for pinout
Design Examples: Memory, XCVR, GPIO
and PCIe Gen4
Contains the instructions on how to program
Contains the instructions on how to program
3. Power Up the Development Kit
The instructions in this chapter explain how to setup the
F-Series FPGA Development Kit for specific use cases.
3.1. Default Settings
F-Series FPGA Development Kit ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be correctly configured with the default settings, follow the instructions
in the factory default switch settings table given below to return the board to its
factory settings before proceeding forward.
Note: X refers to Don't Care in the table below.
Table 4. Factory Default Switch Settings
Configuration mode setting bits
By default, AS -> FAST mode
the resource of the System
MAX® 10 JTAG
Enable Si5341’s outputs
Power up Si52202
Enable UART interface
Enable all the I2C level shifter.
Intel® FPGA Download Cable as JTAG
master when external JTAG header is absent
MAX® 10 in JTAG chain;
Bypass FPGA HPS in JTAG chain
Enable FPGA in JTAG chain
SW5.5 to SW5.6
Power off the board
PCIe x16 mode is selected
Select local clock as PCIe reference clock
3.2. Power Up
Board runs as a standalone work bench
Use the provided 240 W power adapter to supply power through J16. After power adapter
is plugged into J16 and SW5 is set to the ON position, one blue LED
(D8) illuminates, indicating that the board powered up successfully.
Board runs in PCIe socket as an add-in card
Use the provided 240 W power adapter to supply power through J16. After the
power adapter is plugged into J16 and the board is plugged into the PCIe
socket of server/PC, the board will power up when the server/PC is powered. One blue
LED (D8) illuminates, indicating that the board powered up successfully.
3.3. Control on-board clock through Clock Controller GUI
The Clock Controller application can change on-board Si5341
programmable PLLs to any customized frequency between 10 MHz and 750 MHz for
differential output and 10 MHz to 350 MHz for LVCMOS single-ended output.
The Clock Controller application (ClockControl.exe) runs as a stand-alone application and resides in
The Clock Controller communicates with the System
MAX® 10 device through either USB port J13 or 10 pin JTAG header J14. Then System
MAX® 10 controls these programmable clock parts
through a 2-wire I2C bus.
Note: You cannot run
the stand-alone Clock Controller application when the BTS or Power Monitor GUI
is running at the same time.
Figure 2. Clock Controller GUI
The following sections describe the Clock Controller buttons
Reads the current frequency setting for the oscillator associated
with the active tab.
Sets the frequency for the oscillator associated with the active tab
back to its default value. This can also be accomplished by power cycling the
Sets the programmable oscillator frequency for the selected clock to
the value in the CLKx output controls for the
Si5338. Frequency changes might take several milliseconds to take effect. You might
see glitches on the clock during this time. Intel recommends resetting the FPGA
logic after changing frequencies.
Si5341 has a two-time writable
You can generate the register list from the
it into Si5341 to update the settings of the NVM.
3.4. Control on-board power regulator through Power GUI
The Power Monitor application reports most power rails voltage,
current, and power information on the board. It also collects temperature from FPGA
die, power modules and diodes assembled on PCB.
Power GUI communicates with System
MAX® 10 through either USB port J13 or J14. System
MAX® 10 monitors and controls power regulator,
temperature/voltage/current sensing chips through a 2-wire serial bus.
The Power Monitor application (PowerMonitor.exe) runs as a stand-alone application and resides in
Note: You cannot run
the stand-alone Power Monitor application when the BTS or the Clock Controller
GUI is running at the same time.
F-Series FPGA Development Kit includes a design example and an
application called the Board Test System (BTS) to test the functionality of this board.
4.1. Test the functionality of the Development Kit
Note: This section will be updated in a future release.
4.2. BTS Test Areas
BTS checks for hardware fault before you can use the board. If one or more BTS test items
fail, it implies either a wrong hardware setting or hardware fault on specific
Note: This section will be expanded and updated in a future release.
4.3. Identify Test Pass/Fail based on BTS GUI test status
Plug the DDR4 DIMM module which is shipped alone with this development
kit in J1/J2/J3/J4.
GUI only supports fabric memory interfaces namely DDR4 #0, #2 and
QSFPDD/QSFP28 loopback module in J5/J6 before you configure QSFPDD NRZ
example build through BTS GUI. The pseudo random bitstream (PRBS) traffic is running
at 25 Gbps for NRZ build, but you can manually try it out PAM4 @50 Gbps with hard
PRBS pattern with temporary PAM4 build in installer package.
5. Development Kits Hardware and Configuration
F-Series FPGA Development Kit only supports ASx4 configuration
mode on the board. You need to change the hardware setting and/or re-program system images for
The table below show which configuration mode it supports:
Table 5. Supported Configuration Mode
AS - Fast Mode (Default Setting)
AS - Normal Mode
5.1. Configure the FPGA and access HPS Debug Access Port by JTAG
JTAG access doesn’t rely on SW1 settings and
MAX® 10 image.
Plug the USB cable to J13 or
Intel® FPGA Download Cable to J14.
programmer, system console to configure
FPGA SDM, system
MAX® 10 and PCIe JTAG nodes.
Development Studio 5* (DS-5*) Intel SoC FPGA Edition to connect to and communicate
with the HPS Debug Access Port (DAP) through the same JTAG interface.
Note: By default, HPS
and FPGA SDM JTAG nodes are chained together internally. SW4
bypass or enable both nodes at the same time.
5.2. Configure the FPGA device by AS modes (Default Mode)
Default SW1 setting and system
MAX® 10 image support AS configuration mode. Power on and observe FPGA
F-Series FPGA Development Kit also
some HPS interfaces. You can demonstrate the following HPS functions on this board:
10/100/1000Mbps ethernet PHY: U7_KSZ9031 and RJ45 connector
USB UART for communication port: micro USB connector
SD socket: J11
eMMC on board: U16_MTFC8GAKAJCN-4M
Mictor Connector for debug: J12
6. Custom Projects for the Development Kit
6.1. Add SmartVID settings in the QSF file
FPGA assembled on this
development kit enables SmartVID feature by default.
You must put the constraints listed below into your project QSF file
Quartus® Prime from generating an error due to
incomplete SmartVID settings.
Open your project QSF file and copy and paste constraint scripts
listed below into the file. You must ensure that there are no other similar settings
with different values.
You can use the Golden Top project as the starting point. It contains
the constraints, pin locations, defines I/O standards, direction and general
Note: The Golden Top project is slightly different from the
F-Series Development Kit's -3V version to -2V version, please to refer to
corresponding golden top project in installer package for more information.
A. Development Kit Components
A.1. Intel Agilex FPGA
F2486A FBGA Package 55 mm x 42.5 mm
9200 18x19 Multipliers
36 Mb eSRAM
16 x 28 Gbps NRZ transceivers (E-tile)
16 x 17.4 Gbps NRZ transceivers (P-tile)
1x PCIe Gen4 x16 Hard IP blocks
1x 100G Ethernet MAC Hard IP blocks
A.2. Configuration Support
This development kit supports two configuration methods.
A dip switch
is used to select between JTAG only mode and ASx4 configuration mode by manipulating
the MSEL pins.
ASx4 Mode. MT25QU02GCBB3E12-1SIT is a QSPI FLASH on board to
support ASx4 configuration mode.
JTAG via 10-pin header for connecting an Intel
standard UB2/UB1 dongle. The header shall be a right angle shrouded
type connector and it will be accessible through the PCIe
Intel® FPGA Download Cable
A.2.1. JTAG Chain and Header
The figure below shows the JTAG Chain connections. An option to bypass the
FPGA during board bring up is provided but not shown in the
Figure 4. JTAG chain on the Development Kit
The JTAG chain allows programming of the
FPGA and the
MAX® 10 CPLD devices using the
Intel® FPGA Download Cable II dongle. The dongle can be
used to program both the
MAX® 10 CPLD via the external 2x5pin 0.1” programming
header. This header
a shrouded right angle connector and is designed to be accessible from the PCIe
bracket side. This avoids having to remove the PC case to program the device when
the board is installed in a closed system.
A.2.2. On-board Intel FPGA Download Cable II
Intel® FPGA Download Cable II Block
Intel® FPGA Download Cable II core for USB-based configuration of
FPGA is implemented using a TYPE B USB connector, a
CY7C68013A USB2 PHY device, and a
MAX® 10 device. This allows for
the configuration of the
FPGA using a USB cable directly
connected to a PC running
Quartus® Prime software without requiring the
Intel® FPGA Download Cable II dongle.
USB data to interface with the
JTAG port. Four LEDs are provided to indicate
Intel® FPGA Download Cable II activity. Two of them monitor the JTAG data-in and
data-out signals; the remaining two monitor System Console activity. The embedded
Intel® FPGA Download Cable is automatically disabled when
Intel® FPGA Download Cable II dongle is connected to
the JTAG chain.
There are three clock devices in the
F-Series FPGA Development Kit: Si5341,Si52202 and Si510.
Si5341 provides most of clocks to the
FPGA including reference clocks for memory interfaces, QSFP-DD,
and the FPGA SDM/fabric core.
Si52202 provides the dedicated reference clock as an local clock
option of PCIe Gen4 by choosing in clock buffer 9DML0441AKILF. Another input of the
clock buffer is from PCIe Golden Finger as a system clock of PCIe Gen4.
Si510 provides a 50 MHz clock to System
MAX® 10 and Power
Figure 6. Clocking in the
F-Series FPGA Development Kit
A.4. Memory Interfaces
F-Series FPGA Development
Kit has four channels of 288 pin DDR4 DIMM 72-bit interfaces: DDR4 DIMM CH0, DDR4
DIMM CH1,DDR4 DIMM CH2 and DDR4 DIMM CH3.
DDR4 DIMM CH1 is designed for HPS dedicated applications. The other
three memory channels are for FPGA general usage and support both DDR4 and
DDR4 DIMM CH0 is located in FPGA Bank 3A and 3B. It supports
both DDR4 and DDR-T modules.
DDR4 DIMM CH1 is located in FPGA Bank 3C and 3D. It only
supports DDR4 module.
DDR4 DIMM CH2 is located in FPGA Bank 2A and 2B. It supports
both DDR4 and DDR-T modules.
DDR4 DIMM CH3 is located in FPGA Bank 2C and 2D. It supports
both DDR4 and DDR-T modules.
A.5. Transceiver Interfaces
Two transceiver banks are present on the
F-Series FPGA Development Kit
Bank 9A is used for two standard QSFP-DD optical modules (J5
and J6) and support up to 200 Gbps with hard IP for each QSFP-DD module
Bank 10A is fully compliant with PCIe Gen4 x16 and are
connected to the golden finger J7 in this PCIe add-in card
A.6. HPS Interface
FPGA Development Kit enables
the HPS function and supports several HPS interfaces:
RJ 45 supporting Ethernet 10/100/1000 Mbps by RGMII
UART port by USB (Micro) connector
Micro SD card socket
Mictor Connector for HPS JTAG
eMMC (8 GB x 8)
Note: Golden Software Reference Design for HPS (GSRD) is not available for this
A.7. General Input and Output
Table 6. SW1 Pin Connections
Mode select 0 for configuration
Mode select 1 for configuration
Mode select 2 for configuration
Table 7. SW2 Pin Connections
USB MAX JTAG SEL
JTAG select External JTAG HEADER.
JTAG select USB PHY.
ON = Disable SI5341’s outputs
OFF = Enable SI5341’s outputs
SI52202 Power Down
ON = Power down SI52202
OFF = Power up SI52202
ON = Disable UART
OFF = Enable UART
Table 8. SW3 Pin Connections
FPGA I2C Enable
ON = Isolate FPGA from main I2C chain. OFF = connect FPGA to
main I2C chain.
HPS I2C Enable
ON = Isolate HPS from main I2C chain. OFF = connect HPS to
main I2C chain.
Main PMBUS Enable
ON = Isolate power module of VCC_core from main I2Cchain.
OFF= connect power module of VCC_core to main I2C chain.
ON = Isolate power module of VCC_core from SDMPMBUS.
OFF= connect power module of VCC_core to SDM PMBUS.
Table 9. SW4 Pin Connections
JTAG Input Source
ON = select PCIe edge as JTAG master when external JTAG is
OFF = select On-Board
Intel® FPGA Download Cable as JTAG master
when external JTAG is absent.
Power Max10 Bypass
ON = bypass Power Max10 in the JTAG chain.
ON = bypass HPS in the JTAG chain.
OFF = enable HPS in the JTAG chain.
ON = bypass FPGA in the JTAG chain.
OFF = enable FPGA in the JTAG chain.
Table 10. SW5 Pin Connections
SW5.5 to SW5.4
Power ON the board
SW5.5 to SW5.6
Power OFF the board
Table 11. SW6 Pin Connections
PCIe EP Present x16
ON = x16 select
OFF = x16 deselect
PCIe EP Present x8
ON = x8 select
OFF = x8 deselect
PCIe EP Present x4
ON = x4 select
OFF = x4 deselect
PCIe EP Present x1
ON = x1 select
OFF = x1 deselect
Table 12. SW7 Pin Connections
ON = select SI52202 as clock source for PCIe Gen4
OFF = select PCIe edge as clock source for PCIe Gen4
Table 13. Buttons on the Development Kit
HPS cold reset
Cold reset to HPS
Fabric core reset
PCIe Hard IP reset
HPS warm reset
Warm reset to HPS
Intel® FPGA Download Cable Reset
Table 14. LEDs on the Development Kit
Schematic Signal Name
FPGA Pin Number
The power to the
Development Kit is provided from the PCIe slot (up to 75 W) and a secondary
Auxiliary 2x4 PCIe power connector capable of an additional 150 W. The development
kit does not power up until both the +12 V rails from the PCIe slot and the
secondary auxiliary PCIe power connector are detected.
The development kit can also operate as a stand-alone bench top board
for laboratory evaluation when an external 12 V power supply is connected to its 2x4
PCIe power connector. In this mode, the external supply will supply the total 240 W
power for both the VCC core and other power rails on the board. An on-board slide
switch is used to start the power for stand-alone mode.
MAX® 10 power sequencer is used to
manage the Power-Up sequencing needed to meet the
FPGA Power Sequencing requirements. No Power-down sequencing is
required on the
Figure 7. Power Tree Block
Figure 8. Power Tree Block Diagram (-3V Version)
A.8.1. Power Sequence
The Power Sequencing function is implemented by using an
device that monitors the "Power_Good" signals of power modules.
Power measurement is provided for your evaluation to help correlate actual power versus EPE
tool. Voltage measurements will be provided for eight FPGA power rails by using an
8-channel ADC embedded in Power
MAX® 10. Current measurements
used by the internal measurement on power modules which are digital power module and
support PMBUS access.
current for the four groups of power rails can be read through Power Monitor GUI.
The power rails have the current monitor as below:
VCC and VCCP
VCCH, VCC_HSSI, VCCRT_GXER, and VCCRT_GXPL
VCCPT, VCCH_GXPL, and VCCA_PLL
A.8.3. Temperature Monitor
8-channel temperature sensor device, MAX6581, monitors the temperature of the
FPGA including fabric core and transceivers.
Temperature monitoring of the board ambient is also done by
MAX6581 with its embedded temperature sensor diode.
MAX® 10 System Controller by a 2-wire I2C interface. Additionally, the OVERTEMPn and ALERTn signals from the
to the Power
MAX® 10 CPLD to allow it to
immediately sense a temperature fault condition if the board gets too hot.
An over temperature warning LED (Red-colored) is connected to the
MAX® 10 device so software can indicate a visual over
the temperature fault condition and that the fan should be running. The fan will be
controlled by the OVERTEMP_OUT signal from the
MAX® 10 and can be controlled by software.
Temperature fault set points can be programmed into the
the I2C bus through the System
Figure 9. MAX6581 Temperature Sensor Circuit
B. Additional Information
B.1. Safety and Regulatory Information
ENGINEERING DEVELOPMENT PRODUCT - NOT FOR RESALE OR LEASE
This development kit is intended for laboratory development and
engineering use only.
This development kit is designed to allow:
Product developers and system engineers to evaluate
electronic components, circuits, or software associated with the development
kit to determine whether to incorporate such items in a finished
Software developers to write software applications for use
with the end product.
This kit is not a finished product and when assembled may not be
resold or otherwise marketed unless all required Federal Communications Commission
(FCC) equipment authorizations are first obtained.
Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful
Unless the assembled kit is designed to operate under Part 15, Part
18 or Part 95 of the United States Code of Federal Regulations (CFR) Title 47, the
operator of the kit must operate under the authority of an FCC licenseholder or must
secure an experimental authorization under Part 5 of the United States CFR Title
Safety Assessment and CE mark requirements have been completed,
however, other certifications that may be required for installation and operation in
your region have not been obtained.
B.1.1. Safety Warnings
Power Supply Hazardous Voltage
AC mains voltages are present within the power supply assembly. No
user serviceable parts are present inside the power supply.
Power Connect and Disconnect
The AC power supply cord is the primary disconnect device from mains
(AC power) and used to remove all DC power from the board/system. The socket outlet
must be installed near the equipment and must be readily accessible.
System Grounding (Earthing)
To avoid shock, you must ensure that the power cord is connected to a
properly wired and grounded receptacle. Ensure that any equipment to which this
product will be attached is also connected to properly wired and grounded
Power Cord Requirements
The connector that plugs into the wall outlet must be a
grounding-type male plug designed for use in your region. It must have marks showing
certification by an agency in your region. The connector that plugs into the AC
receptacle on the power supply must be an IEC 320, sheet C13, female connector. If
the power cord supplied with the system does not meet requirements for use in your
region, discard the cord and do not use it with adapters.
Do not connect/disconnect any cables or perform
installation/maintenance of this product during an electrical storm.
Risk of Fire
To reduce the risk of fire, keep all flammable materials a safe
distance away from the boards and power supply. You must configure the development
kit on a flame retardant surface.
B.1.2. Safety Cautions
Surfaces and Sharp Edges. Integrated Circuits and heat sinks may be hot if the
system has been running. Also, there might be sharp edges on some boards.
Contact should be avoided.
Thermal and Mechanical Injury
Certain components such as heat sinks, power regulators, and
processors may be hot. Heatsink fans are not guarded. Power supply fan may be
accessible through guard. Care should be taken to avoid contact with these
Maintain a minimum clearance area of 5 centimeters (2 inches) around
the isde, front and back of the board for cooling purposes. Do not block power
supply ventilation holes and fan.
Electro-Magnetic Interference (EMI)
This equipment has not been tested for compliance with emission
limits of FCC and similar international regulations. Use of this equipment in a
residential location is prohibited. This equipment generates, uses and can radiate
radio frequency energy which may result in harmful interference to radio
communications. If this equipment does cause harmful interfence to radio or
television reception, which can be determined by turning the equipment on and off,
the user is required to take measures to eliminate this interference.
Telecommunications Port Restrictions
The wireline telecommunications ports (modem, xDSL, T1/E1) on this
product must not be connected to the Public Switched Telecommunication Network
(PSTN) as it might result in disruption of the network. No formal telecommunication
certification to FCC, R&TTE Directive, or other national requirements have been
Electrostatic Discharge (ESD) Warning
A properly grounded ESD wrist strap must be worn during
operation/installation of the boards, connection of cables, or during installation
or removal of daughter cards. Failure to use wrist straps can damage components
within the system.
Attention: Please return this product to Intel
for proper disposition. If it is not returned, refer to local environmental
regulations for proper recycling. Do not dispose of this product in unsorted
B.2. Compliance Information
CE EMI Conformity Caution
This development board is delivered conforming to relevant standards
mandated by Directive 2014/30/EU. Because of the nature of programmable logic
devices, it is possible for the user to modify the development kit in such a way as
to generate electromagnetic interference (EMI) that exceeds the limits established
for this equipment. Any EMI caused as a result of modifications to the delivered
material is the responsibility of the user of this development kit.
C. Revision History
Table 16. Revision History of the
FPGA Development Kit User Guide