Intel offers separate MAC and PHY IPs for the 10M to 1G Multi-rate Ethernet subsystems to ensure flexible implementation. You can instantiate the Low Latency Ethernet 10G MAC Intel^® FPGA IP with 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel^® Arria^® 10 1G/10GbE and 10GBASE-KR PHY, or XAUI PHY and Intel^® Arria^® 10 Transceiver Native PHY to cater different design requirements.

This configuration provides an XGMII to Low Latency Ethernet 10G MAC Intel^® FPGA IP and implements a single-channel 10.3 Gbps PHY providing a direct connection to an SFP+ optical module using SFI electrical specification.

Intel offers two 10GBASE-R Ethernet subsystem design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel^® FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kits.

The XAUI PHY is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification.

You can obtain the reference design for the 10GbE subsystem implemented using Low Latency Ethernet 10G MAC and XAUI PHY Intel^® FPGA IPs from Design Store. The design supports functional simulation and hardware testing on designated Intel development kit.

The 1G/10GbE and 10GBASE-KR PHY Intel^® Arria^® 10 FPGA IP implement a single-channel 10Mbps/100Mbps/1Gbps/10Gbps serial PHY. The designs provide a direct connection to 1G/10GbE dual speed SFP+ pluggable modules, 10M–10GbE 10GBASE-T and 10M/100M/1G/10GbE 1000BASE-T copper external PHY devices, or chip-to-chip interfaces. These IP cores support reconfigurable 10Mbps/100Mbps/1Gbps/10Gbps data rates.

Intel offers dual-speed 1G/10GbE and multi-speed 10Mb/100Mb/1Gb/10GbE design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel^® FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kit.

The multi-speed Ethernet subsystem implementation using 1G/10GbE or 10GBASE-KR PHY Intel^® Arria^® 10 FPGA IP design requires manual SDC constraints for the internal PHY IP clocks and clock domain crossing handling. Refer to the altera_eth_top.sdc file in the design example to know more about the required create_generated_clock, set_clock_groups and set_false_path SDC constraints.

The 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel^® FPGA IP for Intel^® Arria^® 10 devices implements a single-channel 1G/2.5G/5G/10Gbps serial PHY. The design provides a direct connection to 1G/2.5GbE dual speed SFP+ pluggable modules, MGBASE-T and NBASE-T copper external PHY devices, or chip-to-chip interfaces. These IPs support reconfigurable 1G/2.5G/5G/10Gbps data rates.

Intel offers dual-speed 1G/2.5GbE, multi-speed 1G/2.5G/10GbE MGBASE-T, and multi-speed 1G/2.5G/5G/10GbE MGBASE-T design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel^® FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kit.

For multi-speed 1G/2.5GbE and 1G/2.5G/10GbE MBASE-T Ethernet subsystem implementations using 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP, Intel recommends you copy the transceiver reconfiguration module (alt_mge_rcfg_a10.sv) provided with the design example. This module reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.

The multi-speed 1G/2.5GbE and 1G/2.5G/10GbE MBASE-T Ethernet subsystem implementation also requires manual SDC constraints for the internal PHY IP clocks and clock domain crossing handling. Refer to the altera_eth_top.sdc file in the design example to know more about the required create_generated_clock, set_clock_groups and set_false_path SDC constraints.