Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide

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UG-20040 | 2017.11.06

Quick Start Guide

The Intel^® Arria^® 10 or Intel^® Cyclone^® 10 Hard IP for PCI Express^® IP core includes a programmed I/O (PIO) design example to help you understand usage. The PIO example transfers memory from a host processor to a target device. It is appropriate for low-bandwidth applications. The design example includes an Avalon-ST to Avalon-MM Bridge. This component translates the TLPs received on the PCIe^® link to Avalon-MM memory reads and writes to the on-chip memory.

This design example automatically creates the files necessary to simulate and compile in the Quartus^® Prime software. You can download the compiled design to the Intel^® Arria^® 10 GX FPGA Development Kit. The design examples cover a wide range of parameters. However, the automatically generated design examples do not cover all possible parameterizations of the PCIe IP Core. If you select an unsupported parameter set, generations fails and provides an error message.

Note: Intel^® Cyclone^® 10 GX dvelopment kits are not yet available.

In addition, many static design examples for simulation are only available in the <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 and <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/c10 directories.

Figure 1. Development Steps for the Design Example

Directory Structure

Figure 2. Directory Structure for the Generated Design Example

Design Components for the Avalon -MM Endpoint

Figure 3. Block Diagram for the Platform Designer PIO Design Example Simulation Testbench

Generating the Design

Launch Platform Designer.
The Open System dialog box appears.
Click New to specify a Quartus Prime project name and custom IP variation name for your design. Then, click Create.
In the IP Catalog, locate and select Intel^® Arria^® 10 or Intel^® Cyclone^® 10 Hard IP for PCI Express. The parameter editor appears.
On the IP Settings tabs, specify the parameters for your IP variation.
In the Connections panel, make the following dummy connections:
1. coreclkout_hip to refclk.
2. rxm_bar0 to txs slave interface.
These dummy connection are removed when you generate the design example. They are necessary because Platform Designer system validation requires the refclk to be connected. Platform Designer also determines the size of the Avalon^® -MM BAR master from its connection to an Avalon^® -MM slave device. When you generate the example design, these connections are removed.
Remove the clock_in and reset_in components that were instantiated by default.
On the Example Design tab, the PIO design is available for your IP variation.
For Example Design Files, select the Simulation and Synthesis options.
For Generated HDL Format, only Verilog is available.
For Intel^® Arria^® 10 Target Development Kit select the FPGA Development Kit option.

Note: Intel^® Cyclone^® 10 GX FPGA development kits are not available at this time.
Click Generate Example Design. The software generates all files necessary to run simulations and hardware tests on the Intel^® Arria^® 10 FPGA Development Kit.

Simulating the Design

Figure 4. Procedure

Change to the testbench simulation directory.
Run the simulation script for the simulator of your choice. Refer to the table below.
Analyze the results.

Table 1. Steps to Run Simulation
Simulator	Working Directory	Instructions
ModelSim^®	`<example_design>`/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/	do msim_setup.tcl ld_debug run -all A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
VCS^®	<example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs	sh vcs_setup.sh USER_DEFINED_SIM_OPTIONS="" A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
NCSim^®	`<example_design>`/pcie_example_design_tb/pcie_example_design_tb/sim/cadence	sh ncsim_setup.sh USER_DEFINED_SIM_OPTIONS="" A successful simulation ends with the following message, "Simulation stopped due to successful completion!"

Figure 5. Partial Transcript from Successful Avalon-ST PIO Simulation Testbench

Compiling and Testing the Design in Hardware

Figure 6. Procedure

Figure 7. Software Application to Test the PCI Express Design Example on the Intel^® Arria^® 10 GX FPGA Development Kit. A software application running on a Windows PC performs the same hardware test for all of the PCI Express Design Examples.

The software application to test the PCI Express Design Example on the Intel^® Arria^® 10 GX FPGA Development Kit is available on both 32- and 64-bit Windows platforms. This program performs the following tasks:

Prints the Configuration Space, lane rate, and lane width.
Writes 0x00000000 to the specified BAR at offset 0x00000000 to initialize the memory and read it back.
Writes 0xABCD1234 at offset 0x00000000 of the specified BAR. Reads it back and compares.

If successful, the test program displays the message 'PASSED'

Follow these steps to compile the design example in the Quartus Prime software:

Launch the Quartus Prime software and open <example_design>pcie_example_design.qpf.
On the Processing > menu, select Start Compilation.
The timing constraints for the design example and the design components are automatically loaded during compilation.

Follow these steps to test the design example in hardware:

In the <example_design>/software/windows/interop directory, unzip Altera_PCIe_Interop_Test.zip.
Note: You can also refer to readme_Altera_PCIe_interop_Test.txt file in this same directory for instructions on running the hardware test.
Install the Intel^® FPGA Windows Demo Driver for PCIe on the Windows host machine, using altera_pcie_win_driver.inf.
Note: If you modified the default Vendor ID or Device ID specified in the component GUI, you must also modify them in altera_pcie_win_driver.inf.
1. In the <example_design> directory, launch the Quartus Prime software and compile the design (Processing > Start Compilation).
2. Connect the development board to the host computer.
3. Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).
4. Open the Windows Device Manager and scan for hardware changes.
5. Select the Intel^® FPGA listed as an unknown PCI device and point to the appropriate 32- or 64-bit driver (altera_pice_win_driver.inf) in the Windows_driver directory.
6. After the driver loads successfully, a new device named Altera PCI API Device appears in the Windows Device Manager.
7. Determine the bus, device, and function number for the Altera PCI API Device listed in the Windows Device Manager.
  1. Expand the tab, Altera PCI API Driver under the devices.
  2. Right click on Altera PCI API Device and select Properties.
  3. Note the bus, device, and function number for the device. The following figure shows one example.
  Figure 8. Determining the Bus, Device, and Function Number for New PCIe Device
In the <example_desing/software/windows/interop/Altera_PCIe_Interop_Test/Interop_software directory, click Alt_Test.exe.
When prompted, type the bus, device, and function numbers and select the BAR number (0-5) you specified when parameterizing the IP core.
Note: The bus, device, and function numbers for your hardware setup may be different.
The test displays the message, PASSED, if the test is successful.

Note: Intel^® Cyclone^® 10 GX FPGA development kits are not available at this time.

Design Example Description

Creating a Signal Tap Debug File to Match Your Design Hierarchy

For Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices, the Intel^® Quartus^® Prime software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a Signal Tap file with probe points matching your design hierarchy.

The Intel^® Quartus^® Prime software stores these files in the <IP core directory>/synth/debug/stp/ directory.

Synthesize your design using the Intel^® Quartus^® Prime software.

To open the Tcl console, click View > Utility Windows > Tcl Console.
Type the following command in the Tcl console:
source <IP core directory>/synth/debug/stp/build_stp.tcl
To generate the STP file, type the following command:
main -stp_file <output stp file name>.stp -xml_file <input xml_file name>.xml -mode build
To add this Signal Tap file (.stp) to your project, select Project > Add/Remove Files in Project. Then, compile your design.
To program the FPGA, click Tools > Programmer.
To start the Signal Tap Logic Analyzer, click Quartus Prime > Tools > Signal Tap Logic Analyzer.
The software generation script may not assign the Signal Tap acquisition clock in <output stp file name>.stp. Consequently, the Intel^® Quartus^® Prime software automatically creates a clock pin called auto_stp_external_clock. You may need to manually substitute the appropriate clock signal as the Signal Tap sampling clock for each STP instance.
Recompile your design.
To observe the state of your IP core, click Run Analysis.
You may see signals or Signal Tap instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances. They are present because software generates wider buses and some instances that your design does not include.

Intel Arria 10 or Intel Cyclone 10 Development Kit Conduit Interface

The Intel^® Arria^® 10 or Intel^® Cyclone^® 10 Development Kit conduit interface signals are optional signals that allow you to connect your design to the Intel^® Arria^® 10 or Intel^® Cyclone^® 10 FPGA Development Kit. Enable this interface by selecting Enable Intel^® Arria^® 10 FPGA Development Kit connection on the Configuration, Debug, and Extension Options tab of the component GUI. The devkit_status output port includes signals useful for debugging. Intel^® Cyclone^® 10 GX development kits are not currently available.

Table 2. The Intel^® Arria^® 10 or Intel^® Cyclone^® 10 Development Kit Conduit Interface
Signal Name	Direction	Description
`devkit_status[255:0]`	Output	The `devkit_status[255:0]` bus comprises the following status signals : `devkit_status[1:0]:` `current_speed` `devkit_status[2]:` `derr_cor_ext_rcv` `devkit_status[3]:` `derr_cor_ext_rpl` `devkit_status[4]:` `derr_err` `devkit_status[5]:` `rx_par_err` `devkit_status[7:6]:` `tx_par_err` `devkit_status[8]:` `cfg_par_err` `devkit_status[9]:` `dlup` `devkit_status[10]:` `dlup_exit` `devkit_status[11]:` `ev128ns` `devkit_status[12]:` `ev1us` `devkit_status[13]:` `hotrst_exit` `devkit_status[17:14]:` `int_status[3:0]` `devkit_status[18]:` `l2_exit` `devkit_status[22:19]:` `lane_act[3:0]` `devkit_status[27:23]:` `ltssmstate[4:0]` `devkit_status[35:28]:` `ko_cpl_spc_header[7:0]` `devkit_status[47:36]:` `ko_cpl_spc_data[11:0]` `devkit_status[48]:` `rxfc_cplbuf_ovf` `devkit_status[49]:` `reset_status` `devkit_status[255:50]:` `Reserved`
`devkit_ctrl[255:0]`	Input	The `devkit_ctrl[255:0]` bus comprises the following status signals. You can optionally connect these pins to an on-board switch for PCI-SIG compliance testing, such as bypass compliance testing. `devkit_ctrl[0]:` `test_in[0] is typically set to 1'b0` `devkit_ctrl[4:1]:` `test_in[4:1] is typically set to 4'b0100` `devkit_ctrl[6:5]:` `test_in[6:5] is typically set to 2'b01` `devkit_ctrl[31:7]:` `test_in[31:7] is typically set to 25'h3` `devkit_ctrl[63:32]:` `is typically set to 32'b0` `devkit_ctrl[255:64]:` `is typically set to 192'b0`

Document Revision History for Intel Arria 10 and Intel Cyclone 10 Avalon -ST Hard IP for PCIe Design Example User Guide

Date	Version	Changes Made
2017.11.06	17.1	Made the following changes: Added support for Intel^® Cyclone^® 10 GX devices. Added explanation for the dummy connections made in the Generating the Design topic.
2017.03.15	16.1.1	Rebranded as Intel.
2016.10.31	16.1	Initial release.

Date

Version

Changes Made

2017.11.06

17.1

Made the following changes:

Added support for Intel^® Cyclone^® 10 GX devices.
Added explanation for the dummy connections made in the Generating the Design topic.

2017.03.15

16.1.1

Rebranded as Intel.

2016.10.31

16.1

Initial release.