This application note showcases the synchronization of two ×8-lane
Stratix® 10 FPGA JESD204B RX IP cores to interoperate with the
12-bit, 16-lane Texas Instruments (TI) ADC12DJ3200 Evaluation Module (EVM) running at 6.4
gigabits per second (Gbps) per lane connected through FMC+ port A connector.
TI wideband ADC12DJ3200 device is the 12-bit converter which is capable of
operating at up to 3.2 gigasamples per second (Gsps) in dual channel mode or 6.4 Gsps in an
interleaved single channel mode. This design is programmed to run at the fastest sample rate
of 6.4 Gsps in single channel mode, where this mode effectively interleaves the two
analog-to-digital converter (ADC) channels together to form a single channel ADC at twice the
Applications such as high-density phased array radar, satellite communications, 5G systems,
and medical imaging are driving the need for increased data throughput, higher bandwidth, and
lower power. Small package size and lower PCB cost are preferred in these applications.
This reference design provides the following key features:
Two 8-lane simplex RX JESD204B IP cores interoperate with the ADC12DJ3200
EVM through the
Stratix® 10 Transceiver Signal Integrity
Development Kit FMC+ port A running at 6.4 Gbps per lane. The
JESD204B IP core has the following parameters:
The LMK04828 clock generator on the ADC12DJ3200 EVM provides 160 MHz for
I/O PLL core reference clock and 160 MHz for transceiver CDR reference clock. These clocks
are transmitted from a single clock chip through the FMC+ port A to the core reference clock
pin and the dedicated transceiver pin at the FPGA. The LMK04828 also provides a clock to
LMX2582, where the LMX2582 synthesizer generates a 3,200 MHz ADC sampling clock.
The I/O PLL on the FPGA generates link clock and frame clock. The IP
cores, RX transport layers, and deterministic latency measurement block are sourced from
link clock. The frame clock is supplied to RX transport layers, test pattern checkers, and
any application layer.
The LMK04828 clock chip generates continuous SYSREF signal for the RX JESD204B IP cores at the FPGA and the ADC12DJ3200
The deterministic latency measurement block measures the number of link
clock counts between the start of combined SYNC_N
deassertion output from the two JESD204B IP cores to the first user data output to ensure
latency is deterministic.
Frequency Checker monitors to ensure the I/O PLL core reference clock and
transceiver CDR reference clock from the EVM clock generator and RX recovered clock
frequency generated from CDR are correct.
The main.tcl script (located at the
directory>/system_console directory) generated from the JESD204B Example Design (LMF=888, 6.144 Gbps) (Stratix 10
only) preset is enhanced to support multi-link design. Refer to the Procedures in the main.tcl System Console Script table for details
about the .tcl procedures.
A Signal Tap II file is included in this design for
debug assistance, such as monitoring the short transport pattern at RX transport layers,
checking correct octet ramp pattern at the output of the JESD204B IP cores, and checking the
output counter to ensure design is deterministic from one power cycle to another.
Compile the project to include Signal Tap II file.
Set up the TI ADC12DJxx00 GUI software and board.
Configure the FPGA.
Check the basic operation.
Execute the Tcl Script File (.tcl) code and initialize the JESD204B links.
Check for deterministic latency.
Compiling the Project to Include Signal Tap II File
The reference design provided does not enable Signal Tap II Logic Analyzer in the
To compile the design that include the Signal Tap II file (.stp) into
Quartus® Prime project, follow these steps:
To test the reference design targeted for
Stratix® 10 GX device, download the reference design file to your local project
Quartus® Prime Pro Edition
To prepare the design template in the
Quartus® Prime Pro Edition software GUI, click File > Open and change the file type to the Quartus Prime Design Template
File (*.par). Browse to the <project>.par file and click Ok.
Turn on Assignments > Settings > Category > Enable Signal Tap II Logic Analyzer.
Browse to the stp1.stp
file located at the /stp directory and
To compile the project, select Processing > Start Compilation.
Setting Up the TI ADC12DJxx00 GUI Software and Board
To set up the TI ADC12DJxx00 GUI
software and board, follow these steps:
Install the ADC12DJ3200 GUI Configuration software.
Extract the files from the .zip file.
Run the executable file (setup.exe) and follow the instructions. Use the default
installation location (C:\Program Files (x86)\Texas
Connect the USB cable to PC and turn on the power supply for
the ADC12DJ3200 EVM. Launch the ADC12DJ3200 GUI.exe available from your installation directory.
The USB status becomes green if the ADC12DJ3200 EVM card is
Figure 3. ADC12DJxx00 GUI EVM Tab
Replace the original files with the following modified version
of the .cfg files using the same file
The original files are in this directory: C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\Configuration
File. Extract the ConfigurationFile.zip file
to get the modified version of the .cfg files. You can find
the ConfigurationFile.zip file after installing the
<project>.par file. Back up
the two original files before replacing the two .cfg files provided in the reference design into the same
Select Clock Source > On-board. This is the default setting.
Select On-board Fclk Selection > Fclk = 3200 MHz.
Select Decimation and Serial Data Mode > JMODE1.
Click Program Clocks and ADC.
Clicking the Program Clocks and ADC overwrites any
previous device register settings.
Verify the settings for ADC12DJxx00 LMK04828 > Clock Outputs tab as in the following figure.
Figure 4. ADC12DJxx00 GUI LMK04828 Tab
Configuring the FPGA
To configure the FPGA, follow these
Before configuring the FPGA, ensure the following:
Intel® FPGA Download Cable II driver is installed on the host
Stratix® 10 Transceiver
Signal Integrity Development Kit is powered on.
No other running application is using the JTAG chain.
Quartus® Prime Programmer, select
Hardware Setup > Stratix 10H SI Dev Kit[USB-1].
Click Auto Detect to display the devices in the JTAG
chain. Select device 1SG280HU2S1.
Right click and select Change
File. Choose the appropriate SRAM Object File (.sof) from the <project
directory>/output_files directory. Click Open.
Turn on Program/Configure for the .sof file.
Click Start to program
the image into the FPGA.
Quartus® Prime Programmer
Checking the Basic Operation
To check on the basic operation, follow
Make sure the I/O PLL core reference clock (refclk_core), transceiver clock data recovery (CDR)
reference clock (refclk_xcvr), and receiver
(RX) recovered clock (rxphy_clk) are 160
The LMK04828 clock generator from the ADC12DJ3200 EVM module provides the
reference clock to I/O PLL and transceiver CDR. A frequency checker module is
added to this reference design to verify the I/O PLL core reference clock,
transceiver CDR reference clock, and RX recovered clock frequency are correct.
You can view the measured clock frequency in the Signal Tap II file by clicking at the freq_chk instance as indicated in the following figure. The
frequency values of all measured clocks are displayed in Hz after running
analysis or autorun analysis.
Figure 6. Measured Reference Clock and Recovered Clock
Verify the RX PHY status by monitoring the status of
and rx_cal_busy[7:0] signals for link 0 and link 1.
These signals are available under rx_phy instance in the Signal Tap II file.
Table 1. Bits for Each Lane for Normal Operation of the JESD204B RX
Figure 7. RX PHY Status
Executing the .tcl Code and Initializing the JESD204B Links
To execute the .tcl
code and initialize the JESD204B links, follow these steps:
Launch the System Console in the
Quartus® Prime software, click Tools > System Debugging Tools > System Console.
In the Tcl Console, type the
cd—To change the directory to the working directory
that contains the main.tcl script
(located at <project
execute the main.tcl script.
execute the start_basic_test
To check for deterministic latency,
follow these steps:
Restart the converter and reprogram the clocks and ADC.
Restart and reconfigure the FPGA.
Execute the .tcl code to initialize the JESD204B
Read the RX Buffer Delay (RBD) count by typing the read_rx_status0 procedure in the Tcl
Console and record the value. The RBD count is from the csr_rbd_count field in the rx_status0[10:3] register (at offset 0x80).
Measure and record the number of link counts between the start
of combined SYNC_N deassertion output from the
two JESD204B IP cores to the first user data output, which is the assertion of
the jesd204_rx_link_valid signal. Ensure the
latency is constant for every converter and FPGA power cycle.
Repeat step 1 to step 5 for a few times.
Example of the System Console output after executing the
Figure 8. Successful Link Up Indicated in the System ConsoleThis figure illustrates the expected output from the Tcl
Console of the System Console if the link up is
When the link up is successful, you should observe the following
USER_LED0–USER_LED3 (D12–D15) illuminate
USER_LED4 (D16) turned off
Figure 9. On-board User LEDs
Table 2. On-board User LEDs Indication
On-board User LED
Indication when LED Illuminates
The transport layers and test pattern checkers are out of reset.
The IP cores, transport layers, and deterministic latency module are out of
All lanes are aligned for two JESD204B IP cores receiver.
The receivers at link 0 and link 1 have successful received K28.5
The interrupt is triggered at any of the JESD204B RX IP
Short Transport Layer and Ramp Test Mode Test Results
Verifying Short Transport Test Patterns at Receiver Transport Layer
JESD204B block in the ADC12DJ3200 device defines the short transport test pattern for
N’=12 test mode to verify that the transport layer test patterns in transmitter and
receiver are operating correctly.
To verify the short transport test patterns at the receiver transport layers of
the FPGA, follow these steps:
Quartus® Prime Pro Edition software, click Tools > Signal Tap II Logic Analyzer.
Check the JTAG chain configuration. Select the hardware and
In the Instance Manager, click rx_tprt > run Analysis/Autorun Analysis.
The output of RX transport layers for both links
are grouped in 16 groups in the Signal Tap II
waveform. Each group has 60 bits. You may further split the 60-bit buses into 12-bit
buses as indicated in the following figure to match with the following table.
Figure 10. Short Transport Test Patterns Captured at the Output of RX
Ensure both link 0 and link 1 of receiver output transport
layers are matched with the following table.
Table 3. Short Transport Test Patterns for N’=12 Modes (Length = 1
Frame). This table is taken from the ADC12DJ3200 datasheet.
Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
You can run the ramp test mode after running the short transport pattern test.
In this mode, the JESD04B link layers operate normally, but the transport layers are
disabled. After the initial lane alignment sequence (ILAS), each lane transmits an
identical octet stream that increments from 0x00 to 0xFF and repeats.
To verify the ramp pattern at output data of DLL to the input receiver
transport layer, follow these steps:
Change the command in line 7 of the
ADC12DJxx00_JMODE1.cfg file to: 0x0205 0x04 //
Set JTEST to 4 gives ramp test mode.
Reprogram the clocks and ADC.
Reconfigure the FPGA.
Type the start_basic_test
procedure in the System ConsoleTcl Console to execute the .tcl script to initialize the JESD204B links.
In the Instance Manager, click rx_link > run Analysis.
If you want to check the JESD204B link up process, set a
trigger condition to the dev_sync_n signal. The
signal tap waits for trigger condition to occur. The trigger condition should
occur once you execute the start_basic_test
Figure 11. Octet Ramp Pattern Captured at the Output of DLL
A system is deterministic if latency is repeatable from power-up cycle to
power-up cycle. In this design, the JESD204B IP cores are configured as subclass 1
mode to support deterministic latency. The TI ADC12DJ3200 EVM uses AC coupling for
SYSREF+/-, thus the
periodic SYSREF signal is required to achieve
deterministic latency. The SYSREF period from
LMK04828 is configured to run at a frequency equals to the Local Multi-Frame Clock
(LMFC) frequency before the SYSREF signal is
supplied to the ADC and FPGA. The SYSREF pulse
restarts the LMFC counter on the JESD204B IP cores and converter device, and
realigns the LMFC counter to the LMFC boundary.
To ensure the deterministic latency in the reference design, follow these
Check the FPGA SYSREF single detection.
For detailed description of the registers in the JESD204B RX IP core,
refer to the Addressmap Information for
Passing criteria: The value of csr_sysref_singledet and csr_sysref_lmfc_err should be zero.
Figure 12. csr_sysref_singledet
and csr_sysref_lmfc_err Observed from
the .tcl Console
Check the SYSREF captured.
Passing criteria: If the SYSREF is
sampled correctly, the LMFC counter should be reset. Thus, the RBD_count value should only drift within 1–2 link
clocks from one power cycle to another power cycle. In this test, the RBD_count is consistently 1 across 5 power cycle
tests. It means the /R/ character is
consistently received at 1 LMFC count before the next LMFC boundary for 5 power
Figure 13. Early RBD Release Opportunity for Latest Arrival Lane Within One
Check the latency from the start of combined SYNC_N deassertion output from the two JESD204B IP
cores to the first user data output.
Passing criteria: You should observe consistent latency
from the start of combined SYNC_n deassertion
to the assertion of the jesd204_rx_link_valid
signal. In this design test, you should consistently observe 67 link cycles
clock from one power cycle to another.
Figure 14. Measured Latency from the Start of Combined SYNC_n to
the First User Data Output
Ensure the data latency is fixed during user data phase.
Passing criteria: The ramp pattern should be in perfect shape with
You need to regenerate the platform designer system if you want to modify the
system, such as IP components settings and interfaces.
To regenerate the HDL files for the top level platform designer system, follow
In the platform designer GUI, click Generate > Generate HDL.
Note: If you
want to modify the JESD204B IP cores, Transceiver PHY Reset Controller, and
other component settings, right click on the altera_jesd204_subsystem_RX component and select Drill into Subsystem. After the
modification, save the system. Go back to the top level platform designer
system file and generate the HDL files.
To rerun design in hardware, follow the steps in the Running the
Reference Design section.