The logic array block (LAB) is composed of basic building blocks known as
adaptive logic modules (ALMs). You can configure the LABs to implement logic functions,
arithmetic functions, and register functions.
You can use
half of the available LABs in the
devices as memory LABs (MLABs). Certain devices may have a higher MLAB ratio.
Quartus® Prime software and other
supported third-party synthesis
automatically choose the appropriate mode for common functions such as counters, adders,
subtractors, and arithmetic functions.
is based on the
registers and other features designed to facilitate retiming.
registers are available in ALMs and carry chains. As shown in the
ALM Connection Details figure, the
registers are located on the synchronous clear and clock enable inputs to increase or reduce path delay. All the
registers can be enabled and are controlled by the
Quartus® Prime software during retiming.
Intel Agilex LAB and ALM Architecture and Features
The following sections describe the LAB and ALM for
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains dedicated logic for driving control signals to its ALMs. The MLAB is a superset of the LAB and includes all the LAB features. There are a total of 10 ALMs in each LAB, as shown in the
LAB and MLAB Structure figure.
LAB Structure and Interconnects OverviewThis figure shows an overview of the
LAB and MLAB structure with the LAB interconnects.
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.
LAB and MLAB Structure
Local and Direct Link Interconnects
Each LAB can drive out 60 ALM outputs. A subset of these can directly drive LAB inputs, but any connection to a different row or column must use at least one general-purpose routing wire.
The local interconnect drives the ALM inputs. ALM outputs, as well as column and row interconnects drive the local interconnect.
LAB Local and Direct Link Interconnects
Carry Chain Interconnects
There is a dedicated carry chain path between the ALMs.
devices include an enhanced interconnect structure in
LABs for routing carry chains for efficient arithmetic functions. These ALM-to-ALM connections
bypass the local interconnect.
registers are added to the carry chain to
enable flexible retiming across a chain of LABs and the
Quartus® Prime Compiler
automatically takes advantage of these resources to improve utilization and performance.
Figure 4. Carry Chain Interconnects
LAB Control Signals
There are two clock sources in each LAB control block, which generate two LAB clocks (LABCLK[1:0]) and two delayed LAB clocks (LABCLK_Phi1[1:0])
to drive the ALM registers and Hyper-Registers in the LAB. The delayed clock source is used for time-borrowing feature. The LAB supports two unique clock enable signals, as well as additional clear signals, for the ALM registers.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide
control signals. A low skew clock network distributes global signals to the row clocks [5..0].
The MultiTrack interconnect consists of continuous, performance-optimized routing lines of
different lengths and speeds used for routing
Quartus® Prime Compiler automatically routes critical design paths on faster
interconnects to improve design performance and optimizes the device
Clear Logic Control
LAB-wide signals control the logic for the
register's clear signal. The ALM
both a synchronous and
LAB supports up to two
and two asynchronous clear signals, provided that the total number of clear signals is no
greater than three.
provide a device-wide reset pin (DEV_CLRn) that resets all
the registers in the device. You can enable the DEV_CLRn pin
Quartus® Prime software before compilation. The
device-wide reset signal overrides all other control signals.
LAB-Wide Control Signals
The following sections cover the ALM resources, ALM output, and ALM operating modes.
Each ALM contains a variety of LUT-based resources that can be divided between
two combinational adaptive LUTs (ALUTs),
full adder, and four registers.
With up to eight inputs for the two combinational ALUTs, one ALM can implement
various combinations of two functions. This adaptability allows an ALM to be completely
backward-compatible with four input LUT architectures. One ALM can also implement
a subset of
One ALM contains four programmable registers. Each register has the following ports:
Normal LAB clock
Delayed LAB clock
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can
drive the clock enable signal, clock, and asynchronous or synchronous clear control signals of
an ALM register. The clock
enable signal has priority over synchronous reset signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) and adders drives directly to the outputs of an ALM. Two fast outputs are available for 6 LUT outputs and bottom 5 LUT outputs to bypass the output mux and connect to another LAB for critical path adjustment.
The general routing outputs in each ALM drive the local, row, and column routing resources. Six
ALM outputs, including two fast output paths, can drive column, row, or direct link routing connections.
The LUT, adder, or register output can drive the ALM outputs. Both the LUT or
adder and the ALM register can drive out of the ALM simultaneously.
Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM. The ALM can also drive out registered and unregistered versions of the LUT or adder output.
The following figure shows the
ALM connectivity. In the
Quartus® Prime Resource Property Editor, the entire ALM connection is simplified. Some routings will be routed internally by the
Quartus® Prime software.
ALM Connection Details
ALM Operating Modes
ALM operates in any of the following
Extended LUT mode
Normal mode allows two functions to be implemented in one
ALM, or a single function of up to six inputs.
Up to eight data inputs from the LAB local interconnect are inputs to the
The ALM can support certain combinations of completely independent functions
and various combinations of functions that have common inputs. The
Quartus® Prime Compiler automatically selects the inputs to the LUT. ALMs in
normal mode support register packing.
The following figure shows a combination of different input connections for
the LUT mode. In your design, the
Quartus® Prime software may
assign different input namings during compilation.
Figure 8. ALM in Normal Mode
Combinations of functions with fewer inputs than those shown are also
supported. For example, combinations of functions with the following number of inputs are
4 and 3
3 and 3
3 and 2
5 and 2
For the packing of two 5-input functions into one ALM, the functions must
have at least two common inputs. The common inputs are dataa
and datab. The combination of a 4-input function with a
5-input function requires one common input (either dataa or
In a sparsely used device, functions that could be placed in one ALM may be
implemented in separate ALMs by the
software to achieve the best possible performance. As a device begins to fill up, the
Quartus® Prime software automatically uses the full potential of
Quartus® Prime Compiler automatically searches for functions using common inputs
or completely independent functions to be placed in one ALM to make efficient use of device
resources. In addition, you can manually control resource use by setting location
Figure 9. 6-Input LUT Mode Function in Normal Mode
Figure 10. 3-Input LUT Mode Function in Normal Modedataa and datab are available for register packing.
You can implement any three to six input function using the following
dataa and datab—whereby dataa and datab are shared across both LUTs to provide flexibility to implement a
different function in each LUT.
Both dataa and datab inputs support the register packing feature. If you enable the register
packing feature, both dataa and datab inputs or either one of the inputs bypass the LUT and directly feed into the
register, depending on the packed register mode used. For
devices, the following types of packed register modes are
5-input LUT with 1 packed register path
5-input LUT with 2 packed register paths
Two 3-input LUTs with 2 packed register paths
The 3-input LUT with 2 packed register paths is illustrated in the 3-Input
LUT Mode Function in Normal Mode figure. For
devices, the 6-input LUT mode does not support the register packing feature.
Extended LUT Mode
Figure 11. Supported 8-Input Functions in the Extended LUT Mode
8-input functions can be implemented in a single ALM using all the LUT inputs:
In the 8-input extended LUT mode, the packed register mode is supported,
provided that the packed register shares
with the 8-input LUT.
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to perform pre-adder logic.
Therefore, each adder can add the output of two 4-input functions.
Arithmetic mode also offers clock enable, counter enable, synchronous up and
down control, add and subtract control, and synchronous clear.
The clear and clock enable options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each
pair of registers in an adaptive LUT (ALUT). The
Quartus® Prime software automatically places any registers that are not used by the counter into other LABs.
ALM in Arithmetic Mode
The carry chain provides a fast carry function between the dedicated adders in the arithmetic
The 2-bit carry select feature in
devices splits the propagation delay of carry chains with the ALM.
Carry chains can begin in either the first ALM or the
ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row,
or column interconnects.
Time Borrowing and Latch Modes
devices, you can choose to use the registers in normal mode, time borrowing mode, or latch mode depending on the selection of the LAB clocks (LABCLK). There are a total of four LABCLK generated from two clock sources that can be chosen for each register, provided that the same clock source is used for half of the ALMs, as shown in Figure 7.
Within the four LABCLKs being generated, two out of the four LABCLKs are normal LABCLK, while the remaining two LABCLK are the delayed clocks (LABCLK_Phi1). The delay cell located in the LAB control block is responsible to add an extra delay on the normal LABCLK and generate the delayed LABCLK_Phi1.
The following figures show the master and slave latches that within a register with a timing diagram. The LABCLK_Phi1 is being routed into master latch while the normal LABCLK is being connected into the slave latch. By delaying the clock of master latch, an extra transparent window is added to accommodate long timing path prior to the master latch.
To accommodate and meet the hold timing during time-borrowing in the master latch, an extra slave latch is added to the clock enable (CE) feedback path, to retain the old data during the transparency window.
Besides the time-borrowing mode, the
devices also support latch mode in the ALM register, by controlling the LABCLK in the LAB control block. During the latch mode, only one clock is available for the master and slave latch per LAB, respectively. In the latch mode operation, LABCLK is selected for the slave latch and held at high, while LABCLK_Phi1 is selected for the master latch and the latch opens when LABCLK_Phi1 equals to low.
Document Revision History for the Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide