This design example targets the
FPGA development kit and ED810X+FDMF5820 kit. To enable
the Power Management BUS
MAX® 10 development kit must be
connected to the ED810X+FDMF5820 evaluation kit.
MAX® 10 FPGA Development Board does
not integrate a DC fan or PMBus-based power module. You need to connect these components
through an external hardware. Intel recommends using
Enpirion® Power SoC in this design example.
Enpirion® Power Module Connections
You can control the speed of the DC fan by varying the duty cycle of the pulse width
Figure 3. External DC Fan Connections
Power Module Grouping
This design example uses three power modules. Each power module powers
different power rails for the
Arria® 10 device.
Table 1. Power Module Grouping
Nominal Value (V)
Power Rails on
Arria® 10 Device
VCC, VCCP, VCCR_GXB, VCCERAM
VCCPT, VCCH_GXB, VCCA_PLL
Each power group has different threshold and ramp voltage limits. The preset values are
defined in the program in main.h. You can update the threshold and ramp
voltage via UART using the THRESHOLD or RAMP command.
Pin Assignments and Description
MAX® 10 Pin Assignments
Clock input for the whole system.
Reset the whole design.
Receive UART signal to the PC (host).
Send UART signal from the PC (host).
Alert line for the PMBus.
Alert line for the PMBus.
Alert line for the PMBus.
Clock output to the PMBus devices.
Bidirectional data line for the PMBus.
Control line for the PMBus.
Control line for the PMBus.
Control line for the PMBus.
System indicator for Group 1 power.
System indicator for Group 2 power.
System indicator for Group 3 power.
System indicator for the UFM storage status.
PWM output signal for the DC fan.
User button to perform manual power up.
This design example
requires the following software:
Quartus® Prime version 15.1.2
The communication with the
Nios® II processor is
established through the UART interface. You can use off-the-shelf terminal software such as
Tera Term as a user console.
When you set up the Tera Term software, select CR+LF to enable the New-line Transmit option.
This ensure the command sent through the terminal is recognized by the controller. You also
need to turn on the Local echo option to track the command entered.
Figure 4. Setting Up the Tera Term Software
Alternatively, you can use the example GUI that is provided with this design example for live
data monitoring and display the ADC readout in a graphical format.
Figure 5. Board Control Management GUI
The board management controller GUI is developed using TCL. You need to
install a TCL interpreter to use the GUI. You can download the installer from the ActiveTCL
Downloads. After installing the TCL interpreter, double click the BoardControl.tcl to open the GUI.
Table 3. Functionality of Command Buttons
Command Button/ Entry
Detect COM PORT
Displays which COM PORT is connected to the PC.
Connect COM PORT
Double click the COM PORT to specify which COM PORT to connect.
Click the Connect COM PORT to connect the selected COM PORT.
Select Channel Radio Button
Specifies which ADC channel that you want to stream the data and
displays the data in graphical format.
Upper Threshold or Lower Threshold
Specifies the threshold to be displayed on the graph as red lines. This does not
alter the threshold limit for the controller.
If TSD is selected at the Select Channel Radio Button, the upper threshold cannot
be more than 100°C while the lower threshold cannot be less than –40°C.
For other selection, the upper threshold cannot be more than 2.5V while the lower
threshold cannot be less than 0V.
Starts streaming the data for the channel selected in the Select
Channel Radio Button. The value is displayed and plotted as a graph while the value is
transmitted via the UART interface.
Stops data streaming. You can select other channel in the Select
Channel Radio Button and update the threshold value.
Log File Name
Enter the file name and click Save Datalog if you want to save
the output shown in the Interactive Terminal to a file.
To run the GUI or the Tera Term software, you need to connect the UART
(J11) to PC. You can manually start the power-up or
power-down sequence by using the power-up or power-down button (USER_PB1). In this design
example, only three ADC channels are used. You can customize the design if you require more
ADC channels for your design. For this board, the maximum analog signal input is up to
Custom Fan Board
This is a customized board consisting of other functions. You can design your
own fan board using the design based on the External DC Fan Connections figure.
Figure 14. ED810X+FDMF5820 Kit Connection for VOUT
Table 7. VOUT to J20 Header Connections
MAX® 10 Development
VOUT for the first ED810X+FDMF5820 Kit
VOUT for the second ED810X+FDMF5820 Kit
VOUT for the third ED810X+FDMF5820 Kit
To set up the PMBus connections between the
MAX® 10 Development Kit and the ED810X+FDMF5820 Kit, follow these steps:
Connect the PMBus lines between the
MAX® 10 Development Kit and the ED810X+FDMF5820 Kit.
Connect the PMBus on each of the ED810X+FDMF5820 Kit in a daisy chain.
For more information, refer to the ED810X+FDMF5820 Kit Daisy-Chain Connections table.
Connect SCL and SDA lines from the first ED810X+FDMF5820 Kit to the second
Repeat this step for the second and third ED810X+FDMF5820 Kit in the
Connect the VOUT on the ED810X+FDMF5820 Kit to the
MAX® 10 Development Kit (J20 header) to monitor the voltage
level of the power module using the
MAX® 10 ADC. For
more information, refer to the ED810X+FDMF5820 Kit Connection for VOUT figure and VOUT to
J20 Header Connections table.
The analog channel of the
development kit supports up to 2.5V only. Do not provide voltage higher than 2.5V to the
MAX® 10 Development Kit
Connection for the ADC Input PortYou can modify the design example if you are using more than three
power modules in your design. There are up to 16 ADC channels available.
After you have the complete hardware connection for the design example,
you can program the bmc.pdf to the
MAX® 10 device to test the functionality of the design example.
If you need to customize the design example, follow the steps listed in the
Customizing Design Example section.
Figure 16. Design Example Complete Hardware Connections
Running the Design Example
To run the design example, follow these steps:
Connect all the required hardware. For more information, refer to the Hardware Setup
Download and install the Board Management Controller design example from
the design store. For more information, refer to the Importing Design Template section.
MAX® 10 device on the Development Kit with
bmc.pof located in the project folder.
Open Tera Term or BoardControl.tcl to send
command to the
Nios® II processor. For more information,
refer to the Other Software section.
Table 8. Controller Supported Commands. All commands are case sensitive.
Reads the ADC channel voltage or temperature.
ADC ALL—reads all ADC channels.
ADC 00—reads ADC Channel
ADC 01—reads ADC Channel
ADC TSD—reads temperature.
Turns on the power groups.
POWER 1 ON—turns on the power for Group 1.
POWER 1 OFF—turns off the power for Group 1.
POWER 2 ON—turns on the power for Group 2.
Powers on or off all power groups based on the predefined sequence.
SEQ ON—turns on the power from Group 1 to Group 3 in sequence.
SEQ OFF—turns off the power from Group 3 to Group 1 in sequence.
Reads all the data stored in the UFM.
Erases all the data stored in the UFM.
Checks the available space left in the UFM.
Updates the upper or lower threshold value for each channel. Data is logged into
the UFM when the value detected on each channel is beyond the threshold value.
THRESHOLD 1 H 1.2—sets the
upper threshold for Channel 1 to 1.2V.
THRESHOLD 1 L 0.95—sets the
lower threshold for Channel 1 to 0.95V.
H 1.6—sets the upper threshold for Channel
Updates the threshold value for the ramp-up or ramp-down voltage.
During the power-up operation, the controller checks if the voltages on a power
group have reached the threshold value (High) before turning on the next power
group. During the power-down operation, the controller checks if the voltages on a
power group is below the threshold value (Low) before turning off the power module
RAMP H 1 0.8—sets the high threshold value to 0.8V for Group
RAMP L 1 0.05—sets the low threshold value to 0.05V for Group
Updates the lower or upper threshold value for the TSD. Data is logged into the UFM
when the temperature detected by the TSD is beyond the threshold value.
This does not impact the fan speed.
TEMP H 80—sets the high threshold value to 80°C.
TEMP L 20—sets the low threshold value to 20°C.
Shows all limits set in the board management controller.
Resets all limits to the default values defined in
Changes the DC fan speed by changing the duty cycle of the PWM.
FAN 1—changes the fan speed to 1, where the duty cycle is
FAN 3—changes the fan speed to 3, where the duty cycle is
Enables or disables data log to the UFM.
LOG UFM ON—enables data log to the UFM.
LOG UFM OFF—disables data log to the UFM.
Displays the interval to check the ADC or TSD.
Updates the interval to check the ADC or TSD.
UPDATE TIMER 5—updates the interval to five minutes. The
controller checks the ADC or TSD on the interval of every five minutes.
Displays the summary of all the supported commands on the
Customizing the Design Example
To customize the design example to meet your requirements, follow the
steps listed in the Importing Design Template and Importing Software Code for the
Nios® II Processor sections.
Importing Design Template
To import design template, follow these steps:
Download the design example from Intel Cloud.
Quartus® Prime software. Click the
File menu and select New Project
Specify the working directory for your design. Type BMC as the project name. Click Next.
Select Project template in the Project Type page. Click
On the Design Templates page, click Install the
In the Design Template Installation window, browse to the working directory where
the bmc.par file is located. The default destination
directory is the location you have specified in Step 3. Next, click
OK to install the design template.
After the installation completes, you will receive a message to prompt you that
the design template installation was successful. Click
On the Design Templates page, select Board Management
Controller in the list of available design templates. Click
On the Summary page, click Finish to complete the
Quartus® Prime project creation.
On the Tool menu, select Platform Designer.
In the Open window, select nios.qsys file. Click
If you encounter error messages on the nios.i2c_opencores_0
and nios.pwm_0, you need to include the
<design_folder>/platform/ip folder in the IP search path.
On the Tools menu, select Options to update the IP search
In the Options window, click Add and browse to the
<design_folder>/platform/ip folder. Click Finish.
You can customize the Platform Designer system to meet your
design requirements. Save the changes and generate the HDL.
Importing Software Code for the
To import the software code for the design example, follow these steps:
Unzip the bmc_software.zip in the
Nios® II Software Build Tools for
Specify the workspace for the project.
In the Project Explorer tab, select Import.
On the Import window, select Import
Nios® II Software Build Tools Project. Click
On the Import Software Build Tools Project window, click
Browse to select the <design_folder>/software/bmc
folder in the Project location. Type bmc as the Project
name. Click Finish.
On the Importing a custom Software Build Tools project window, click
Browse to select the
<design_folder>/software/bmc_bsp folder in the Project location. Type
bmc_bsp as the Project name. Click
In the Project Explorer tab, select the bmc_bsp project.
Right-click and select
Nios® II and
You can edit the C codes in the bmc folder to meet your design
requirements. Save the changes.
On the Project menu, select Build All to compile the
changes made on the C codes.
Design in the Intel MAX 10 Device
Figure 17. Platform Designer System Block Diagram
MAX® 10 Design Components
Nios® II Processor
The soft processor manages the operation of the design. The
Nios® II E core is used in this design
Synthesizes the clocks required in this design example.
PLL output counter C0—to synthesize 80-MHz clock for the whole system.
This design example uses a 1-minute timer. By default, the system
checks for voltages and temperature at every 5-minutes interval. If the voltage or
temperature exceeds the preset limits, the
Nios® II processor will data log the value to the UFM.
You can change the timer interval value (TIMER_MINUTE) in
main.h. You can also change the timer minute using the
Storage for the program memory.
The TSD measures the temperature on the
MAX® 10 device. The presets are defined in main.h.
You can also preset on-the-fly using the TEMP
command when connected to a PC through the UART.
The fan speed is based on the threshold temperature in the system.
This is a custom Platform Designer component. The duty
cycle of the PWM is used to control the fan speed.
For more information about this custom component, refer to the PWM
Registers and Setting table.
Temperature < low threshold—the PWM duty cycle is 33%.
Low threshold < temperature < upper threshold—the PWM duty cycle is
Temperature > upper threshold—the PWM duty cycle is 100%.
The default value for the low threshold is 20°C and the high
threshold is 50°C.
You can set the threshold value using the TEMP command.
TEMP L—trigger point for the low threshold.
TEMP H—trigger point for the high threshold.
You can change the duty cycle and the PWM frequency in fan.c.
When the board is powered on, the fan runs at 33.33% duty cycle. After each timer
interrupts, the program reads the TSD temperature and tune the fan to operate at a
different speed. You can change the fan speed to 1, 2, or 3 using the
You can send command to read the voltage and temperature of each
channel. There are up to 16 analog inputs that are muxed to the
MAX® 10 ADC. This enables the
MAX® 10 device to monitor multiple voltage rails in the system.
Storage for data logs—failing channel, failing voltage, or failing temperature.
Data is stored based on their failing condition.
Two types of data are stored in UFM1.
For a failing voltage—0x000AYXXX is logged into the UFM.
For a failing temperature—0x00050XXX is logged into the UFM.
Where Y is the failing channel or group, XXX is the 12-bit output data produced by
the ADC or TSD block.
LED3 is turned on when UFM1 is full. No new data log will be written into UFM1 when
it is full.
When UFM1 is full, you need to read all the UFM1 data to the PC. You can save the
readout to a file on the PC for analysis if required. After that, you need to erase
the UFM before new data can be logged into the UFM again.
You can also perform some basic
by using Erase UFM1, Read
UFM1, and Check UFM1 Space
The PMBus is built using the OpenCores IP and is used to control the external power
The PMBus is a standard protocol used in power management
applications. It is built on top of the I2C with additional ALERT
In this design example, the SCL,
SDA, and ALERT
pins must be pulled to high using a 1-kΩ resistor to run at 400 kHz.
This design example supports the following commands:
on the power module
off the power module
the power module operation by the PMBus only
You can add new commands in power.c and
Interactive terminal. The list of supported commands in this
design example is listed in the Supported Commands table. You can add
your command by modifying main.c.
Table 10. PWM Registers and Settings. The duty cycle of the PWM is pulse
Specify the PWM period, in clock cycles.
Specify the duration of the high pulse of the PWM, in clock