Intel Stratix 10 Power Management User Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 20.3 |
1. Intel Stratix 10 Power Management Overview
The Intel® Stratix® 10 device family offers SmartVID standard power devices in all speed grades. Lower power fixed-voltage devices are also available in all speed grades except for the fastest speed grade.
Intel® Stratix® 10 devices also offer power gating feature to the digital signal processing (DSP) blocks and M20K memory blocks that are not in use for static power savings. You can implement this feature through the Intel® Quartus® Prime software. This user guide describes power saving features of the Intel® Stratix® 10 device family, and also describes the power-up and power-down sequencing requirements for the Intel® Stratix® 10 devices.
2. Intel Stratix 10 Power Management Architecture and Features
The following sections describe the power consumption, power reduction techniques, power sense line feature, power-on reset (POR) requirements, power-up and power-down sequencing requirements.
2.1. Power Consumption
- Static power—the power that the configured device consumes when powered up but no user clocks are operating, excluding DC bias power of analog blocks, such as I/O and transceiver analog circuitry.
- Dynamic power—the additional power consumption of the device due to signal activity or toggling.
- Standby power—the component of active power that is independent of signal activity or toggling. Standby power includes, but is not limited to, I/O and transceiver DC bias power.
2.1.1. Dynamic Power Equation
The following equation shows how to calculate dynamic power where P is power, C is the load capacitance, and V is the supply voltage level. The frequency refers to the clock frequency and data toggles once every clock cycle.
The equation shows that power is design-dependent. Power is dependent on the operating frequency of your design, applied voltage, and load capacitance, which depends on design connectivity. Intel® Stratix® 10 devices minimize static and dynamic power using advanced process optimizations. These optimizations allow Intel® Stratix® 10 designs to meet specific performance requirements with the lowest possible power.
2.2. Power Reduction Techniques and Features
Intel® Stratix® 10 devices leverage on advanced 14-nm process technology, an enhanced core architecture, and various optimizations to reduce total power consumption. The power reduction techniques and features are listed below:
- SmartVID Standard Power Devices
- Power-Screened Devices
- Temperature Compensation
- DSP and M20K Power Gating
- Clock Gating
- Power Sense Line
2.2.1. SmartVID Standard Power Devices
The SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation. This feature is supported in devices with the –V standard power option only. For the –V standard power option devices, you must connect the PWRMGT_SCL and PWRMGT_SDA pins in both the Power Management BUS (PMBus™) master and PMBus slave modes. An additional PWRMGT_ALERT pin is required when you configure the Intel® Stratix® 10 device in the PMBus slave mode. All connections required must be set up on the circuit board and in the Intel® Quartus® Prime software.
For more information about how to connect these pins on the circuit board, refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
For instructions to set up the connection in the Intel® Quartus® Prime software, refer to the Specifying Parameters and Options.
Intel programs the optimum voltage level required by each individual Intel® Stratix® 10 device into a fuse block during device manufacturing. The Secure Device Manager (SDM) Power Manager reads these values and can communicate them to an external power regulator or a system power controller through the PMBus interface.
The SmartVID feature allows a power regulator to provide the Intel® Stratix® 10 device with VCC and VCCP voltage levels that maintain the performance of the specific device speed grade. When the SmartVID feature is used:
- Intel® Stratix® 10 devices are initially powered up to a nominal voltage level of 0.9V for both VCC and VCCP .
- After the VID-fused value in the Intel® Stratix® 10 device is determined and propagated to the external voltage regulator, both the VCC and VCCP voltages are regulated based on the VID-fused value.
2.2.1.1. SmartVID Feature Implementation in Intel Stratix 10 Devices
Devices supporting the SmartVID feature have a VID-fused value programmed into a fuse block during device manufacturing. The VID-fused value represents a voltage level in the range of 0.8V to 0.94V. Each device has its own specific VID-fused value.
The VID-fused value is sent to the external regulator or system power controller through the PMBus interface. Upon receiving the VID-fused value, an adjustable regulator tunes the VCC and VCCP voltage levels to the voltage specified by the VID-fused value.
Intel® Stratix® 10 devices perform the SmartVID setup in the early stage of the configuration process. The SmartVID process will continue to monitor the VCC and VCCP voltage rails in user mode. The Power Manager monitors the temperature and adjusts the voltage when required. For more information, refer to the Temperature Compensation section.
Specification | Value |
---|---|
Voltage range | 0.8 V – 0.94 V |
Voltage step | 10 mV |
Ramp time |
|
Voltage Output Format | Operating Modes | |
---|---|---|
PMBus Master Mode | PMBus Slave Mode | |
Linear mode | Yes | No |
VID mode | No | No |
Direct mode | Yes | Yes, with coefficient m=1, b=0, and R=0 |
2.2.1.2. SDM Power Manager
In Intel® Stratix® 10 devices, the SmartVID feature is managed by the SDM subsystem. The SDM subsystem is powered up after VCC and VCCP voltage levels are powered up to 0.9V. The SDM Power Manager reads the VID-fused value and communicates this value to the external voltage regulator through the PMBus interface.
The SDM Power Manager has the following stages:
- Initial/Shutdown stage
- Sets the external voltage regulator to supply power to VCC and VCCP to the voltage level based on the VID-fused value and the device temperature.
- Configures the FPGA and switches the FPGA to user mode.
- Monitor stage
- Monitors temperature and updates the VCC and VCCP.
The shutdown stage is triggered during device reconfiguration.
2.2.1.2.1. PMBus Master Mode
In the PMBus master mode, during the initial stage, the SDM Power Manager powers up the VCC and VCCP to the voltage level based on the VID-fused value and the device temperature before it starts to configure the FPGA. After entering the user mode (in the monitor stage), the SDM Power Manager monitors temperature changes and decides if the VCC and VCCP output voltage values need to be updated. If voltages require updating, the SDM Power Manager identifies the voltage value based on the fuse values and the current temperature and sends the desired voltage value to the voltage regulators through the PMBus (PWRMGT_SCL and PWRMGT_SDA).
Command Name | Command Code | PMBus Transaction Type | Number of Bytes |
---|---|---|---|
PAGE 2 | 00h | Write byte | 1 |
VOUT_MODE 3 | 20h | Read byte | 1 |
VOUT_COMMAND | 21h | Write word | 2 |
READ_VOUT | 8Bh | Read word | 2 |
MFR_ADC_CONTROL 4 | D8h | Write byte | 1 |
Multi-Master Mode
The PMBus master mode supports the multi-master mode.
When multiple devices start to communicate at the same time, the device writing the most zeros to the bus or the slowest device wins the arbitration. The other devices immediately discontinue any operation on the bus. When there is an on-going bus communication, all devices must detect the communication and not interrupt it. The devices must wait for a stop condition to appear before starting communication to the bus.
In this mode, all master devices must be multi masters in a multi-master system. Single-master systems may not understand the arbitration and the busy detection mechanisms can cause unpredictable results.
2.2.1.2.2. PMBus Slave Mode
Intel® Stratix® 10 devices can also be configured in the PMBus slave mode with an external power management controller acting as the PMBus master. When you configure the Intel® Stratix® 10 device in the PMBus slave mode, you must connect an additional PWRMGT_ALERT pin while connecting the existing PWRMGT_SCL and PWRMGT_SDA pins.
The external PMBus master must poll the state of the PWRMGT_ALERT pin periodically, at an interval not longer than 100ms. When the PWRMGT_ALERT pin is asserted, the external master uses the Alert Response Address (ARA) flow to de-assert the ALERT signal and responds based on the STATUS_BYTE. The external master must also issue the VOUT_COMMAND every 200ms or less to check for a possible change in the target voltage due to temperature compensation.
Command Name | Command Code | Default | PMBus Transaction Type | Number of Bytes |
---|---|---|---|---|
CLEAR_FAULTS | 03h | — | Send byte | 0 |
VOUT_MODE | 20h | 40h | Read byte | 1 |
VOUT_COMMAND | 21h | — | Read word | 2 |
STATUS_BYTE | 78h | 00h | Read byte | 1 |
Sequence | SDM | PMBus Master | Notes |
---|---|---|---|
1 | Asserts the ALERT signal | — | — |
2 | — | Detects the ALERT signal | — |
3 | — | Initiates the ARA flow | — |
4 | Responds to the ARA flow and provides its address | — | Only the device which has asserted the ALERT signal in step 1 responds to the ARA flow by providing its address. |
5 | De-asserts the ALERT signal | — | The ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow. |
6 | — | Reads the STATUS_BYTE | — |
7 | Returns STATUS_BYTE=0 | — | Indicates the FPGA voltage requires an update. |
8 | — | Sends CLEAR_FAULTS | — |
9 | — | Sends VOUT_COMMAND | The VOUT_COMMAND must be received by the SDM within 200ms after the ALERT signal is asserted. Failure to meet this requirement will cause configuration error. 5 |
10 | Receives the VOUT_COMMAND, responds with the target voltage | — | Calculated based on the temperature, the VID fuse and the coefficient for the direct format (you need to specify this input). |
11 | — | Sets the voltage regulator to the target voltage in step size not greater than 10mV/10ms step | — |
Sequence | SDM | PMBus Master | Notes |
---|---|---|---|
1 | Asserts the ALERT signal | — | The SDM detects fault and asserts the ALERT signal. 6 |
2 | — | Detects the ALERT signal | — |
3 | — | Initiates the ARA flow | — |
4 | Responds to the ARA flow and provides its address | — | Only the device which has asserted the ALERT signal in step 1 responds to the ARA flow by providing its address. |
5 | De-asserts the ALERT signal | — | The ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow. |
6 | — | Reads the STATUS_BYTE | — |
7 | Returns the STATUS_BYTE when not equal to 0 | — | Indicates that other fault has occurred |
8 | — | Sends CLEAR_FAULTS | To reset the STATUS_BYTE. |
9 | — | Reads the STATUS_BYTE | To confirm that STATUS_BYTE=0 |
10 | — | External master to handle the faults | — |
The Intel® Stratix® 10 device in the PMBus slave mode will be sending the VOUT_COMMAND value in the direct format only. To read the actual voltage value, use the following equation to convert the VOUT_COMMAND value from the Intel® Stratix® 10 device.
The equation shows how to convert the direct format value where:
- X, is the calculated, real value units in mV;
- m, is the slope coefficient, a 2-byte two's complement integer;
- Y, is the 2-byte two's complement integer received from the Intel® Stratix® 10 device;
- b, is the offset, a 2-byte two's complement integer;
- R, is the exponent, a 1-byte two's complement integer
The following example shows how an external power management controller retrieves values from the Intel® Stratix® 10 device. Coefficients used in the VOUT_COMMAND are as follows:
- m = 1
- b = 0
- R = 0
If the external power management controller retrieved a value of 0384h, it is equivalent to the following:
X = (1/1) x (0384h x 10-0 - 0) = 900 mV = 0.90 V
The following faults can raise the ALERT signal:
- PMBUS_ERR_RD_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
- PMBUS_ERR_WR_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
- PMBUS_ERR_UNSUPPORTED_CMD (VOUT_COMMAND, VOUT_MODE, READ_STATUS, and CLEAR_FAULTS are the only supported commands in the PMBUS Slave Mode)
- PMBUS_ERR_READ_FLAG (Received duplicate command before being able to respond to the first command)
- PMBUS_ERR_INVALID_DATA (Invalid or malformed PMBus/I2C message)
If any of the above errors are detected, the ALERT signal is raised and bit 1 of the status register is set.
2.2.2. Power-Screened Devices
Intel® Stratix® 10 power-screened devices are available in –2L and –3X options. Power-screened devices offer lower static power than the SmartVID –V power option devices. The –2L and –3X power-screened devices run at a fixed-voltage supply and do not require using the PMBus regulator.
2.2.3. Temperature Compensation
Intel® Stratix® 10 devices are able to compensate for performance degradation at colder temperatures by raising the voltage. While raising the voltage does increase the dynamic power consumption, this is countered by lower leakage at cold temperatures, thus enabling total power consumption at cold temperatures to still be lower than at hot temperatures.
The SmartVID feature supports this dynamic voltage adjustment. The SDM Power Manager checks for temperature changes and updates the new VID value if the temperature crosses the threshold point.
The following shows the process when there is a change in the VID value:
- If the Intel® Stratix® 10 device operates as the PMBus master, the SDM sends the relevant commands to adjust the voltage of the external voltage regulator using the new VID value.
- If the Intel® Stratix® 10 device operates as the PMBus slave, the external power management controller gets the new VID value with the VOUT_COMMAND which is issued every 200 ms or less, and set the voltage regulator with the new VID value.
2.2.4. DSP and M20K Power Gating
Power gating of the DSP blocks and M20K memory blocks is enabled via the configuration RAM (CRAM) bits. Intel® Stratix® 10 devices support power gating for both DSP blocks and M20K memory blocks. By default, the Intel® Quartus® Prime software automatically configures unused DSP blocks and M20K memory blocks to be power gated.
2.2.5. Clock Gating
Clock gating can be used to reduce dynamic power consumption. When an application is idle, its clock can be gated temporarily and ungated based on wake-up events. This is done using user logic to enable or disable the global clock (GCLK) and sector clock (SCLK).
You can perform dynamic power reduction by gating the clock signals of any circuitry not used by the design in the Intel® Stratix® 10 devices. The sector clock gating is done at the multiplexer level.
Clock gating a large portion of your FPGA design could cause significant current change over a short time period when the gated circuitry is enabled or disabled. The maximum current step resulting from this clock gating should be sized such that it does not create noise exceeding the maximum allowed AC noise specification, as determined by the PDN decoupling design on your PCB. You can control the current step size by dividing a large gated area into smaller sub-regions and staging those regions to enter or exit power gating sequentially.
2.2.6. Power Sense Line
Intel® Stratix® 10 devices support the power sense line feature. VCCLSENSE and GNDSENSE pins are differential remote sense pins used to monitor the VCC power supply.
You must connect the VCCLSENSE and GNDSENSE pins to the remote sense inputs for all regulators that support the remote voltage sensing feature.
2.3. Power-On Reset Circuitry
The POR circuitry keeps the Intel® Stratix® 10 device in the reset state until the power supply outputs are within the recommended operating range.
A POR event occurs when you power up the Intel® Stratix® 10 device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Intel® Stratix® 10 device I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.
The Intel® Stratix® 10 POR circuitry uses individual detection circuitry to monitor each of the configuration-related power supplies independently. The POR circuitry is gated by the outputs of all the individual detectors.
POR delay is the time from when the POR trips out to the final reset signal.
The Intel® Stratix® 10 device is held in the POR state until all power supplies have passed their trigger point. After power supplies have passed the trigger point, the SDM will wait for a configurable delay time and then start device configuration.
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
Power Supplies Monitored | Power Supplies Not Monitored |
---|---|
2.4. Power Sequencing Considerations for Intel Stratix 10 Devices
The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality. Intel® Stratix® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The table below also shows what the unpowered pins can tolerate during power-up and power-down sequences.
The I/O pins are tri-stated with a weak pull-up during power up.
Pin Type | Power-Up | Power-Down | ||||||
---|---|---|---|---|---|---|---|---|
Tristate | Drive to GND | Drive to VCCIO | Driven with < 1.0 Vp-p | Tristate | Drive to GND | Drive to VCCIO | Driven with < 1.0 Vp-p | |
3VIO banks | √ | — | — | — | √ | √ | — | — |
LVDS I/O banks | √ | √ | √10 | — | √ | √ | √10 | — |
Differential Transceiver pins | √ | √ | — | √11 | √ | √ | — | √11 |
2.4.1. Power-Up Sequence Requirements for Intel Stratix 10 Devices
The power rails in Intel® Stratix® 10 devices are each divided into three groups. Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines and AN692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices for additional details.
The diagram below illustrates the voltage groups of the Intel® Stratix® 10 devices and their required power-up sequence.
Power Group | Intel® Stratix® 10 GX and SX (L-Tile and H-Tile) | Intel® Stratix® 10 MX (HBM, H-Tile, and E-Tile) | Intel® Stratix® 10 TX (H-Tile and E-Tile) | Intel® Stratix® 10 DX (E-Tile and P-Tile) |
---|---|---|---|---|
Group 1 |
VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS |
VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCPLLDIG_SDM VCCRT_GXE VCCRTPLL_GXE |
VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS VCCRT_GXE VCCRTPLL_GXE |
VCC VCCP VCCERAM VCCFUSE_GXP 12 VCCRT_GXP VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS VCCRT_GXE VCCRTPLL_GXE |
Group 2 |
VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC |
VCCPT VCCH_GXB VCCA_PLL VCCPLL_SDM VCCADC VCCM_WORD 13 VCCH_GXE VCCCLK_GXE |
VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC VCCH_GXE VCCCLK_GXE |
VCCPT VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC VCCM_WORD 13 VCCH_GXP VCCCLK_GXP VCCH_GXE VCCCLK_GXE |
Group 3 |
VCCIO 14 VCCIO3V 14 VCCIO_SDM 14 VCCIO_HPS 14 VCCFUSEWR_SDM VCCIO3D 15 |
VCCIO VCCIO3V VCCIO_SDM VCCIO_UIB 13 VCCFUSEWR_SDM |
VCCIO VCCIO3V VCCIO_SDM VCCIO_HPS VCCFUSEWR_SDM |
VCCIO VCCIO_SDM VCCIO_HPS VCCIO_UIB 13 VCCFUSEWR_SDM |
Group 4 |
VCCIO3C 15 |
— | — | — |
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up.
The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up.
The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value.
Group 4 power rails can ramp up after the last power rail in Group 3 ramps up to a minimum threshold of 90% of their full value.
All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast POR delay time. The POR delay time depends on the POR delay setting you use. For the POR specifications of the Intel® Stratix® 10 devices, refer to the POR Specifications section in the Intel® Stratix® 10 Device Datasheet .
For configuration via protocol (CvP), the total tRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. Select a fast POR delay setting to allow sufficient time for the PCI Express* ( PCIe* ) link initialization and configuration. For more details about power supply ramp up for the CvP mode, refer to the Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide.
2.4.2. Power-Down Sequence Recommendations and Requirements for Intel Stratix 10 Devices
Intel's FPGAs need to follow certain requirements during a power-down sequence. The power-down sequence can be a controlled power-down event via an on/off switch or an uncontrolled event as with a power supply collapse. In either case, you must follow a specific power-down sequence. Below are four power-down sequence specifications. They are either Recommended (one), Required (two), or Relaxed (one). To comply with Intel® ’s FPGA Power-Down requirements, the Recommended option is best.
Recommended Power-Down Ramp Specification
This is the best option to minimize power supply currents.
- Power down all power rails fully within 100 ms.
- Power down power supplies within the same Group in any order.
- Before Group 3 supplies power down, power down all Group 4 supplies within 10% of GND.
- Before Group 2 supplies power down, power down all Group 3 supplies within 10% of GND.
- Before Group 1 supplies power down, power down all Group 2 supplies within 10% of GND.
- The maximum voltage differential between any Group 3 supply and any Group 2 supply is 1.92 V, and only applicable for the 1.8V voltage rails in Group 2.
- Ensure that the newly combined power rails do not cause any driving of unpowered GPIO or transceiver pins.
- Ensure that the newly combined power rails do not violate any power-down sequencing specification due to device (third party) leakage; maintain the Required Voltage Differential Specification.
During the power-up/down sequence, the device output pins are tri-stated. To ensure long term reliability of the device, Intel recommends that you do not drive the input pins during this time.
Required Power-Down Ramp Specification
In cases where power supply is collapsing or if the recommended specification cannot be met, the following PDS sequence is required.
- Power down all power rails fully within 100 ms.
- As soon as possible, disable all power supplies.
- Tri-state Group 1 supplies, and do not drive them actively to GND.
- If possible, drive or terminate Group 2, Group 3, and Group 4 supplies to GND.
- Ensure no alternative sourcing of any power supply exists during the power-down sequence; reduce all supplies monotonically and with a consistent RC typical decay.
- By the time any Group 1 supply goes under 0.35 V, all Group 2, Group 3, and Group 4 supplies must be under 1.0 V.
Required Voltage Differential Specification
To not excessively overstress device transistors during power-down, there is an additional voltage requirement between any two power supplies between different power groups during power-down:
ΔV < ΔVnom + 500 mV
- Power down all power rails fully within 100 ms.
- For example, if Group 1 Voltage = 0.9 V, Group 2 Voltage = 1.8 V, and Group
3 Voltage = 3.0 V, then:
G3Vnom = 3.0 V
G2Vnom = 1.8 V
G2Vnom = 1.8 V
G1Vnom = 0.9 V
G3Vnom = 3.0 V
G1Vnom = 0.9 V
(G3V – G2V)nom = 1.2 V (G2V – G1V)nom = 0.9 V (G3V – G1V)nom = 2.1 V (G3V – G2V) <= 1.2 V + .5 V (G2V – G1V) <= 0.9 V + .5 V (G3V – G1V) <= 2.1 V + .5 V (G3V – G2V) <= 1.7 V (G2V – G1V) <= 1.4 V (G3V – G1V) <= 2.6 V - To meet this voltage differential requirement, ramp down all power supplies as soon as possible according to the Required Power-Down Ramp Specification.
Relaxed Power-Down Duration Specification
For supplies being powered down with no active termination, voltage reduction to GND slows down as supply approaches 0 V. In this case, the 100 ms power requirement is relaxed - measure it when supply reaches near GND.
- Ensure all Group 1 supplies reach < 100 mV within 100 ms.
- Ensure all Group 2, Group 3, and Group 4 supplies reach < 200 mV within 100 ms.
2.5. Power Supply Design
The power supply requirements for Intel® Stratix® 10 devices will vary depending on the static and dynamic power for each specific use case. The Enpirion portfolio of power management solutions, combined with comprehensive design tools, enable optimized Intel® Stratix® 10 device power supply design. The Enpirion portfolio includes power management solutions that are compatible with the multiple interface methods utilized by Intel® Stratix® 10 devices and designed to support Intel® Stratix® 10 power reduction features such as the SmartVID feature.
Intel® Stratix® 10 devices have multiple input voltage rails that require regulated power supplies for their operation. Multiple input rail requirements may be grouped according to system considerations such as voltage requirements, noise sensitivity, and sequencing. The Intel® Stratix® 10 Device Family Pin Connection Guidelines provides more detailed recommendations about which input rails may be grouped. The Early Power Estimator (EPE) tool for Intel® Stratix® 10 devices also provides input rail power requirements and specific device recommendations based on each specific Intel® Stratix® 10 use case. Individual input rail voltage and current requirements are summarized on the “Report” tab. Input rail groupings and specific power supply recommendations can be found on the “Report” and “Enpirion” tabs, respectively.
3. Intel Stratix 10 Power Management and VID Interface Implementation Guide
The Intel® Stratix® 10 SDM Power Management Firmware manages the SmartVID configuration and enables the FPGA to power up before you can access the FPGA core.
3.1. Intel Stratix 10 Power Management and VID Interface Getting Started
The Intel® Stratix® 10 Power Management and VID interface is installed as part of the Intel® Quartus® Prime software.
3.1.1. Specifying Parameters and Options
Follow these steps to specify the Power Management and VID parameters and options.
- Create an Intel® Quartus® Prime project using the New Project Wizard available from the File menu.
- On the Assignments menu, click Device.
- On the Device dialog box, click Device and Pin Options.
- On the Device and Pin Options dialog box, click Configuration.
- On the Configuration page, specify the VID Operation mode. There are two modes available—PMBus Master and PMBus Slave.
- Both the PMBus Master and PMBus Slave modes require the PWMGT_SDA and PWMGT_SCL pins. For the PMBus Slave mode, additional PWRMGT_ALERT pin is required. To configure these pins, on the Configuration page, click Configuration Pin Options. For the configuration pin parameters, refer to Table 10.
- On the Configuration Pin dialog box, assign the appropriate SDM_IO pin to the power management pins. Click OK.
- On the Device and Pin Options dialog box, click Power Management and VID to specify the device settings if your device is in the PMBus Master mode. Click OK. For the power management and VID parameters, refer to Table 11.
This completes the SmartVID setup for the Intel® Stratix® 10 device.
3.1.1.1. Configuration Pin Parameters
You can configure the following power management pins using the GUI parameters.
Parameters | Value | Description |
---|---|---|
Use PWRMGT_SCL output | SDM_IO0 |
This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode. Disable this parameter for the non-SmartVID device. Intel® recommends using the SDM_IO14 pin for this parameter. |
SDM_IO14 | ||
Use PWRMGT_SDA output | SDM_IO11 |
This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode. Disable this parameter for the non-SmartVID device. Intel® recommends using the SDM_IO11 pin for this parameter. |
SDM_IO12 | ||
SDM_IO16 | ||
Use PWRMGT_ALERT output | SDM_IO0 |
This is a required PMBus interface for the power management that is used only in the PMBus Slave mode. Disable this parameter for the non-SmartVID device. Intel® recommends using the SDM_IO12 pin for this parameter. This parameter is an active-low signal. |
SDM_IO9 | ||
SDM_IO12 |
3.1.1.2. Power Management and VID Parameters
You can use the GUI parameters to configure the Power Management and VID interface if the VID operation is in the PMBus Master mode.
Parameters | Value | Description |
---|---|---|
Bus speed mode 16 | 100 KHz | Bus speed mode of PMBus interface when operating in the PMBus Master mode. |
400 KHz | ||
Slave device type16 | ED8401 |
Supported device types. Intel® recommends you to use one of the slave device type listed in the drop-down menu. If you are not using one of the slave device type listed in the drop-down menu, select Other option. |
EM21XX | ||
EM22XX | ||
LTM4677 | ||
ISL82XX | ||
Other | ||
Device address in PMBus Slave mode17 | 7-bit hexadecimal value | Device address in the PMBus Slave mode. |
Slave device_0 address16 | 7-bit hexadecimal value |
External power regulator address. This parameter must be non-zero when you are using the PMBus Master mode. |
Slave device_1 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_2 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_3 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_4 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_5 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_6 address16 | 7-bit hexadecimal value | External power regulator address. |
Slave device_7 address16 | 7-bit hexadecimal value | External power regulator address. |
Voltage output format16 | Auto discovery |
The voltage output format when the operation mode is PMBus Master. If the voltage output format is the Auto discovery or Direct format, you must set the following parameters:
If the voltage regulator is the Linear format, you must set the Linear format N parameter. 18 |
Direct format | ||
Linear format | ||
Direct format coefficient m16 | Signed integer: -32768 to 32767 | Direct format coefficient m of the slave device type when the operation mode is PMBus Master. |
Direct format coefficient b16 | Signed integer: -32768 to 32767 | Direct format coefficient b of the slave device type when the operation mode is PMBus Master. |
Direct format coefficient R16 | Signed integer: -128 to 127 | Direct format coefficient R of the slave device type when the operation mode is PMBus Master. |
Linear format N16 | –16 to 15 | Output voltage command when the voltage output format is set to the Linear format. |
Translated voltage value unit16 | millivolts | Indicates the translated output voltage is in millivolts (mV) or volts (V). |
volts | ||
Enable PAGE command16 | Enable | By enabling the PAGE command, the FPGA PMBus Master will use the PAGE command to set all the output channels (0xFF) on registered regulator modules to respond to VOUT_COMMAND. If only specified output channels on registered regulator modules must respond to VOUT_COMMAND, enter the corresponding page value (0x00 – 0xFF). |
Disable |
3.1.1.3. Intel Stratix 10 Power Management and VID Interface QSF Constraint Guide
For the configuration pin parameters, refer to Table 10. For the power management and VID parameters, refer to Table 11.
Specifying the Power Management and VID Parameters through QSF Constraints
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS41
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS42
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS43
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS44
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS45
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS46
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS47
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS48
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD xx
4. Intel Stratix 10 Power Management User Guide Archives
Intel® Quartus® Prime Version | User Guide |
---|---|
20.1 | Intel Stratix 10 Power Management User Guide |
19.4 | Intel Stratix 10 Power Management User Guide |
19.3 | Intel Stratix 10 Power Management User Guide |
19.2 | Intel Stratix 10 Power Management User Guide |
18.1 | Intel Stratix 10 Power Management User Guide |
18.0 | Intel Stratix 10 Power Management User Guide |
17.1 | Intel Stratix 10 Power Management User Guide |
5. Document Revision History for the Intel Stratix 10 Power Management User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.10.16 | 20.3 |
|
2020.04.30 | 20.1 | Added the Supported Voltage Output Format for Intel® Stratix® 10 Devices with the –V Power Option table. |
2020.01.23 | 19.4 |
|
2019.11.05 | 19.3 | Updated the power rails in Table: Voltage Rails:
|
2019.09.19 | 19.3 |
|
2019.08.23 | 19.2 | Updated the note for VCCBAT in the Power Supplies Monitored and Not Monitored by the POR Circuitry section. |
2019.07.01 | 19.2 |
|
2018.09.26 | 18.1 |
|
2018.05.07 | 18.0 |
|
2018.02.28 | 17.1 |
|
Date | Version | Changes |
---|---|---|
May 2017 | 2017.05.08 |
|
October 2016 | 2016.10.31 |
Initial release. |