AN 745: Design Guidelines for DisplayPort Intel FPGA IP Interface
1. Design Guidelines for DisplayPort Intel FPGA IP Interface
These guidelines facilitate board designs for the DisplayPort Intel® FPGA IP video interfaces.
1.1. DisplayPort Intel FPGA IP Design Guidelines
- Main Link—Main Link is a unidirectional, high-bandwidth channel that transports video and audio over 1, 2, or 4 lanes at 8.1, 5.4, 2,7, and 1.62 Gigabits per second (Gbps) per lane. All lanes carry data. The clock is embedded in 8b/10b encoded serial data.
- AUX CH—The AUX CH is 1 Megabits per second (Mbps) half-duplex bidirectional channel used for link management and device control.
- HPD—The DisplayPort Intel® FPGA IP sink device uses HPD to detect its presence, The HPD signal serves as an interrupt request by the DisplayPort sink device.
1.1.1. Main Link
1.1.1.1. Main Link TX
The FPGA Transceiver PHY TX includes on-chip 100 ohm differential termination and bias voltage generation. You may add a repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to compensate for loss.
FPGA Transceiver PHY Operations | Description |
---|---|
Transceiver PHY TX Reference Clock Connection |
A free-running 135 MHz differential clock (e.g. LVDS) is AC-coupled to a dedicated reference clock input of the transceiver bank. The reference clock input supports on-chip termination (OCT). Enable OCT using a QSF assignment:
Note: Your design does not require external termination if OCT is
enabled.
|
Transceiver TX On-Chip Termination |
By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_TX). |
Transceiver TX Channel Bonding |
Bonding TX channels reduces on-chip channel-to-channel skew, which allows more skew margin at the board or system level to meet the DisplayPort Intel® FPGA IP Source inter-lane skew requirement. Refer to Table 2 for more information. |
Transceiver TX Voltage Swing and Pre-emphasis |
DisplayPort TX specification for the Main Link allows four differential peak-to-peak voltage swing levels, and four pre-emphasis (Post Cursor1) levels. Certain combinations of voltage swing levels and pre-emphasis levels that result in differential peak-to-peak swing outside the allowable range (1.38 V) are not allowed. The reconfiguration management module available in the Intel® Quartus® Prime design example includes a sub-module that translates the DisplayPort voltage swing and pre-emphasis levels to the FPGA transceiver setting. Refer to Table 3 for more information. Use the reconfiguration management file and a sub-module of the Intel® Quartus® Prime design examples that maps the DisplayPort levels to the transceiver analog parameter setting.
|
TX Repeater (Redriver or Retimer) |
To mitigate system signal losses, you may place a redriver or retimer between the FPGA and the external DisplayPort connector for a box-to-box connection. In such designs, place the repeater close to the external DisplayPort connector and generate the DisplayPort signals at the voltage and pre-emphasis levels determined during link training, instead of the FPGA. In this case, you can turn off the Support analog reconfiguration option in the DisplayPort Intel® FPGA IP parameter editor and set the FPGA voltage swing in the QSF assignments. The selection of the appropriate signaling level between the FPGA and the repeater depend on the PCB loss and the equalization of the redriver/retimer input. The typical setting for the transmitter is 400 mV voltage swing without pre-emphasis. Refer to Table 4 for more information. |
Bonded TX channels placed in a single transceiver bank results in lower channel-to-channel skew, allowing more skew budget at the board level. For information about the maximum channel-to-channel skew, refer to the Device Datasheet.
You have the option to select bonding mode through the Transceiver PHY parameter editor.
Device Family | Transceiver PHY Bonding Mode | Notes |
---|---|---|
Intel® Stratix® 10 L-tile and H-tile/ Intel® Arria® 10/ Intel® Cyclone® 10 GX | PMA and PCS bonding |
Note: The digital reset signal (tx_digitalreset) to all TX channels within a bonded group must meet a
maximum skew tolerance of one-half the TX parallel clock cycle (tx_clkout). Refer to the Timing
Constraints for Bonded PCS and PMA Channels section of the respective Transceiver PHY User Guides for more information.
|
Arria V | xN | – |
Stratix V | x6/xN | – |
Voltage Swing Level | Pre-Emphasis Level | |||
---|---|---|---|---|
0 | 1 | 2 | 3 | |
0 | Supported | Supported | Supported | Supported |
1 | Supported | Supported | Supported | Not allowed |
2 | Supported | Supported | Not allowed | Not allowed |
3 | Supported | Not allowed | Not allowed | Not allowed |
Device Family | DisplayPort version 1.2 Rates (RBR, HBR, HBR2) | DisplayPort version 1.4 Rate (HBR3) | Example Repeater |
---|---|---|---|
Intel® Stratix® 10 L-tile and H-tile | Not Required | Not Required | – |
Intel® Arria® 10 | Not Required | Not Required | – |
Intel® Cyclone® 10 GX | Not Required | Not Required | – |
Arria V | Required 1 | Not Applicable 2 | TI SN75DP130 (Redriver) |
Cyclone V | Required 1 | Not Applicable 2 | TI SN75DP130 (Redriver) |
Stratix V | Not Required | Not Applicable 2 | – |
1.1.1.2. Main Link TX Electrical Specifications
Parameter | Minimum | Typical | Maximum | Notes |
---|---|---|---|---|
Maximum Output Voltage Level | – | – | 1.38 V |
Maximum differential peak-to-peak swing for all output level and pre-emphasis combinations |
Lane-to-Lane Output Skew | – | – | 1250 ps |
VESA DisplayPort Standard version 1.4 for all data rates |
Lane-to-Lane Output Skew (HBR, RBR) | – | – | 2 UI |
VESA DisplayPort Standard version 1.2a for HBR and RBR |
Lane-to-Lane Output Skew (HBR2) | – | – | 4 UI + 500 ps |
VESA DisplayPort Standard version 1.2a for HBR2 |
Parameter | Minimum | Typical | Maximum | Notes |
---|---|---|---|---|
Maximum TX Total Jitter | – | – | 0.65 UI |
For HBR3, TPS4 pattern, at 1E-9 |
– | – | 0.62 UI |
For HBR2, CP2520 pattern, at 1E-9 |
|
– | – | 0.40 UI |
For HBR2, D10.2 pattern, at 1E-9 |
|
TX Differential Peak-to-Peak EYE Voltage at HBR3 | 75 mV | – | – |
For HBR3, TPS4 pattern, at 1E-9 |
TX Differential Peak-to-Peak EYE Voltage at HBR2 | 90 mV | – | – |
For HBR2, CP2520 pattern, at 1E-9 |
1.1.1.3. Main Link RX
You may add an RX repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to clean up jitter and compensate for losses. AC-coupling is optional for Main Link RX.
FPGA Transceiver PHY Operations | Description |
---|---|
Transceiver RX On-Chip Termination |
By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_RX). |
RX Repeater (Redriver or Retimer) |
To clean up jitter and compensate for signal losses, a sink device uses a redriver or retimer between the external DisplayPort connector and the FPGA RX. In such systems, the device places the repeater close to the external DisplayPort connector and regenerates the received DisplayPort signals.
Refer to Table 8 for more information. |
Device Family | VESA DisplayPort Standard version 1.2a Rates (RBR, HBR, HBR2) | VESA DisplayPort Standard version 1.4 Rate (HBR3) | Example Repeater |
---|---|---|---|
Intel® Stratix® 10 L-tile and H-tile | Not Required 3 | Not Required 3 | – |
Intel® Arria® 10 and Intel® Cyclone® 10 GX | Not Required 3 | Required 4 |
|
Arria V | Required 4 | Not Applicable 5 | TI SN75DP130 (Redriver) |
Cyclone V | Required 4 | Not Applicable 5 | TI SN75DP130 (Redriver) |
Stratix V | Not Required | Not Applicable 5 | – |
1.1.1.4. Main Link RX Electrical Specifications
Parameter | Minimum | Typical | Maximum | Notes |
---|---|---|---|---|
Minimum Receiver EYE Width at HBR3 | 0.35 UI | – | – |
For HBR3, TPS4 pattern |
RX Differential Peak-to-Peak EYE Voltage at HBR3 | 75 mV | – | – | |
Minimum Receiver EYE Width at HBR2 | 0.38 UI | – | – |
For HBR2, CP2520 pattern |
RX Differential Peak-to-Peak EYE Voltage at HBR2 | 70 mV | – | – |
1.1.2. AUX Channel
The 100-KΩ and 1-MΩ pull-up and pull-down resistors are placed between the connectors and AC-coupling capacitors. These resistors help detect any DisplayPort upstream devices, including a powered DisplayPort upstream device by a sink device.
Parameter | Minimum | Maximum | Notes |
---|---|---|---|
AUX Direct Current (DC) Common Mode Voltage | 0.0 V | 2.0 V | Common mode voltage is equal to Vbias_TX (or Vbias_RX) |
AUX Peak-to-Peak Voltage | 0.29 V | 1.38 V | Differential peak-to-peak voltage swing |
AUX AC-Coupling Capacitor | 75 nF | 200 nF | The AUX channel AC-coupling capacitors are placed on both the DisplayPort upstream and downstream devices. |
1.1.2.1. Implementing Bus LVDS I/O Interface
The BLVDS I/O is a bidirectional differential I/O interface and requires special pin assignment consideration. Depending on the FPGA bank VCCIO voltage and I/O standard used, the BLVDS I/O may require a series resistor, Rs. The series resistor ensures the AUX channel differential voltage swing is below the maximum peak-to-peak voltage swing specification.
FPGA Device | Pin | I/O Standard | VCCIO | Series Resistor (Rs) Value |
---|---|---|---|---|
Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 | LVDS | Differential SSTL-18 Class I | 1.8 V | 22 Ω |
Differential SSTL-18 Class II | ||||
Arria V, Cyclone V, and Stratix V | DIFFIO_RX 6 | Differential SSTL-2 Class II | 2.5 V | 100 Ω |
1.1.2.2. Implementing Bidirectional LVDS
The interface to the device is straightforward. For example, TI SN65MLVD200A requires three LVTTL general purpose I/O pins (aux_oe, aux_out, aux_in). If the FPGA bank I/Os are not tolerant with LVTTL, a level shifter is required, as shown in the figure above.
There may be crosstalk from the single-ended LVTTL signals to the Main-Link high speed signals if the traces are routed close to each other. During board signal integrity (SI) design, pay special attention to routing.
For more information about the BLVDS driver, TI SN65MLVD200A, refer to the SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet.
1.1.2.3. Detection of DisplayPort Upstream Source Device
The weak pull-up and pull-down resistors form a voltage divider that allows the sink device to detect the presence of the upstream source device.
Between the AC-coupling capacitor and the DisplayPort connector:
- The source device weakly pulls down the AUX+ line to GND and weakly pulls up the AUX- line to DP_PWR (typically 3.3 V) with nominal 100K ohm resistors.
- The sink device weakly pulls up the AUX+ line to 3.3 V and weakly pulls down the AUX- line to GND with nominal 1M ohm resistors.
The AUX+ and AUX- lines connect to the FPGA through 10K ohm resistors (e.g. RX_SENSE_P and RX_SENSE_N signals in the Bitec DisplayPort daughter card). The DisplayPort Intel® FPGA IP sink senses the logic level of the AUX+ and AUX- lines using the rx_cable_detect and rx_pwr_detect inputs and triggers the HPD signal when the powered upstream source device is detected.
The sense signals require level translation if they are connected to an FPGA I/O that is not 3.3V tolerant, for example, Intel® Arria® 10 device bank with VCCIO = 1.8 V.
1.1.3. DisplayPort Hot Plug Detect (HPD)
To prevent the HPD signal from floating when not connected, tie to GND with a >100K ohm resistor in both the DisplayPort Intel® FPGA IP source and sink devices.
1.1.4. DisplayPort Power
This power is provided by the DisplayPort source and sink to power up attached devices such as a Branch device or an Active Cable Assembly.
As per the VESA DisplayPort Standard, the maximum current drawn by an attached device is 0.5 A at 3.3V setting.
1.1.5. Bitec DisplayPort Daughter Card Revisions
The schematic diagrams of the Bitec HSMC and FMC DisplayPort daughter cards show the connectivity for Intel FPGA development boards.
Revision | Release Date | Change | Note |
---|---|---|---|
Rev. 11 | August 2018 | Added MCD6000C1 Retimer at RX. |
|
Rev. 10 | May 2017 | Added Parade Technologies Retimer (PS8460) on RX. |
VESA DisplayPort PHY CTS version 1.4 passed in Intel® Arria® 10 device. Note: The production of Bitec FMC daughter card Rev. 10 has been
discontinued. However, Intel still
supports the daughter card to be used with DisplayPort Intel® FPGA IP designs.
|
Rev. 8 | November 2017 | – |
|
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel FPGA IP Interface
Document Version | Changes |
---|---|
2020.04.13 |
|
2020.01.10 |
|
2018.01.22 |
|
2015.11.02 | Initial release. |