Timing model adjustment on I/O-to-Core and Core-to-I/O for
MAX® 10 ES devices
Updated Timing Model in the Quartus II software version 15.0
The ADC prescalar in the 10M08 ES devices does not meet datasheet specifications, affecting gain error and total harmonic
distortion (THD) specifications. Other specifications related to prescalar are not affected. This issue will be fixed in production
Table 2. Gain Error and Drift Specifications for 10M08 ES Devices
Gain error and drift
With prescalar on
With prescalar on
Table 3. Total Harmonic Distortion Specifications for 10M08 ES Devices
Total Harmonic Distortion
FIN = 50 kHz, FS = 1 MHz, PLL, Prescalar enabled
HBM ESD performance for 10M08 ES devices is below target levels (CDM meets targets). Altera will improve ESD performance in
As per JEDEC document JESD625b, follow the standard ESD handling guidelines, particularly for human handling, (i.e. wear proper
ground strap) when handling 10M08 ES devices.
Timing Model Adjustment
To better align the
Quartus® II timing models with silicon characterization, Altera recommends adjusting the timing for I/O-to-Core and Core-to-I/O data
MAX® 10 ES devices. For temporary solution, add 300 ps (0.3 ns) clock uncertainty in TimeQuest Timing Analyzer.
To add 300 ps (0.3 ns) clock uncertainty in TimeQuest Timing Analyzer, add the following constraints in the Synopsys Design
Constraints File (.sdc):
After adding the .sdc file constraint, a clock uncertainty row is added in Data Required Path in the timing report.
Figure 1. Timing Report Before 300 ps Clock Uncertainty is Added
Figure 2. Timing Report After 300 ps Clock Uncertainty is Added
Device Guidelines for MAX 10 ES Devices
This guidelines sheet provides Altera's recommended guidelines when using
MAX® 10 ES devices.
ES devices are not intended to be used for volume production or device
ES devices are intended to be used at nominal voltage and nominal
temperature only for DDR3 EMIF support.
Recommended Power-up Sequencing for MAX 10 ES Devices
To ensure the minimum current draw during power up and configuration for
MAX® 10 dual supply ES devices, follow the recommended power-up sequence as shown in the figure below.
Figure 3. Recommended Power-up Sequence. The power rails in each group must be ramped up to a minimum of 90% of their full rail before the next group starts.
Full Chip Erase Prior to Initial Device Programming
You must perform a full chip erase prior to device programming when you use the
MAX® 10 device for the first time. The full chip erase prevents the reconfiguration watchdog timer from timing out. The full chip
erase must be done only prior to initial programming.
For full chip erase, follow these steps:
Quartus® II Programmer.
In the Programmer window, click Hardware Setup and select USB Blaster.
Click Auto Detect on the left pane.
Select the device and set the Erase column as shown in the following figure.
Click Start to start full chip erase.
Figure 4. The Quartus II Programmer
This migration guidelines is applicable if you plan to use
MAX® 10 SC or SF variant (for single supply devices) and DC or
DF variant (for dual supply devices) in production devices.
Altera recommends designing your board with
MAX® 10 ES device SA or DA variant according to the
recommendation for SC or SF variant (for single supply devices) and DC or DF variant
(for dual supply devices). There are cross variants pin mismatches between
MAX® 10 ES devices and
MAX® 10 production devices. You can migrate
the pins as recommended in the following tables without impact to your design.
MAX® 10 Devices
Migration from ES Device SA Variant to Production Device SC or SF
MAX® 10 ES Device SA Variant Pin
MAX® 10 Production Device SC or SF Variant Pin
MAX® 10 Devices Migration from ES
Device DA Variant to Production Device DC or DF Variant
MAX® 10 ES Device DA Variant Pin
MAX® 10 Production Device DC or DF Variant Pin
Document Revision History
Updated the note in Device Errata and
Device Guidelines chapters: ES devices are not intended to be used for
volume production or device qualification testing.
Added EMIF guideline: ES devices are intended to be used at
nominal voltage and nominal temperature only for DDR3 external
memory interface (EMIF) support.
Removed transient current guidelines.
Added Migration Guidelines.
Added total harmonic distortion specifications for 10M08 ES devices in ADC Prescalar errata.