FPGA Interface Manager Data Sheet for Intel FPGA Programmable Acceleration Card D5005
The FPGA Interface Manager (FIM) data sheet provides the key parameters to
which you must design your Accelerator Functional Unit (AFU).
The FIM consists of the following:
FPGA Interface Unit (FIU): The platform
interface layer that acts as a bridge between
and Core Cache Interface (CCI-P).
Core Cache Interface (CCI-P): standard
interface AFUs use to communicate with
External Memory Interface (EMIF)
High-Speed Serial Interface (HSSI) for external
Each of these components have parameter values that must be met by the AFU.
Intel® FPGA PAC D5005
FIM and AFU Parameter Data
Use the following tables in conjunction with the
Accelerator Functional Unit (AFU) Developer's Guide
Intel® Acceleration Stack for Intel®
Xeon® CPU with FPGAs
Core Cache Interface (CCI-P) Reference Manual to complete your AFU design.
Physical Coding Sublayer (PCS) + Physical Medium
Attachment (PMA) Sublayer
For more information about the Networking Interface for the
Intel® FPGA PAC D5005, please contact your Intel support representative to obtain the
Networking Interface for Open Programmable Acceleration
Engine User Guide.
The clocks of the PR HSSI Interface synchronize the unified data interface
between the MAC IP and the HSSI PHY.
signal directions listed for HSSI ports are from the perspective of the FIM. The
signals listed below are identical for both QSFP28 interfaces.
Table 7. Clock Signals
The fPLL generates a 156.25MHz in the HSSI
PHY from a 644.53125MHz QSFP28 external reference clock.
Only f2a_tx_parallel_clk_x1 is used, while
The f2a_tx_parallel_clk_x1 and
are identical clocks driven by the same source,
which also drives the rx_coreclkin
inputs of all 4 channels of the Native PHY IP cores.
All transmit data from the MAC to the HSSI
PHY is synchronous to f2a_tx_parallel_clk_x1 and f2a_rx_parallel_clk_x1.
All receive data to the MAC
from the HSSI PHY is synchronous to f2a_tx_parallel_clk_x1 and f2a_rx_parallel_clk_x1.
The fPLL generates a 312.5MHz in the HSSI PHY
from a 644.53125MHz QSFP28 external reference clock.
Only f2a_tx_parallel_clk_x2 is used, while
The f2a_tx_parallel_clk_x2 and
are identical clocks driven by the same
Same signal as f2a_tx_parallel_clk_x1.
Same signal as f2a_tx_parallel_clk_x2.
Data Interface and Signals
The HSSI unified data interface conforms to the
Stratix® 10 FPGA
Transceiver Native PHY IP core with enhanced PCS in 10GBase-R mode. It consists of
generic parallel data and encoding control interfaces for transmit and receive that
are mapped to specific signaling behavior as outlined in the
Stratix® 10 L- and H-Tile Transceiver PHY User Guide. The unified
data interface also includes flow control ports to manage passing data to and from
the HSSI PHY interface.
The table below provides a cross reference from the hssi:raw_pr
unified data interface signals to the
Stratix® 10 FPGA Transceiver
Native PHY IP core with enhanced PCS signal set. The HSSI PHY IP is configured in
Configuration-3, PMA width-32, FPGA Fabric width-66, making the gearbox ratio 32:66.
The TX Core FIFO is configured in Phase Compensation mode. The RX Core FIFO is
configured in 10GBase-R mode. The Simplified Data Interface is disabled. The
Double-Rate Transfer is disabled. For detailed information on these signals, refer
to the PCS-Core Interface Ports: Enhanced
Table 8. Data Signals
Native PHY IP
Transmit and Receive Data and Encoding Control
The PR HSSI Interface provides signals for HSSI PHY PCS status and transceiver
loopback control. The signal behavior conforms to the
Stratix® 10 FPGA Transceiver Native PHY IP core with enhanced PCS. The below
table cross references the HSSI port names to the Native PHY IP port names.
Table 9. Control and Status Signals
Native PHY IP
synchronizers to cross clock domains to your preferred clock