The EPCQ-A devices are conditionally compatible for a direct
migration from EPCQ and EPCS devices.
You must consider the following items to determine the compatibility and the
next step of action for a successful device migration.
If you are using
cores, you may need to regenerate and recompile your design. In certain conditions, the
programming files can be reused without recompilation. Refer to IP Core Compatibility for more information about
to Table 3 if you are not
using IP cores that interface with the configuration device.
Pins, Package and Capacity
Migration can only be done to an EPCQ-A device that has sufficient capacity
for the programming file and have the same pin count package.
Pin 3 (nRESET) on the EPCQ64A and EPCQ128A
devices act as a reset pin. This pin has an internal pull-up, and if you do not use the
reset function, connect the nRESET pin to either VCC or leave it unconnected. Refer to Pin Information for more information about
the pin-outs and descriptions.
Figure 1. EPCS to EPCQ Migration Pin Package and Capacity Summary
The dummy clock requirement of the fast read (0Bh) and extended quad input fast read (EBh)
EPCQ—the dummy clock is configurable with the non-volatile configuration
register (NVCR). When the EPCQ is used with a
Arria® V or
device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing
mode and ASx1 or ASx4 configuration. However, in EPCQ-A devices, the dummy clock is fixed
at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you
must regenerate the programming files, such as .pof,
.jic, and .rpd.
EPCS—the dummy clock is fixed at 8 for fast read, therefore you do not
have to regenerate the programming files if all other conditions are met.
Table 3 defines the need to
regenerate the programming files. Refer to IP Core and Programming File Migration Guideline for more information
about the conditions.
Status Register contains the Top/Bottom (TB) bit (bit 5), Block Protect
(BP) bits (bit 4, bit 3, bit 2) for sector protection bits. EPCS devices do not have TP bit
and some EPCQ device densities have BP3 (bit 6), while bit 6 is reserved in EPCQ-A devices.
Due to this differences, you may need to recompile the programming file if your design uses
the sector protect feature. Refer to Status Register for more information about status registers and sector protect bits.
All of the EPCS, EPCQ and
devices have the sector size of 512kb except for EPCS128 which has 2Mb. This impacts the
sector erase operation. If the design is erasing the flash during user mode, you must update
your design to comply the sector size when migrating from EPCS128 to EPCQ128A. After
updating your design, regenerate a new programming file for the EPCQ-A device.
1.2. Software Migration Guidelines
When you use a
legacy device that is not supported in the
Quartus® Prime software version 17.1 and
later and you need to modify your design to migrate the configuration device to EPCQ-A, you need
to use 13.1.4 patch 4.70r. For more information, refer to the readme patch instructions and the
patches for Windows and Linux in the Software Download page of the FPGA
Configuration Devices Support website.
1 Enhanced SFL is an option available in the
Serial Flash Loader IP core when using with devices earlier than
1.2.2. Programming File Compatibility
Note: This section describes programming file
compatibility for designs without
Intel® FPGA IP
List of supported programming files:
Programmer Object File (.pof)
JTAG Indirect Configuration File (.jic)
Raw Programming Data (.rpd)
STAPL File (.jam/.jbc)
Serial Vector Format (.svf)
Note: Compression and encryption would not affect the programming file
Table 3. Programming File Compatibility Guide
Note: For designs that do not
contain IP cores which interface with the configuration device, depending upon the FPGA
family and configuration scheme implemented, the existing programming files may be
compatible with EPCQ-A devices without the need to regenerate the programming
10 The FPGA 2.5V I/O VOH
level is insufficient to achieve EPCQ or EPCQ-A VIH threshold across entire voltage
11 The minimum VOH for 3V or
3.3V LVTTL is 2.4V in the
Intel® FPGA device. This specification is
based on the worst condition. Since the input current of EPCQ and
EPCQ-A is small enough, the VOH of
Intel® FPGA device
does not violate the minimum VIH of EPCQ
and EPCQ-A in the usual usage.
Intel® recommends that you perform simulation
using the IBIS model to ensure the required specifications are
12 0.2 V for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A.
0.4 V is for EPCQ4A
1.3.2. Timing Specifications
The following tables show the general comparison of the EPCS, EPCQ, and EPCQ-A
operation timing. For more detailed and up-to-date information, refer to the
respective device datasheet.
You need to take note
of these values to avoid from the migration to fail:
In AS configuration scheme, the FPGA will initiate the configuration process
after POR. During the configuration process, the FPGA issues flash operation commands such as
read device ID, normal read and erase bulk. You must ensure that the FPGA is able to read the
data correctly from the configuration devices. This is done by ensuring the setup time, tDSU and hold time, tDH meets the
requirements explained in the respective FPGA device datasheets. To evaluate the tDSU and tDH in your system, follow the
Figure 7. FPGA to EPCQ-A Board Trace Block Diagram
The data setup timing slack must be equal or larger than the minimum data
setup time, tDSU
tDCLK – (tBT_DCLK + tCLQV + tBT_DATA) ≥ tDSU
The hold timing slack must be equal or larger than the minimum data hold
tBT_DCLK + tCLQX +
tBT_DATA ≥ tDH
tDCLK = Period for a DCLK cycle
tBT_DCLK = Board trace propagation delay for
DCLK from FPGA to EPCQ-A
tCLQV = Clock low to output valid
tCLQX = Output hold time
tBT_DATA = Board trace propagation delay for
Data from EPCQ-A to FPGA