The main modules of the HPS are:

• MPU subsystem featuring a dual-core Arm* Cortex^®-A9 MPCore processor
• General-purpose direct memory access (DMA) controller
• Two Ethernet media access controllers (EMACs)
• Two USB 2.0 on-the-go (OTG) controllers
• NAND flash controller
• Quad SPI flash controller
• Secure digital/multimedia card (SD/MMC) controller
• Two serial peripheral interface (SPI) master controllers
• Two SPI slave controllers
• Four inter-integrated circuit (I²C) controllers¹
• 64 KB on-chip RAM
• 64 KB on-chip boot ROM
• Two UARTs
• Four timers
• Two watchdog timers
• Three general-purpose I/O (GPIO) interfaces
• Arm* CoreSight* debug components:
  • Debug access port (DAP)
  • Trace port interface unit (TPIU)
  • System trace macrocell (STM)
  • Program trace macrocell (PTM)
  • Embedded trace router (ETR)
  • Embedded cross trigger (ECT)
• System manager
• Clock manager
• Reset manager
• Scan manager
• FPGA manager
• SDRAM controller subsystem

The MPU subsystem provides the following functionality:

• Arm* Cortex^®-A9 MPCore*
  • Two Arm* Cortex^®-A9 processors
  • NEON™ single instruction, multiple data (SIMD) coprocessor and vector floating-point v3 (VFPv3) per processor
  • Snoop control unit (SCU) to ensure coherency
  • Accelerator coherency port (ACP) that accepts coherency memory access requests
  • Interrupt controller
  • One general-purpose timer and one watchdog timer per processor
  • Debug and trace features
  • 32 KB instruction and 32 KB data level 1 (L1) caches per processor
  • Memory management unit (MMU) per processor
• Arm* L2-310 level 2 (L2) cache
  • Shared 512 KB L2 cache
• ACP ID mapper
  • Maps the 12-bit ID from the level 3 (L3) interconnect to the 3-bit ID supported by the ACP

A programmable address filter in the L2 cache controls which portions of the 32-bit physical address space can be accessed by each master.

The HPS–FPGA memory-mapped interfaces provide the major communication channels between the HPS and the FPGA fabric. The HPS–FPGA memory-mapped interfaces include:

• FPGA–to–HPS bridge—a high–performance bus with a configurable data width of 32, 64, or 128 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS. This interface allows the FPGA fabric to have full visibility into the HPS address space. This interface also provides access to the coherent memory location
• HPS–to–FPGA bridge—a high–performance interface with a configurable data width of 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric
• Lightweight HPS–to–FPGA bridge—an interface with a 32–bit fixed data width, allowing the HPS to master transactions to slaves in the FPGA fabric. This lower–bandwidth interface is useful for accessing the control and status registers of soft peripherals

HPS and FPGA fabric masters have access to the SDRAM controller subsystem.

The SDRAM controller subsystem implements the following high‑level features:

• Support for double data rate 2 (DDR2), DDR3, and low-power double data rate 2 (LPDDR2) devices
• Error correction code (ECC) support, including calculation, single‑bit error correction and write-back, and error counters
• Fully-programmable timing parameter support for all JEDEC‑specified timing parameters
• All ports support memory protection and mutual accesses
• FPGA fabric interface with up to six ports that can be combined for a data width up to 256-bits wide using Avalon-MM and AXI interfaces.

The SDRAM controller subsystem is composed of the SDRAM controller, DDR PHY, control and status registers and their associated interfaces.

The on-chip RAM offers the following features:

• 64 KB size
• 64-bit slave interface
• High performance for all burst lengths

The boot ROM offers the following features:

• 64 KB size
• Contains the code required to support HPS boot from cold or warm reset
• Used exclusively for booting the HPS

The NAND flash controller is based on the Cadence^® Design IP^® NAND Flash Memory Controller and offers the following functionality and features:

• Supports one x8 NAND flash device
• Supports Open NAND Flash Interface (ONFI) 1.0
• Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, and ST Micro
• Supports programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction) ECC sector size
• Supports pipeline read-ahead and write commands for enhanced read/write throughput
• Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
• Supports multiplane devices
• Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB
• Supports single-level cell (SLC) and multi-level cell (MLC) devices with programmable correction capabilities
• Provides internal DMA
• Provides programmable access timing

The quad SPI flash controller is based on the Cadence Quad SPI Flash Controller and offers the following features:

• Supports SPIx1, SPIx2, or SPIx4 (Quad SPI) serial NOR flash devices
• Supports direct access and indirect access modes
• Supports single, dual, and quad I/O instructions
• Support up to four chip selects
• Programmable write-protected regions
• Programmable delays between transactions
• Programmable device sizes
• Support eXecute-In-Place (XIP) mode
• Programmable baud rate generator to generate device clocks

The Secure Digital (SD), Multimedia Card (MMC), (SD/MMC) and CE-ATA host controller is based on the Synopsys* DesignWare* Mobile Storage Host controller and offers the following features:

• Integrated descriptor-based DMA
• Supports CE-ATA digital protocol commands
• Supports single card
• Single data rate (SDR) mode only
• Programmable card width: 1-, 4-, and 8-bit
• Programmable card types: SD, SDIO, or MMC
• Up to 64 KB programmable block size
• Supports the following standards and card types:
  • SD, including eSD—version 3.0²
  • SDIO, including embedded SDIO (eSDIO)—version 3.0³
  • CE‑ATA—version 1.1
• Supports various types of multimedia cards, MMC version 4.41⁴
  • MMC: 1-bit data bus
  • Reduced-size MMC (RSMMC): 1-bit and 4-bit data bus
  • MMCMobile: 1-bit data bus
  • MMCPlus: 1-bit, 4-bit, and 8-bit data bus
  • Default speed and high speed
• Supports embedded MMC (eMMC) version 4.41⁵
  • 1-bit, 4-bit and 8-bit data bus

The clock manager offers the following features:

• Manages clocks for HPS
• Supports dynamic clock tuning

The reset manager manages both hardware and software reset sources in the HPS. Reset status is also provided. Reset types include cold, warm, and debug. Reset behavior depends on the type.

The scan manager is used to configure and manage HPS I/O pins and to communicate with the FPGA JTAG.

The DMA controller provides high-bandwidth data transfers for modules without integrated DMA controllers. The DMA controller is based on the Arm* Corelink* DMA Controller (DMA‑330) and offers the following features:

• Micro-coded to support flexible transfer types
  • Memory-to-memory
  • Memory-to-peripheral
  • Peripheral-to-memory
  • Scatter-gather
• Supports up to eight channels
• Supports flow control with 31 peripheral handshake interfaces
• Software can schedule up to 16 outstanding read and 16 outstanding write instructions
• Supports nine interrupt lines: one for DMA thread abort and eight for external events

The FPGA manager offers the following features:

• Manages configuration of the FPGA portion of the device
• 32-bit fast passive parallel configuration interface to the FPGA CSS block
• Partial reconfiguration
• Compressed FPGA configuration images
• Advanced Encryption Standard (AES) encrypted FPGA configuration images
• Monitors configuration-related signals in FPGA
• Provides 32 general-purpose inputs and 32 general-purpose outputs to the FPGA fabric

The two EMACs are based on the Synopsys* DesignWare* 3504‑0 Universal 10/100/1000 Ethernet MAC and offer the following features:

• Supports 10, 100, and 1000 Mbps standard
• Supports RGMII external PHY interface
  • Media independent interface (MII)
  • Gigabit media independent interface (GMII)
  • Reduced gigabit media independent interface (RGMII)
  • Serial gigabit media independent interface (SGMII) with additional external conversion logic
• Provides full GMII interface when using FPGA interface
• Integrated DMA controller
• Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
• IEEE 802.3-az, version D2.0 of Energy Efficient Ethernet
• Supports IEEE 802.1Q VLAN tag detection for reception frames
• Supports a variety of address filtering modes
• Management of PHY through Management data input/output (MDIO) interface or optionally, I²C interface

The HPS provides two USB 2.0 Hi-Speed On-the-Go (OTG) controllers from Synopsys DesignWare. The USB controller signals cannot be routed to the FPGA like those of other peripherals; instead they are routed to the dedicated I/O.

Each of the USB controllers offers the following features:

• Complies with the following specifications:
  • USB OTG Revision 1.3
  • USB OTG Revision 2.0
  • Embedded Host Supplement to the USB Revision 2.0 Specification
• Supports software-configurable modes of operation between OTG 1.3 and OTG 2.0
• Supports all USB 2.0 speeds:
  • High speed (HS, 480-Mbps)
  • Full speed (FS, 12-Mbps)
  • Low speed (LS, 1.5-Mbps)
    Note: In host mode, all speeds are supported; however, in device mode, only high speed and full speed are supported.
• Local buffering with Error Correction Code (ECC) support
  Note:

  The USB 2.0 OTG controller does not support the following interface standards:

  • Enhanced Host Controller Interface (EHCI)
  • Open Host Controller Interface (OHCI)
  • Universal Host Controller Interface (UHCI)
• Supports USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) PHYs (SDR mode only)
• Supports up to 16 bidirectional endpoints, including control endpoint 0
  Note: Only seven periodic device IN endpoints are supported.
• Supports up to 16 host channels
  Note: In host mode, when the number of device endpoints is greater than the number of host channels, software can reprogram the channels to support up to 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints.
• Supports generic root hub
• Supports automatic ping capability

The HPS provides three GPIO interfaces that are based on Synopsys* DesignWare* APB* General Purpose Programming I/O peripheral and offer the following features:

• Supports digital de-bounce
• Configurable interrupt mode
• Supports up to 71 I/O pins and 14 input-only pins, based on device variant

The following table shows the HPS address spaces and their sizes.

Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space has the peripheral, FPGA slaves, SDRAM window, and boot regions.

The following figure shows the relationships between the HPS address spaces. The figure is not to scale.

The window regions provide access to other address spaces. The thin black arrows indicate which address space is accessed by a window region (arrows point to accessed address space). For example, accesses to the ACP window in the L3 address space map to a 1 GB region of the MPU address space.

The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to “MPU Address Space”.

The ACP window can be mapped to any 1 GB region in the MPU address space (blue vertical bidirectional arrow), on gigabyte-aligned boundaries.

The L3 address space is 4 GB and applies to all L3 masters except the MPU. The L3 address space has more configuration options than the other address spaces.

Each peripheral slave interface has a dedicated address range in the peripheral region. The table below lists the base address and address range size for each slave.

The L4 peripheral clocks, denoted by l4_mp_clk, range up to 200 MHz.

For more information about the specific peripheral clocks, refer to their respective chapters.

Unused clock outputs should be set to a safe frequency such as 50 MHz to reduce power consumption and improve system stability.

The clock in the OSC1 clock group is derived directly from the HPS_CLK1 pin. This clock is never gated or divided.

HPS_clk1 is used as a PLL input and also by HPS logic that does not operate on a clock output from a PLL.

The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are derived from the main PLL. The main PLL is always sourced from the HPS_CLK1 pin of the device.

mpu_base_clk

main_base_clk

dbg_base_clk

main_qspi_base_clk

main_nand_sdmmc_base_clk

cfg_h2f_user0_base_clk

The counter outputs from the main PLL can have their frequency further divided by programmable dividers external to the PLL. Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example the clock transitions on cycle 15 of the divide‑by‑16 divider for the main C2 output and cycle 3 of the divide‑by‑4 divider for the main C0 output.

The following figure shows how each counter output from the main PLL can have its frequency further divided by programmable post‑PLL dividers. Green-colored clock gating logic is directly controlled by software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks.

The clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that a clean transition occurs, and can have the following control values changed dynamically by software write accesses to the control registers:

• PLL bypass
• PLL numerator, denominator, and counters
• External dividers

For these registers, hardware detects that the write has occurred and performs the correct sequence to ensure that a glitch-free transition to the new clock value occurs. These clocks can pause during the transition.

mpu_clk

mpu_l2_ram_clk

mpu_periph_clk

l3_main_clk

l3_mp_clk

l3_sp_clk

l4_main_clk

l4_mp_clk

l4_sp_clk

dbg_at_clk

dbg_trace_clk

dbg_timer_clk

dbg_clk

main_qspi_clk

main_nand_sdmmc_clk

cfg_clk

h2f_user0_clock

The peripheral clock group consists of a PLL, dividers, and clock gating. The clocks in the peripheral clock group are derived from the peripheral PLL. The peripheral PLL can be programmed to be sourced from the HPS_CLK1 pin, the HPS_CLK2 pin, or the f2h_periph_ref_clk clock provided by the FPGA fabric.

The counter outputs from the main PLL can have their frequency further divided by external dividers. Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example, the clock transitions on cycle 15 of the divide‑by‑16 divider for the main C2 output and cycle 3 of the divide‑by‑4 divider for the C1 output.

emac0_base_clk

emac1_base_clk

periph_qspi_base_clk

periph_nand_sdmmc_base_clk

periph_base_base_clk

h2f_user1_base_clk

The following figure shows programmable post-PLL dividers and clock gating for the peripheral clock group. Clock gate blocks in the diagram indicate clocks that may be gated off under software control. Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.

usb_mp_clk

spi_m_clk

emac0_clk

emac1_clk

l4_mp_clk

l4_sp_clk

gpio_db_clk

h2f_user1_clock

Flash memory peripherals can be driven by the main PLL, the peripheral PLL, or from clocks provided by the FPGA fabric.

qspi_clk

nand_x_clk

nand_clk

sdmmc_clk

The clock manager provides one interrupt output which is enabled using the interrupt enable register (intren). The interrupt is the OR of the bits in the interrupt status register (inter) that indicate lock and loss of lock for each of the three PLLs.

The following table lists every clock input generated by the clock manager to all modules in the HPS. System clock names are global for the entire HPS and system clocks with the same name are phase-aligned at all endpoints.

mpu_clk

mpu_periph_clk

dbg_at_clk

dbg_clk

mpu_l2_ram_clk

l4_mp_clk

l3_main_clk

dbg_at_clk

dbg_clk

l3_mp_clk

l4_mp_clk

usb_mp_clk

nand_x_clk

cfg_clk

l3_sp_clk

l3_main_clk

mpu_l2_ram_clk

osc1_clk

spi_m_clk

l4_sp_clk

l4_mp_clk

l3_main_clk

l3_main_clk

l4_main_clk

dbg_at_clk

l4_mp_clk

cfg_clk

l4_mp_clk

l3_main_clk

l4_mp_clk

l3_main_clk

l4_mp_clk

l4_mp_clk

l4_mp_clk

qspi_clk

l4_mp_clk

sdmmc_clk

l4_mp_clk

emac0_clk

osc1_clk

l4_mp_clk

emac1_clk

osc1_clk

usb_mp_clk

usb_mp_clk

nand_x_clk

nand_clk

osc1_clk

osc1_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_sp_clk

l4_mp_clk

gpio_db_clk

l4_mp_clk

gpio_db_clk

l4_mp_clk

gpio_db_clk

osc1_clk 

l4_sp_clk

ddr_dq_clk

ddr_dqs_clk

ddr_2x_dqs_clk

mpu_l2_ram_clk

l3_main_clk

osc1_clk

osc1_clk

spi_m_clk

spi_m_clk

l4_main_clk

l4_main_clk

l4_mp_clk

dbg_clk

dbg_at_clk

dbg_trace_clk

osc1_clk

l4_sp_clk

spi_m_clk

dbg_timer_clk

The address map and register definitions for the HPS-FPGA bridge consist of the following regions:

• Clock Manager Module

Base Address: 0xFFD04000

Clock Manager Module

Main PLL Group

Peripheral PLL Group

SDRAM PLL Group

Altera Group

Base Address: 0xFFD04000