The main modules of the HPS are:

• MPU subsystem featuring a dual-core Arm* Cortex*-A9 MPCore* processor
• System interconnect that includes three memory-mapped interfaces between the HPS and FPGA:
  • HPS-to-FPGA: 32-, 64-, or 128-bit wide AXI-4
  • Lightweight HPS-to-FPGA: 32-bit wide AXI-4
  • FPGA-to-HPS: 32-, 64-, or 128-bit wide ACE
• General-purpose direct memory access (DMA) controller
• Security manager
• Supports peripheral memories with single-error correction and double-error detection (SECDED)
• Three Ethernet media access controllers (EMACs)
• Two USB 2.0 on-the-go (OTG) controllers
• NAND flash controller
• Quad serial peripheral interface (QSPI) flash controller
• Secure digital/multimedia card (SD/MMC) controller
• Two serial peripheral interface (SPI) master controllers
• Two SPI slave controllers
• Five inter-integrated circuit (I²C) controllers¹
• 256 KB on-chip RAM
• 128 KB on-chip boot ROM
• Two UARTs
• Four system timers
• Two watchdog timers
• Three general-purpose I/O (GPIO) interfaces
• Arm* CoreSight* debug components:
  • Debug access port (DAP)
  • Trace port interface unit (TPIU)
  • System trace macrocell (STM)
  • Program trace macrocell (PTM)
  • Embedded trace router (ETR)
  • Embedded cross trigger (ECT)
• System manager
• Clock manager
• Reset manager
• FPGA manager

The MPU subsystem is a stand-alone, full-featured Arm* Cortex*-A9 MPCore* dual-core 32-bit application processor. It provides the following functionality:

• Arm* Cortex*-A9 MPCore*
  • Two Arm* Cortex*-A9 processors
  • NEON* single instruction, multiple data (SIMD) coprocessor and vector floating-point v3 (VFPv3) per processor
  • Snoop control unit (SCU) to ensure coherency between processors
  • Accelerator coherency port (ACP) that accepts coherency memory access requests
  • Interrupt controller
  • One general-purpose timer and one watchdog timer per processor
  • Debug and trace features
  • 32 KB instruction and 32 KB data level 1 (L1) caches per processor
  • Memory management unit (MMU) per processor
• Arm* L2-310 level 2 (L2) cache
  • Shared 512 KB L2 cache

As shown in the "HPS Block Diagram", the L2 cache has one 64-bit master port that is connected to the main L3 interconnect and one 64-bit master port connected to the SDRAM L3 interconnect. A programmable address filter in the L2 cache controls which portions of the 32-bit physical address space can be accessed by each master.

The HPS–FPGA memory-mapped interfaces provide the major communication channels between the HPS and the FPGA fabric. The HPS–FPGA memory-mapped interfaces include:

• FPGA–to–HPS bridge—a high–performance bus with a configurable data width of 32, 64, or 128 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS. This interface allows the FPGA fabric to have full visibility into the HPS address space. This interface also provides access to the coherent memory interface
• HPS–to–FPGA bridge—a high–performance interface with a configurable data width of 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric
• Lightweight HPS–to–FPGA bridge—an interface with a 32–bit fixed data width, allowing the HPS to master transactions to slaves in the FPGA fabric

The SDRAM L3 interconnect is part of the system interconnect and connects the HPS to the hard memory controller that is located in the FPGA fabric. The SDRAM L3 interconnect is composed of the SDRAM adapter and the SDRAM scheduler, which are secured by firewalls. It supports Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) quality of service (QoS) for the fabric interfaces

The hard memory controller implements the following high-level features:

• Support for double data rate 3 (DDR3) and DDR4 devices
• Software-configurable priority scheduling on individual SDRAM bursts
• Error correction code (ECC) support, including calculation, single‑bit error correction and write-back, and error counters
• Fully-programmable timing parameter support for all JEDEC‑specified timing parameters
• All ports support memory protection and mutual-exclusive accesses
• FPGA-to-SDRAM interface—a configurable interface to the SDRAM scheduler in the SDRAM L3 interconnect You can configure the following parameters:
  • Up to three bridges
  • Up to 288 bits across all three ports

The on-chip RAM offers the following features:

• 256 KB size
• 64-bit slave interface
• High performance for all burst lengths
• ECC support provides detection of single–bit and double–bit errors and correction for single-bit errors
• Can clear the on-chip RAM on reset

The boot ROM offers the following features:

• 32-bit interface
• Capable of data transfers for every clock cycle
• 128 KB size
• Contains the code required to support both secure and non-secure HPS boot from cold or warm reset
• Used exclusively for booting the HPS

The NAND flash controller is based on the Cadence^® Design IP^® NAND Flash Memory Controller and offers the following functionality and features:

• Supports up to four chip selects. One chip select is connected to an HPS I/O pin and the rest can be connected to the FPGA I/O pins.
• Integrated descriptor-based DMA controller
• 8-bit and 16-bit ONFI 1.0 NAND flash devices
• Programmable page sizes of 512 bytes, 2 KB, 4 KB, and 8 KB
• Supports 32, 64, 128, 256, 384, and 512 pages per block
• Programmable hardware ECC for single-level cell (SLC) and multi-level cell (MLC) devices
• 512-byte ECC sector size with 4-, 8-, or 16-bit correction
• 1 KB ECC sector size with 24-bit correction

The quad SPI flash controller is used for access to serial NOR flash devices. It supports standard SPI flash devices as well as high-performance dual and quad SPI flash devices. The Quad SPI flash controller is based on the Cadence Quad SPI Flash Controller and offers the following features:

• Supports SPIx1, SPIx2, or SPIx4 (Quad SPI) serial NOR flash devices
• Supports direct access and indirect access modes
• Supports single, dual, and quad I/O instructions
• Support up to four chip selects
• Programmable write-protected regions
• Programmable delays between transactions
• Programmable device sizes
• Support eXecute-In-Place (XIP) mode
• Programmable baud rate generator to generate device clocks

The Secure Digital (SD), Multimedia Card (MMC), (SD/MMC) and CE-ATA host controller is based on the Synopsys* DesignWare* Mobile Storage Host controller and offers the following features:

• Integrated descriptor-based DMA
• Supports CE-ATA digital protocol commands
• Supports single card
• Single data rate (SDR) mode only
• Programmable card width: 1-, 4-, and 8-bit
• Programmable card types: SD, SDIO, or MMC
• Up to 64 KB programmable block size
• Supports the following standards and card types:
  • SD, including eSD—version 3.0²
  • SDIO, including embedded SDIO (eSDIO)—version 3.0³
  • CE‑ATA—version 1.1
• Supports various types of multimedia cards, MMC version 4.41⁴
  • MMC: 1-bit data bus
  • Reduced-size MMC (RSMMC): 1-bit and 4-bit data bus
  • MMCMobile: 1-bit data bus
• Supports embedded MMC (eMMC) version 4.5⁵
  • 1-bit, 4-bit, and 8-bit data bus

The reset domains and sequences support several security features. The security manager brings the reset manager out of reset only when device security is confirmed. Afterwards, the reset manager brings the rest of the HPS system out of reset. The reset manager performs the following functions:

• Manages resets for HPS
• Controls the resets for cold, warm, debug, and TAP reset domains
• Controls the RAM clearing domain separately

The HPS provides four 32-bit general-purpose timers connected to the level 4 (L4) peripheral bus. The four system timers are based on the Synopsys DesignWare Advanced Peripheral Bus (APB) Timers peripheral and offer the following features:

• 32-bit timer resolution
• Free-running timer mode
• Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock frequency)
• Interrupt generation

The DMA controller provides high-bandwidth data transfers for modules without integrated DMA controllers. The DMA controller is based on the Arm* Corelink* DMA Controller (DMA‑330) and offers the following features:

• Micro-coded to support flexible transfer types
  • Memory-to-memory
  • Memory-to-peripheral
  • Peripheral-to-memory
  • Scatter-gather
• Supports up to eight channels
• Supports flow control with 32 peripheral handshake interfaces

The FPGA manager manages and monitors the FPGA portion of the SoC device. The FPGA manager can configure the FPGA fabric from the HPS, monitor the state of the FPGA, and drive or sample signals to or from the FPGA fabric.

ECC controllers provide single- and double-bit error memory protection for integrated on-chip RAM and peripheral RAMs within the HPS.

The HPS provides two USB 2.0 Hi-Speed On-the-Go (OTG) controllers from Synopsys DesignWare. The USB controller signals cannot be routed to the FPGA like those of other peripherals; instead they are routed to the dedicated I/O.

Each of the USB controllers offers the following features:

• Complies with the following specifications:
  • USB OTG Revision 1.3
  • USB OTG Revision 2.0
  • Embedded Host Supplement to the USB Revision 2.0 Specification
• Supports software-configurable modes of operation between OTG 1.3 and OTG 2.0
• Supports all USB 2.0 speeds:
  • High speed (HS, 480-Mbps)
  • Full speed (FS, 12-Mbps)
  • Low speed (LS, 1.5-Mbps)
    Note: In host mode, all speeds are supported; however, in device mode, only high speed and full speed are supported.
• Local buffering with Error Correction Code (ECC) support
  Note:

  The USB 2.0 OTG controller does not support the following interface standards:

  • Enhanced Host Controller Interface (EHCI)
  • Open Host Controller Interface (OHCI)
  • Universal Host Controller Interface (UHCI)
• Supports USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) PHYs (SDR mode only)
• Supports up to 16 bidirectional endpoints, including control endpoint 0
  Note: Only seven periodic device IN endpoints are supported.
• Supports up to 16 host channels
  Note: In host mode, when the number of device endpoints is greater than the number of host channels, software can reprogram the channels to support up to 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints.
• Supports generic root hub
• Supports automatic ping capability

The following table shows the HPS address spaces and their sizes.

Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space has the peripheral, FPGA slaves, SDRAM window, and boot regions.

The following figure shows the relationships between the HPS address spaces. The figure is not to scale.

The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to “MPU Address Space”.

The L3 address space is 4 GB and applies to all L3 masters except the MPU. The L3 address space has more configuration options than the other address spaces.

Each peripheral slave interface has a dedicated address range in the peripheral region. The table below lists the base address and address range size for each slave.

The L4 peripheral clocks, denoted by l4_mp_clk, range up to 200 MHz.

For more information about the specific peripheral clocks, refer to their respective chapters.

The Boot Clock (boot_clk) is used as the default clock for both cold or warm reset (Boot Mode), the Hardware Sequencer local clock and the external bypass clock reference.

The boot_clk is generated from the secure cb_intosc_hs_div2_clk or the unsecure external oscillator. boot_clk is only updated coming out of cold reset or a warm reset (boot mode request) and is not sampled at any other time.

The source of every output clock block comes from the following:

• Bypass source: boot_clock configured through fuses and security manager: registers at cold or warm reset
• Non-External Bypass: Each Clock may come from 1 of 5 sources:

Clock Output Blocks have the following features:

• Each clock output block contains an external bypass multiplexer
• Some clock output blocks contain additional dividers
• Clock gates controlled by either hardware or software are used to disable the clocks
• The MPU and NOC (includes debug clocks) blocks contain enable outputs to define clock frequency ratios to the MPU, NOC and CoreSight logic

The CSR Register logic uses an independent clock, l4_sys_free_clk, to allow the clock to be changed by software.

Updating the PLL settings wihtout a system reset will not reset the clock manager. All clocks will transition gracefully to their boot safe dividers. You can go in and out of boot mode and force the PLLs into bypass without doing a system reset. Software may reset the PLLs and reconfigure the VCO and bring it out of reset. By doing this you can safely update the PLL settings.

You can dynamically slow down the MPU clock without touching the PLL by modifying the MPU external counter register (MAINPLLGRP.MPUCLK.CNT) to slow down the MPU frequency.

The Ci dividers are used to derive lower frequencies from the PLLs. The M and N dividers can be dynamically updated without losing the PLL lock if the VCO frequency changes less than 20%. If changes greater than 20% are needed, iteratively changing the frequency in increments of less than 20% allows a slow ramp of the VCO frequency without loss of clock.

To minimize jitter, use the following guidelines:

• The VCO should be as close to maximum as possible
• It is better to use the Ci dividers than the N divider. The N divider should be kept as small as possible.
• The M divider should be minimized, but should be greater than 32.

When making any changes that affect the VCO frequency, software must put the PLL into external bypass. After changing the VCO frequency, software must wait for the PLL lock, as indicated by the intrs register or enabled interrupt, before taking the PLL out of bypass.

As shown in the "Hardware Clock Groups" and "Peripheral Clocks" figures, every clock has five possible sources. When switching between clock sources:

• Put PLL into bypass mode
• Change the mux select
• Switch back out of bypass mode
  Note: The new clock source must be active and locked before exiting bypass mode.

As shown in the "PLL Integration in Clock Manager" figure, each PLL has multiple input sources. If the input source is changed, the PLL loses VCO lock and all output clocks are not reliable. Before switching the PLL input source, software must select the boot_clk bypass for all PLL0 and PLL1 clocks. After the PLL output clocks are bypassed, software can change the PLL source and reinitialize the PLL.

Unused clock outputs should be set to a safe frequency such as 50 MHz to reduce power consumption and improve system stability.

The clock manager provides one interrupt output, which is enabled through the interrupt enable register (intren). The interrupt can be programmed to trigger twhen either the PLL achieves or loses its lock.

For complete HPS address map and register definitions, refer to the Arria 10 HPS Address Map and Register Definitions.

Base Address: 0xFFD04000

Offset: 0x0

Access: RW

ctrl Fields

This bit is only used if swctrlbtclken is set.

If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2.  If 0, boot_clk source will be from the external oscillator (HPS_CLK1 input pin that becomes signal osc1_clk in the device).

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

If set, then Software will take control of the boot_clk mux select.  If set, then swctrlbtclksel will determine the mux setting.  If not set, the security features will determine the fuse settings.

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

When set the Clock Manager is in Boot Mode.
In Boot Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to their Boot Mode settings.  All clocks will be bypassed and external HW managed counters and dividers will be set to divide by 1.
This bit should only be cleared when clocks have been correctly configured. 
This field is set on a cold reset and optionally on a warm reset. SW may set this bit to force the clocks into Boot Mode.  SW exits Boot Mode by clearing this bit.

Offset: 0x4

Access: RW

intr Fields

If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared.

If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, the Main PLL has not lost lock since this bit was cleared.

If 1, the Peripheral PLL has achieved lock at least once since this bit was cleared. If 0, the Peripheral PLL has not achieved lock since this bit was cleared.

If 1, the Main PLL has achieved lock at least once since this bit was cleared. If 0, the Main PLL has not achieved lock since this bit was cleared.

Offset: 0x8

Access: RW

intrs Fields

If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared.

If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, the Main PLL has not lost lock since this bit was cleared.

If 1, the Peripheral PLL has achieved lock at least once since this bit was cleared. If 0, the Peripheral PLL has not achieved lock since this bit was cleared.

If 1, the Main PLL has achieved lock at least once since this bit was cleared. If 0, the Main PLL has not achieved lock since this bit was cleared.

Offset: 0xC

Access: RW

intrr Fields

If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.

If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared.

If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, the Main PLL has not lost lock since this bit was cleared.

If 1, the Peripheral PLL has achieved lock at least once since this bit was cleared. If 0, the Peripheral PLL has not achieved lock since this bit was cleared.

If 1, the Main PLL has achieved lock at least once since this bit was cleared. If 0, the Main PLL has not achieved lock since this bit was cleared.

Offset: 0x10

Access: RW

intren Fields

When set to 1,the Peripheral PLL feedback cycle slipped bit is ORed into the Clock Manager interrupt output.  When set to 0, the Peripheral PLL feedback cylce slipped bit is not ORed into the Clock Manager interrupt output.

When set to 1,the Main PLL feedback cycle slipped bit is ORed into the Clock Manag