Intel Stratix 10 Analog to Digital Converter User Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 20.4 |
1. Intel Stratix 10 ADC Overview
Intel® Stratix® 10 devices contain two types of on-die sensors:
- Voltage sensor—provides digital voltage readings.
- You can use the voltage sensor to perform live monitoring of critical on-chip supply voltages and external analog signals.
- You can access the voltage readout using the Voltage Sensor Intel® FPGA IP.
- Temperature sensor—provides on-die temperature readings.
- The internal digital temperature sensor consists of internal temperature sensing diodes (TSD) and built-in ADC.
- You can monitor the on-die temperature through the internal digital temperature sensor in the Intel® Stratix® 10 core fabric and transceiver tiles.
- You can use the Temperature Sensor Intel® FPGA IP to read the digital temperature in Celsius.
- You can also access on-die TSDs using external third-party temperature sensors.
- If you want temperature reading correlation, you can use both internal and external temperature sensors simultaneously.
1.1. Release Information for Voltage Sensor and Temperature Sensor Intel FPGA IP Cores
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.1.1 |
Intel® Quartus® Prime Version | 20.4 |
Release Date | 2020.12.14 |
Item | Description |
---|---|
IP Version | 19.1.1 |
Intel® Quartus® Prime Version | 20.4 |
Release Date | 2020.12.14 |
2. Intel Stratix 10 ADC Architecture and Features
To access the voltage or internal TSD readouts, use the Voltage Sensor Intel® FPGA IP or Temperature Sensor Intel® FPGA IP. To use an external temperature sensor, connect the sensor to the Intel® Stratix® 10 external TSD pins.
2.1. Intel Stratix 10 Voltage Sensor
The voltage sensor monitors two external differential inputs and five internal power supplies. To read the voltage values through the SDM, use the Voltage Sensor IP core.
The ADC samples the voltage at regular intervals. When the Voltage Sensor IP core sends voltage sampling request to the SDM, the SDM returns the most recently read voltage value. The IP core then returns the observed voltage value as an unsigned 32-bit fixed point binary number.
The maximum value of the external analog signal (differential scale) is 1.24 V. Although the ADC supports input voltages up to 1.24 V, the Voltage Sensor IP core can monitor the internal 1.8 V VCCIO_SDM and VCCPT power supplies. A built-in voltage divider halves these voltages before the ADC measures them. The SDM then doubles the values in the ADC read outs.
2.1.1. Voltage Conversion
For example, if the returned value is 0x0000C000, the voltage value is 0.75 V.
2.2. Intel Stratix 10 Temperature Sensing Diodes
- The internal TSDs allow you to monitor the device's on-die temperature using the on-chip digital temperature sensing circuitry. The internal TSDs are available in the core fabric, transceiver tiles, and high-bandwidth DRAM memory (HBM2) stacks.
- The external TSDs allow you to monitor the device's on-die temperature using external temperature sensors. The external TSDs are available in the core fabric and transceiver tiles.
When a transceiver tile is powered down, the tile's internal TSD is not available. However, you can still sample the tile's temperature through its external TSD.
2.2.1. Internal Temperature Sensor
When the Temperature Sensor IP core sends temperature sampling request to the SDM, the SDM returns the most recently read temperature value. The IP core then returns the observed temperature value in Celsius as a signed 32-bit fixed point binary number.
2.2.1.1. Temperature Calculation for the Internal Temperature Sensor
To convert the returned value into decimal, use two's complement operation on the signed integer portion. Then, add the decimal number to the unsigned 8-bit fraction ( ). For example, if the returned value is 0xFFFFE1C0, the temperature value is -30.25°C.
The unsigned 8-bit fraction is always zero for the temperature values returned by the transceiver tiles.
2.2.2. External Temperature Sensor
The external TSD requires two pins for voltage reference. If you do not use the external TSD pins, leave the pins unconnected.
2.2.3. Temperature Sensor Channels and Locations
- To read the internal TSDs, specify the channels to sample in the cmd_data signal to the Temperature Sensor IP core.
- To read the external TSDs, connect external temperature sensors to the designated TEMPDIODE pin.
Internal TSD Channel | External TSD | |
---|---|---|
Pin | Device and Package Support | |
CH0 |
TEMPDIODEp[0] TEMPDIODEn[0] |
All Intel® Stratix® 10 devices and packages. |
CH1 |
TEMPDIODEp[1] TEMPDIODEn[1] |
All Intel® Stratix® 10 devices and packages. |
CH2 |
TEMPDIODEp[2] TEMPDIODEn[2] |
Support of these external TSDs depends on availability of the transceiver tile. However, regardless of transceiver tile availability, these external TSDs are not supported in the NF43, UF50, and HF55 packages of the following devices:
For the listed devices, use the Temperature Sensor IP core to read the internal TSD channels. |
CH3 |
TEMPDIODEp[3] TEMPDIODEn[3] |
|
CH4 |
TEMPDIODEp[4] TEMPDIODEn[4] |
|
CH5 |
TEMPDIODEp[5] TEMPDIODEn[5] |
|
CH6 |
TEMPDIODEp[6] TEMPDIODEn[6] |
|
CH7 | — | The high-bandwidth DRAM memory (HBM2) stacks do not feature external TSDs. Use the internal TSD channels. |
CH8 | — |
2.2.4. Temperature Sensor Error Codes
Error Code | Invalid Condition | Solution |
---|---|---|
0x80000000 | Selected temperature sensor channel is currently inactive. | Ensure that the tile where the TSD is located is actively in use. |
0x80000001 | Selected temperature sensor channel returned a value that is not the latest reading. | Retrieve the temperature reading again |
0x80000002 | Selected temperature sensor channel is invalid for the device. | Ignore the returned data because the temperature sensor channel location is invalid |
0x80000003 | System is corrupted or failed to respond | Contact Intel FPGA support |
0x80000004 | ||
0x80000005 | Communication mechanism is busy | Retrieve the temperature reading again |
0x800000FF | System is corrupted or failed to respond | Contact Intel FPGA support |
3. Intel Stratix 10 ADC Design Considerations
3.1. Guidelines: Selecting Temperature Sensing Chip to Interface with the Intel Stratix 10 External TSD
To interface with the Intel® Stratix® 10 external TSD, use a temperature sensing chip that supports features such as:
- Configurable ideality factor
- Offset adjustment with or without Beta compensation
These features allow you to perform calibration and measurement compensation to achieve a better accuracy on the temperature sensing chip.
3.2. Guidelines: Using External Temperature Sensors
Intel recommends that you sample the temperature when the device is inactive or use the internal temperature sensor with the internal TSD.
You can use both internal and external temperature sensors simultaneously.
Board Connection Guidelines for the Traces to the External TSD Pins
- Keep the trace lengths to the TEMPDIODEP or TEMPDIODEN pins less than eight inches.
- Route both traces in parallel and place them close to each other with grounded guard tracks on each side.
- Intel recommends a 10-mils width and space for both traces.
- Route both traces through the most minimum number of vias and crossunders possible to minimize the thermocouple effects.
- Ensure that the number of vias for both traces are the same.
- Ensure that both traces are approximately the same length.
- To avoid coupling, insert a GND plane between the external TSD pins traces and high-frequency toggling signals, such as clocks and I/O signals.
- To filter high-frequency noise, place an external capacitor between the traces close to the external temperature sensing chip. For more details, refer to the third-party temperature sensing chip manufacturer design guidelines.
- If you use only the internal TSD, you can leave the TEMPDIODEP and TEMPDIODEN pins unconnected.
For details about device specifications and connection guidelines, refer to the external temperature sensor manufacturer's datasheet.
3.3. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel Stratix 10 External TSD
The calibration of the external temperature sensing chip identifies optimized settings such as the temperature offset and change in ideality factor. The external chip uses these settings to accurately sample the temperature from the Intel® Stratix® 10 external TSD.
4. Intel Stratix 10 ADC Implementation Guides
- To sample external or internal voltages, use the Voltage Sensor Intel® FPGA IP.
- To sample the on-die temperature using the internal TSDs, use the Temperature Sensor Intel® FPGA IP.
The Voltage Sensor or Temperature Sensor IP core does not have configurable options in the Intel® Quartus® Prime parameter editor. To use the IP core, instantiate an instance of it in your design and use the digital signal interface of the IP core to access the voltage or temperature readouts.
The command and response interfaces of the Voltage Sensor and Temperature Sensor IP cores are Avalon® Streaming (Avalon-ST) interfaces with ready latency of 0.
4.1. Sampling the Intel Stratix 10 Voltage Sensor Channels
-
During device initialization, before the device enters user
mode:
- Assert the reset port of the Voltage Sensor IP core to keep it in reset mode.
- Keep the cmd_valid and cmd_data signal at "0".
-
After the device enters user mode, simultaneously assert a
logic high to the cmd_valid signal and send the
cmd_data value. For each sampling, assert
cmd_valid for a period of only one to three
clock cycles. When you are not acquiring the voltage sensor readout, deassert
cmd_valid.
The cmd_data signal is a 16-bit bitmask that specifies from which channel to sample the voltage. The SDM samples the voltages approximately every 1 ms 1.When you assert cmd_valid while cmd_ready is high, the IP core requests from the SDM the most recent voltage values of the channels you specify in cmd_data. After sending the request, the IP core drives cmd_ready low and waits for response from the SDM.
-
Each time the rsp_valid signal
goes high, indicating that the voltage value is ready, read the rsp_data and rsp_channel response signals.
The rsp_valid signal goes high once for each bit in the cmd_data word. The first valid data in the cycle is available when rsp_valid asserts while the rsp_startofpacket signal is high. The last valid data in the cycle is available when rsp_valid asserts while the rsp_endofpacket signal is high. In each valid response, the rsp_data signal provides the voltage value while the rsp_channel signal indicates from which channel the voltage was sampled.
4.2. Reading the Intel Stratix 10 Internal Temperature Sensing Diodes
-
During device initialization,
before the device
enters user mode:
- Assert the reset port of the Temperature Sensor IP core to keep it in reset mode.
- Keep the cmd_valid and cmd_data signal at "0".
-
After the device enters user mode, simultaneously assert a logic high
to the cmd_valid signal and send the cmd_data value. For each sampling, assert cmd_valid for a period of only one to three clock cycles. When
you are not acquiring the temperature sensor readout, deassert cmd_valid.
The cmd_data signal is a 9-bit bitmask that specifies from which channel to sample the temperature.When you assert cmd_valid while cmd_ready is high, the IP core requests from the SDM the most recent temperature values of the channels you specify in cmd_data. After sending the request, the IP core drives cmd_ready low and waits for response from the SDM.
-
Each time the rsp_valid signal goes
high, indicating that the temperature value is ready, read the rsp_data and rsp_channel response
signals.
The rsp_valid signal goes high once for each bit in the cmd_data word. The first valid data in the cycle is available when rsp_valid asserts while the rsp_startofpacket signal is high. The last valid data in the cycle is available when rsp_valid asserts while the rsp_endofpacket signal is high. For each valid response, the rsp_data signal provides the temperature value while the rsp_channel signal indicates from which channel the temperature was sampled.
5. Intel Stratix 10 ADC IP Core References
5.1. Voltage Sensor Intel FPGA IP Digital Signals
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
clk | 1 | Input | All signals in the IP core is synchronous to this clock. The frequency supported for this clock is from 10 MHz to 100 MHz. |
reset | 1 | Input | Active high reset. Deassert this signal synchronous to the clock. |
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
cmd_valid | 1 |
Input |
Assert this signal high to send voltage sampling request to the IP core. |
cmd_ready | 1 |
Output |
The IP core drives this signal high to indicate that the IP core is ready to receive command. |
cmd_data | 16 |
Input |
Bitmask to indicate from which channel to return the voltage value. Send this data signal together with the cmd_valid signal.
For example, 0000001000010001 signals the IP core to sample the voltage values from channels 0, 4, and 9. Set only valid bits in the cmd_data word. Otherwise, the response from the voltage sensor is undefined. |
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
rsp_valid | 1 |
Output |
Indication from the IP core that the voltage value is ready. |
rsp_channel | 4 |
Output |
Indicates the channel of the voltage value sampled from the analog inputs or internal supplies. |
rsp_data | 32 |
Output |
The voltage value in a signed 32-bit fixed-point binary format, with 16 bits below the binary point. |
rsp_startofpacket | 1 |
Output |
Indicates that the current transfer is the start of packet. |
rsp_endofpacket | 1 | Output | Indicates that the current transfer is the end of packet. |
5.2. Temperature Sensor Intel FPGA IP Digital Signals
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
clk | 1 | Input | All signals in the IP core is synchronous to this clock. The frequency supported for this clock is from 10 MHz to 100 MHz. |
reset | 1 | Input | Active high reset. Deassert this signal synchronous to the clock. |
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
cmd_valid | 1 |
Input |
Assert this signal high to send temperature sampling request to the IP core. |
cmd_ready | 1 |
Output |
The IP core drives this signal high to indicate that the IP core is ready to receive command. |
cmd_data | 9 |
Input |
Bitmask to indicate from which channel to return the temperature. Send this data signal together with the cmd_valid signal.
For example, 0000101 signals the IP core to sample the temperature values from channel 0 (core fabric) and channel 2 (bank 6B). For the designated temperature sensor channel number of each transceiver tile and HBM2 stacks, refer to the related information. Set only valid bits in the cmd_data word. Otherwise, the response from the temperature sensor is undefined. Note: The availability of the internal TSD channels varies among
Intel®
Stratix® 10 devices and packages.
|
Signal |
Width (Bit) |
Type | Description |
---|---|---|---|
rsp_valid | 1 |
Output |
Indication from the IP core that the temperature value is ready. |
rsp_channel | 4 |
Output |
Indicates the channel of the temperature value sampled from the core fabric or transceiver tile. |
rsp_data | 32 |
Output |
The temperature value in a signed 32-bit fixed-point binary format, with 8 bits below the binary point. A value of 0x80000000 indicates invalid data. |
rsp_startofpacket | 1 |
Output |
Indicates that the current transfer is the start of packet. |
rsp_endofpacket | 1 | Output | Indicates that the current transfer is the end of packet. |
6. Intel Stratix 10 Analog to Digital Converter User Guide Archives
Intel® Quartus® Prime Version | User Guide |
---|---|
20.3 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
19.3 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
19.2 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
19.1 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
18.1 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
18.0 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
17.1 | Intel® Stratix® 10 Analog to Digital Converter User Guide |
7. Document Revision History for the Intel Stratix 10 Analog to Digital Converter User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2021.02.09 | 20.4 | Updated the description for temperature sensor error codes 0x80000001 and 0x80000005. |
2020.10.19 | 20.3 |
|
2019.10.09 | 19.3 |
|
2019.07.09 | 19.2 |
|
2019.05.17 | 19.1 | Added a note regarding IP core instantiation guidelines in the topics about sampling the voltage sensor and reading the internal temperature sensor. |
2019.05.13 | 19.1 |
|
2018.11.05 | 18.1 |
|
2018.07.19 | 18.0 |
|
2018.05.07 | 18.0 |
|
Date | Version | Changes |
---|---|---|
November 2017 | 2017.11.06 |
|
May 2017 | 2017.05.08 |
|
February 2017 | 2017.02.13 |
|
December 2016 | 2016.12.05 | Updated the tables listing the clock and reset signals for the Voltage Sensor and Temperature Sensor IP cores. |
October 2016 | 2016.10.31 | Initial release. |