Arria V Device Datasheet
Arria V GX, GT, SX, and ST Device Datasheet
Arria® V devices are offered in commercial and industrial grades. Commercial devices are offered in –C4 (fastest), –C5, and –C6 speed grades. Industrial grade devices are offered in the –I3 and –I5 speed grades.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Arria® V devices.
Operating Conditions
Arria® V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria® V devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Arria® V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms.
The functional operation of the device is not implied for these conditions.
Symbol | Description | Minimum | Maximum | Unit |
---|---|---|---|---|
VCC | Core voltage power supply | –0.50 | 1.43 | V |
VCCP | Periphery circuitry, PCI Express* ( PCIe* ) hard IP block, and transceiver physical coding sublayer (PCS) power supply | –0.50 | 1.43 | V |
VCCPGM | Configuration pins power supply | –0.50 | 3.90 | V |
VCC_AUX | Auxiliary supply | –0.50 | 3.25 | V |
VCCBAT | Battery back-up power supply for design security volatile key register | –0.50 | 3.90 | V |
VCCPD | I/O pre-driver power supply | –0.50 | 3.90 | V |
VCCIO | I/O power supply | –0.50 | 3.90 | V |
VCCD_FPLL | Phase-locked loop (PLL) digital power supply | –0.50 | 1.80 | V |
VCCA_FPLL | PLL analog power supply | –0.50 | 3.25 | V |
VCCA_GXB | Transceiver high voltage power | –0.50 | 3.25 | V |
VCCH_GXB | Transmitter output buffer power | –0.50 | 1.80 | V |
VCCR_GXB | Receiver power | –0.50 | 1.50 | V |
VCCT_GXB | Transmitter power | –0.50 | 1.50 | V |
VCCL_GXB | Transceiver clock network power | –0.50 | 1.50 | V |
VI | DC input voltage | –0.50 | 3.80 | V |
VCC_HPS | HPS core voltage and periphery circuitry power supply | –0.50 | 1.43 | V |
VCCPD_HPS | HPS I/O pre-driver power supply | –0.50 | 3.90 | V |
VCCIO_HPS | HPS I/O power supply | –0.50 | 3.90 | V |
VCCRSTCLK_HPS | HPS reset and clock input pins power supply | –0.50 | 3.90 | V |
VCCPLL_HPS | HPS PLL analog power supply | –0.50 | 3.25 | V |
VCC_AUX_SHARED | HPS auxiliary power supply | –0.50 | 3.25 | V |
IOUT | DC output current per pin | –25 | 40 | mA |
TJ | Operating junction temperature | –55 | 125 | °C |
TSTG | Storage temperature (no bias) | –65 | 150 | °C |
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years.
Symbol | Description | Condition (V) | Overshoot Duration as % of High Time | Unit |
---|---|---|---|---|
Vi (AC) | AC input voltage | 3.8 | 100 | % |
3.85 | 68 | % | ||
3.9 | 45 | % | ||
3.95 | 28 | % | ||
4 | 15 | % | ||
4.05 | 13 | % | ||
4.1 | 11 | % | ||
4.15 | 9 | % | ||
4.2 | 8 | % | ||
4.25 | 7 | % | ||
4.3 | 5.4 | % | ||
4.35 | 3.2 | % | ||
4.4 | 1.9 | % | ||
4.45 | 1.1 | % | ||
4.5 | 0.6 | % | ||
4.55 | 0.4 | % | ||
4.6 | 0.2 | % |
For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Arria® V devices.
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 1 | Typical | Maximum1 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | –C4, –I5, –C5, –C6 | 1.07 | 1.1 | 1.13 | V |
–I3 | 1.12 | 1.15 | 1.18 | V | ||
VCCP | Periphery circuitry, PCIe* hard IP block, and transceiver PCS power supply | –C4, –I5, –C5, –C6 | 1.07 | 1.1 | 1.13 | V |
–I3 | 1.12 | 1.15 | 1.18 | V | ||
VCCPGM | Configuration pins power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
VCC_AUX | Auxiliary supply | — | 2.375 | 2.5 | 2.625 | V |
VCCBAT 2 |
Battery back-up power supply (For design security volatile key register) |
— | 1.2 | — | 3.0 | V |
VCCPD 3 | I/O pre-driver power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
VCCIO | I/O buffers power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 1.283 | 1.35 | 1.418 | V | ||
1.25 V | 1.19 | 1.25 | 1.31 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCD_FPLL | PLL digital voltage regulator power supply | — | 1.425 | 1.5 | 1.575 | V |
VCCA_FPLL | PLL analog voltage regulator power supply | — | 2.375 | 2.5 | 2.625 | V |
VI | DC input voltage | — | –0.5 | — | 3.6 | V |
VO | Output voltage | — | 0 | — | VCCIO | V |
TJ | Operating junction temperature | Commercial | 0 | — | 85 | °C |
Industrial | –40 | — | 100 | °C | ||
tRAMP 4 | Power supply ramp time | Standard POR | 200 µs | — | 100 ms | — |
Fast POR | 200 µs | — | 4 ms | — |
Transceiver Power Supply Operating Conditions
Symbol | Description | Minimum 5 | Typical | Maximum5 | Unit |
---|---|---|---|---|---|
VCCA_GXBL | Transceiver high voltage power (left side) | 2.375 | 2.500 | 2.625 | V |
VCCA_GXBR | Transceiver high voltage power (right side) | ||||
VCCR_GXBL | GX and SX speed grades—receiver power (left side) | 1.08/1.12 | 1.1/1.15 6 | 1.14/1.18 | V |
VCCR_GXBR | GX and SX speed grades—receiver power (right side) | ||||
VCCR_GXBL | GT and ST speed grades—receiver power (left side) | 1.17 | 1.20 | 1.23 | V |
VCCR_GXBR | GT and ST speed grades—receiver power (right side) | ||||
VCCT_GXBL | GX and SX speed grades—transmitter power (left side) | 1.08/1.12 | 1.1/1.156 | 1.14/1.18 | V |
VCCT_GXBR | GX and SX speed grades—transmitter power (right side) | ||||
VCCT_GXBL | GT and ST speed grades—transmitter power (left side) | 1.17 | 1.20 | 1.23 | V |
VCCT_GXBR | GT and ST speed grades—transmitter power (right side) | ||||
VCCH_GXBL | Transmitter output buffer power (left side) | 1.425 | 1.500 | 1.575 | V |
VCCH_GXBR | Transmitter output buffer power (right side) | ||||
VCCL_GXBL | GX and SX speed grades—clock network power (left side) | 1.08/1.12 | 1.1/1.156 | 1.14/1.18 | V |
VCCL_GXBR | GX and SX speed grades—clock network power (right side) | ||||
VCCL_GXBL | GT and ST speed grades—clock network power (left side) | 1.17 | 1.20 | 1.23 | V |
VCCL_GXBR | GT and ST speed grades—clock network power (right side) |
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum 7 | Typical | Maximum7 | Unit |
---|---|---|---|---|---|---|
VCC_HPS | HPS core voltage and periphery circuitry power supply | –C4, –I5, –C5, –C6 | 1.07 | 1.1 | 1.13 | V |
–I3 | 1.12 | 1.15 | 1.18 | V | ||
VCCPD_HPS 8 | HPS I/O pre-driver power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
VCCIO_HPS | HPS I/O buffers power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V 9 | 1.283 | 1.35 | 1.418 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCRSTCLK_HPS | HPS reset and clock input pins power supply | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3.0 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
VCCPLL_HPS | HPS PLL analog voltage regulator power supply | — | 2.375 | 2.5 | 2.625 | V |
VCC_AUX_SHARED | HPS auxiliary power supply | — | 2.375 | 2.5 | 2.625 | V |
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates.
I/O Pin Leakage Current
Symbol | Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
II | Input pin | VI = 0 V to VCCIOMAX | –30 | — | 30 | µA |
IOZ | Tri-stated I/O pin | VO = 0 V to VCCIOMAX | –30 | — | 30 | µA |
Bus Hold Specifications
Parameter | Symbol | Condition | VCCIO (V) | Unit | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.2 | 1.5 | 1.8 | 2.5 | 3.0 | 3.3 | ||||||||||
Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | ||||
Bus-hold, low, sustaining current | ISUSL |
VIN > VIL (max) |
8 | — | 12 | — | 30 | — | 50 | — | 70 | — | 70 | — | µA |
Bus-hold, high, sustaining current | ISUSH |
VIN < VIH (min) |
–8 | — | –12 | — | –30 | — | –50 | — | –70 | — | –70 | — | µA |
Bus-hold, low, overdrive current | IODL | 0 V < VIN < VCCIO | — | 125 | — | 175 | — | 200 | — | 300 | — | 500 | — | 500 | µA |
Bus-hold, high, overdrive current | IODH | 0 V <VIN <VCCIO | — | –125 | — | –175 | — | –200 | — | –300 | — | –500 | — | –500 | µA |
Bus-hold trip point | VTRIP | — | 0.3 | 0.9 | 0.375 | 1.125 | 0.68 | 1.07 | 0.7 | 1.7 | 0.8 | 2 | 0.8 | 2 | V |
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.
Symbol | Description | Condition (V) | Calibration Accuracy | Unit | ||
---|---|---|---|---|---|---|
–I3, –C4 | –I5, –C5 | –C6 | ||||
25-Ω RS | Internal series termination with calibration (25-Ω setting) | VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 | ±15 | ±15 | ±15 | % |
50-Ω RS | Internal series termination with calibration (50-Ω setting) | VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 | ±15 | ±15 | ±15 | % |
34-Ω and 40-Ω RS | Internal series termination with calibration (34-Ω and 40-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | ±15 | ±15 | ±15 | % |
48-Ω, 60-Ω, and 80-Ω RS | Internal series termination with calibration (48-Ω, 60-Ω, and 80-Ω setting) | VCCIO = 1.2 | ±15 | ±15 | ±15 | % |
50-Ω RT | Internal parallel termination with calibration (50-Ω setting) | VCCIO = 2.5, 1.8, 1.5, 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
20-Ω, 30-Ω, 40-Ω,60-Ω, and 120-Ω RT | Internal parallel termination with calibration (20-Ω, 30-Ω, 40-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.5, 1.35, 1.25 | –10 to +40 | –10 to +40 | –10 to +40 | % |
60-Ω and 120-Ω RT | Internal parallel termination with calibration (60-Ω and 120-Ω setting) | VCCIO = 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
25-Ω RS_left_shift | Internal left shift series termination with calibration (25-Ω RS_left_shift setting) | VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 | ±15 | ±15 | ±15 | % |
OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | Condition (V) | Resistance Tolerance | Unit | ||
---|---|---|---|---|---|---|
–I3, –C4 | –I5, –C5 | –C6 | ||||
25-Ω RS | Internal series termination without calibration (25-Ω setting) | VCCIO = 3.0, 2.5 | ±30 | ±40 | ±40 | % |
25-Ω RS | Internal series termination without calibration (25-Ω setting) | VCCIO = 1.8, 1.5 | ±30 | ±40 | ±40 | % |
25-Ω RS | Internal series termination without calibration (25-Ω setting) | VCCIO = 1.2 | ±35 | ±50 | ±50 | % |
50-Ω RS | Internal series termination without calibration (50-Ω setting) | VCCIO = 3.0, 2.5 | ±30 | ±40 | ±40 | % |
50-Ω RS | Internal series termination without calibration (50-Ω setting) | VCCIO = 1.8, 1.5 | ±30 | ±40 | ±40 | % |
50-Ω RS | Internal series termination without calibration (50-Ω setting) | VCCIO = 1.2 | ±35 | ±50 | ±50 | % |
100-Ω RD | Internal differential termination (100-Ω setting) | VCCIO = 2.5 | ±25 | ±40 | ±40 | % |
The definitions for the equation are as follows:
- The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
- RSCAL is the OCT resistance value at power-up.
- ΔT is the variation of temperature with respect to the temperature at power up.
- ΔV is the variation of voltage with respect to the VCCIO at power up.
- dR/dT is the percentage change of RSCAL with temperature.
- dR/dV is the percentage change of RSCAL with voltage.
OCT Variation after Power-Up Calibration
Symbol | Description | VCCIO (V) | Value | Unit |
---|---|---|---|---|
dR/dV | OCT variation with voltage without recalibration | 3.0 | 0.100 | %/mV |
2.5 | 0.100 | |||
1.8 | 0.100 | |||
1.5 | 0.100 | |||
1.35 | 0.150 | |||
1.25 | 0.150 | |||
1.2 | 0.150 | |||
dR/dT | OCT variation with temperature without recalibration | 3.0 | 0.189 | %/°C |
2.5 | 0.208 | |||
1.8 | 0.266 | |||
1.5 | 0.273 | |||
1.35 | 0.200 | |||
1.25 | 0.200 | |||
1.2 | 0.317 |
Pin Capacitance
Symbol | Description | Maximum | Unit |
---|---|---|---|
CIOTB | Input capacitance on top/bottom I/O pins | 6 | pF |
CIOLR | Input capacitance on left/right I/O pins | 6 | pF |
COUTFB | Input capacitance on dual-purpose clock output/feedback pins | 6 | pF |
CIOVREF | Input capacitance on VREF pins | 48 | pF |
Hot Socketing
Symbol | Description | Maximum | Unit |
---|---|---|---|
IIOPIN (DC) | DC current per I/O pin | 300 | μA |
IIOPIN (AC) | AC current per I/O pin | 810 | mA |
IXCVR-TX (DC) | DC current per transceiver transmitter (TX) pin | 100 | mA |
IXCVR-RX (DC) | DC current per transceiver receiver (RX) pin | 50 | mA |
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
Symbol | Description | Condition (V)11 | Value12 | Unit |
---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO = 3.3 ±5% | 25 | kΩ |
VCCIO = 3.0 ±5% | 25 | kΩ | ||
VCCIO = 2.5 ±5% | 25 | kΩ | ||
VCCIO = 1.8 ±5% | 25 | kΩ | ||
VCCIO = 1.5 ±5% | 25 | kΩ | ||
VCCIO = 1.35 ±5% | 25 | kΩ | ||
VCCIO = 1.25 ±5% | 25 | kΩ | ||
VCCIO = 1.2 ±5% | 25 | kΩ |
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Arria® V devices.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards
I/O Standard | VCCIO (V) | VIL (V) | VIH (V) | VOL (V) | VOH (V) | IOL 13 (mA) | IOH 13 (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Max | Min | |||
3.3-V LVTTL | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 1.7 | 3.6 | 0.45 | 2.4 | 4 | –4 |
3.3-V LVCMOS | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 1.7 | 3.6 | 0.2 | VCCIO – 0.2 | 2 | –2 |
3.0-V LVTTL | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.4 | 2.4 | 2 | –2 |
3.0-V LVCMOS | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.2 | VCCIO – 0.2 | 0.1 | –0.1 |
3.0-V PCI* | 2.85 | 3 | 3.15 | — | 0.3 × VCCIO | 0.5 × VCCIO | VCCIO + 0.3 | 0.1 × VCCIO | 0.9 × VCCIO | 1.5 | –0.5 |
3.0-V PCI* -X | 2.85 | 3 | 3.15 | — | 0.35 × VCCIO | 0.5 × VCCIO | VCCIO + 0.3 | 0.1 × VCCIO | 0.9 × VCCIO | 1.5 | –0.5 |
2.5 V | 2.375 | 2.5 | 2.625 | –0.3 | 0.7 | 1.7 | 3.6 | 0.4 | 2 | 1 | –1 |
1.8 V | 1.71 | 1.8 | 1.89 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.45 | VCCIO – 0.45 | 2 | –2 |
1.5 V | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.2 V | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
I/O Standard | VCCIO (V) | VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-2 Class I, II | 2.375 | 2.5 | 2.625 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | VREF – 0.04 | VREF | VREF + 0.04 |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.833 | 0.9 | 0.969 | VREF – 0.04 | VREF | VREF + 0.04 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-135 Class I, II | 1.283 | 1.35 | 1.418 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-125 Class I, II | 1.19 | 1.25 | 1.26 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.85 | 0.9 | 0.95 | — | VCCIO/2 | — |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.68 | 0.75 | 0.9 | — | VCCIO/2 | — |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO | 0.5 × VCCIO | 0.53 × VCCIO | — | VCCIO/2 | — |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | — | — | — |
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) | VOL (V) | VOH (V) | IOL 14 (mA) | IOH 14 (mA) | ||
---|---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Max | Min | Max | Min | |||
SSTL-2 Class I | –0.3 | VREF – 0.15 | VREF + 0.15 | VCCIO + 0.3 | VREF – 0.31 | VREF + 0.31 | VTT – 0.608 | VTT + 0.608 | 8.1 | –8.1 |
SSTL-2 Class II | –0.3 | VREF – 0.15 | VREF + 0.15 | VCCIO + 0.3 | VREF – 0.31 | VREF + 0.31 | VTT – 0.81 | VTT + 0.81 | 16.2 | –16.2 |
SSTL-18 Class I | –0.3 | VREF – 0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | VTT – 0.603 | VTT + 0.603 | 6.7 | –6.7 |
SSTL-18 Class II | –0.3 | VREF – 0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | 0.28 | VCCIO – 0.28 | 13.4 | –13.4 |
SSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 8 | –8 |
SSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 16 | –16 |
SSTL-135 | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.16 | VREF + 0.16 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-125 | — | VREF – 0.85 | VREF + 0.85 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
HSTL-18 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-18 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-12 Class I | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 8 | –8 |
HSTL-12 Class II | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO+ 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 16 | –16 |
HSUL-12 | — | VREF – 0.13 | VREF + 0.13 | — | VREF – 0.22 | VREF + 0.22 | 0.1 × VCCIO | 0.9 × VCCIO | — | — |
Differential SSTL I/O Standards
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VX(AC) (V) | VSWING(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Max | |
SSTL-2 Class I, II | 2.375 | 2.5 | 2.625 | 0.3 | VCCIO + 0.6 | VCCIO/2 – 0.2 | — | VCCIO/2 + 0.2 | 0.62 | VCCIO + 0.6 |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | VCCIO/2 – 0.175 | — | VCCIO/2 + 0.175 | 0.5 | VCCIO + 0.6 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 15 | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.18 | 15 | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) |
SSTL-125 | 1.19 | 1.25 | 1.31 | 0.18 | 15 | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) |
Differential HSTL and HSUL I/O Standards
I/O Standard | VCCIO (V) | VDIF(DC) (V) | VX(AC) (V) | VCM(DC) (V) | VDIF(AC) (V) | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Max | |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.2 | — | 0.78 | — | 1.12 | 0.78 | — | 1.12 | 0.4 | — |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | 0.68 | — | 0.9 | 0.68 | — | 0.9 | 0.4 | — |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | VCCIO + 0.3 | — | 0.5 × VCCIO | — | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO | 0.3 | VCCIO + 0.48 |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.26 | 0.26 | 0.5 × VCCIO – 0.12 | 0.5 × VCCIO | 0.5 × VCCIO + 0.12 | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO | 0.44 | 0.44 |
Differential I/O Standard Specifications
I/O Standard | VCCIO (V) | VID (mV)16 | VICM(DC) (V) | VOD (V) 17 | VOCM (V)17 18 | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Condition | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
PCML | Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Transceiver Specifications for Arria® V GX and SX Devices and Transceiver Specifications for Arria® V GT and ST Devices tables. | ||||||||||||||
2.5 V LVDS19 | 2.375 | 2.5 | 2.625 | 100 | VCM = 1.25 V | — | 0.05 | DMAX ≤ 1.25 Gbps | 1.80 | 0.247 | — | 0.6 | 1.125 | 1.25 | 1.375 |
— | 1.05 | DMAX > 1.25 Gbps | 1.55 | ||||||||||||
RSDS (HIO)20 | 2.375 | 2.5 | 2.625 | 100 | VCM = 1.25 V | — | 0.25 | — | 1.45 | 0.1 | 0.2 | 0.6 | 0.5 | 1.2 | 1.4 |
Mini-LVDS (HIO)21 | 2.375 | 2.5 | 2.625 | 200 | — | 600 | 0.300 | — | 1.425 | 0.25 | — | 0.6 | 1 | 1.2 | 1.4 |
LVPECL22 | — | — | — | 300 | — | — | 0.60 | DMAX ≤ 700 Mbps | 1.80 | — | — | — | — | — | — |
1.00 | DMAX > 700 Mbps | 1.60 |
Switching Characteristics
This section provides performance characteristics of Arria® V core and periphery blocks.
Transceiver Performance Specifications
Transceiver Specifications for Arria V GX and SX Devices
Symbol/Description | Condition | Transceiver Speed Grade 4 | Transceiver Speed Grade 6 | Unit | ||||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | |||
Supported I/O standards | 1.2 V PCML, 1.4 V PCML,1.5 V PCML, 2.5 V PCML, Differential LVPECL23, HCSL, and LVDS | |||||||
Input frequency from REFCLK input pins | — | 27 | — | 710 | 27 | — | 710 | MHz |
Rise time | Measure at ±60 mV of differential signal 24 | — | — | 400 | — | — | 400 | ps |
Fall time | Measure at ±60 mV of differential signal24 | — | — | 400 | — | — | 400 | ps |
Duty cycle | — | 45 | — | 55 | 45 | — | 55 | % |
Peak-to-peak differential input voltage | — | 200 | — | 300 25/2000 | 200 | — | 30025/2000 | mV |
Spread-spectrum modulating clock frequency | PCIe* | 30 | — | 33 | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe* | — | 0 to –0.5% | — | — | 0 to –0.5% | — | — |
On-chip termination resistors | — | — | 100 | — | — | 100 | — | Ω |
VICM (AC coupled) | — | — | 1.1/1.15 26 | — | — | 1.1/1.1526 | — | V |
VICM (DC coupled) | HCSL I/O standard for the PCIe* reference clock | 250 | — | 550 | 250 | — | 550 | mV |
Transmitter REFCLK phase noise27 | 10 Hz | — | — | –50 | — | — | –50 | dBc/Hz |
100 Hz | — | — | –80 | — | — | –80 | dBc/Hz | |
1 KHz | — | — | –110 | — | — | –110 | dBc/Hz | |
10 KHz | — | — | –120 | — | — | –120 | dBc/Hz | |
100 KHz | — | — | –120 | — | — | –120 | dBc/Hz | |
≥1 MHz | — | — | –130 | — | — | –130 | dBc/Hz | |
RREF | — | — | 2000 ±1% | — | — | 2000 ±1% | — | Ω |
Symbol/Description | Condition | Transceiver Speed Grade 4 | Transceiver Speed Grade 6 | Unit | ||||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | |||
fixedclk clock frequency | PCIe* Receiver Detect | — | 125 | — | — | 125 | — | MHz |
Transceiver Reconfiguration Controller Intel® FPGA IP (mgmt_clk_clk) clock frequency | — | 75 | — | 125 | 75 | — | 125 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 4 | Transceiver Speed Grade 6 | Unit | ||||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | |||
Supported I/O standards | 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS | |||||||
Data rate28 | — | 611 | — | 6553.6 | 611 | — | 3125 | Mbps |
Absolute VMAX for a receiver pin29 | — | — | — | 1.2 | — | — | 1.2 | V |
Absolute VMIN for a receiver pin | — | –0.4 | — | — | –0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration | — | — | — | 1.6 | — | — | 1.6 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration | — | — | — | 2.2 | — | — | 2.2 | V |
Minimum differential eye opening at the receiver serial input pins30 | — | 100 | — | — | 100 | — | — | mV |
VICM (AC coupled) | — | — | 0.7/0.75/0.8 31 | — | — | 0.7/0.75/0.8 31 | — | mV |
VICM (DC coupled) | ≤ 3.2Gbps 32 | 670 | 700 | 730 | 670 | 700 | 730 | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 | — | — | 85 | — | Ω |
100-Ω setting | — | 100 | — | — | 100 | — | Ω | |
120-Ω setting | — | 120 | — | — | 120 | — | Ω | |
150-Ω setting | — | 150 | — | — | 150 | — | Ω | |
tLTR 33 | — | — | — | 10 | — | — | 10 | µs |
tLTD 34 | — | 4 | — | — | 4 | — | — | µs |
tLTD_manual 35 | — | 4 | — | — | 4 | — | — | µs |
tLTR_LTD_manual 36 | — | 15 | — | — | 15 | — | — | µs |
Programmable ppm detector37 | — | ±62.5, 100, 125, 200, 250, 300, 500, and 1000 | ppm | |||||
Run length | — | — | — | 200 | — | — | 200 | UI |
Programmable equalization AC and DC gain |
AC gain setting = 0 to 338 DC gain setting = 0 to 1 |
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices diagrams. | dB |
Symbol/Description | Condition | Transceiver Speed Grade 4 | Transceiver Speed Grade 6 | Unit | ||||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | |||
Supported I/O standards | 1.5 V PCML | |||||||
Data rate | — | 611 | — | 6553.6 | 611 | — | 3125 | Mbps |
VOCM (AC coupled) | — | — | 650 | — | — | 650 | — | mV |
VOCM (DC coupled) | ≤ 3.2Gbps32 | 670 | 700 | 730 | 670 | 700 | 730 | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 | — | — | 85 | — | Ω |
100-Ω setting | — | 100 | — | — | 100 | — | Ω | |
120-Ω setting | — | 120 | — | — | 120 | — | Ω | |
150-Ω setting | — | 150 | — | — | 150 | — | Ω | |
Intra-differential pair skew | TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps | — | — | 15 | — | — | 15 | ps |
Intra-transceiver block transmitter channel-to-channel skew | ×6 PMA bonded mode | — | — | 180 | — | — | 180 | ps |
Inter-transceiver block transmitter channel-to-channel skew39 | ×N PMA bonded mode | — | — | 500 | — | — | 500 | ps |
Symbol/Description | Transceiver Speed Grade 4 | Transceiver Speed Grade 6 | Unit | ||
---|---|---|---|---|---|
Min | Max | Min | Max | ||
Supported data range | 611 | 6553.6 | 611 | 3125 | Mbps |
fPLL supported data range | 611 | 3125 | 611 | 3125 | Mbps |
Symbol/Description | Transceiver Speed Grade 4 and 6 | Unit | |
---|---|---|---|
Min | Max | ||
Interface speed (single-width mode) | 25 | 187.5 | MHz |
Interface speed (double-width mode) | 25 | 163.84 | MHz |
Transceiver Specifications for Arria V GT and ST Devices
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O standards | 1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL40, HCSL, and LVDS | ||||
Input frequency from REFCLK input pins | — | 27 | — | 710 | MHz |
Rise time | Measure at ±60 mV of differential signal 41 | — | — | 400 | ps |
Fall time | Measure at ±60 mV of differential signal41 | — | — | 400 | ps |
Duty cycle | — | 45 | — | 55 | % |
Peak-to-peak differential input voltage | — | 200 | — | 30042/2000 | mV |
Spread-spectrum modulating clock frequency | PCIe* | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe* | — | 0 to –0.5% | — | — |
On-chip termination resistors | — | — | 100 | — | Ω |
VICM (AC coupled) | — | — | 1.2 | — | V |
VICM (DC coupled) | HCSL I/O standard for the PCIe* reference clock | 250 | — | 550 | mV |
Transmitter REFCLK phase noise43 | 10 Hz | — | — | –50 | dBc/Hz |
100 Hz | — | — | –80 | dBc/Hz | |
1 KHz | — | — | –110 | dBc/Hz | |
10 KHz | — | — | –120 | dBc/Hz | |
100 KHz | — | — | –120 | dBc/Hz | |
≥ 1 MHz | — | — | –130 | dBc/Hz | |
RREF | — | — | 2000 ±1% | — | Ω |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
fixedclk clock frequency | PCIe* Receiver Detect | — | 125 | — | MHz |
Transceiver Reconfiguration Controller Intel® FPGA IP (mgmt_clk_clk) clock frequency | — | 75 | — | 125 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS | ||||
Data rate (6-Gbps transceiver) 44 | — | 611 | — | 6553.6 | Mbps |
Data rate (10-Gbps transceiver)44 | — | 0.611 | — | 10.3125 | Gbps |
Absolute VMAX for a receiver pin45 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin | — | –0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration | — | — | — | 1.6 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration | — | — | — | 2.2 | V |
Minimum differential eye opening at the receiver serial input pins46 | — | 100 | — | — | mV |
VICM (AC coupled) | — | — | 75047/800 | — | mV |
VICM (DC coupled) | ≤ 3.2Gbps 48 | 670 | 700 | 730 | mV |
Differential on-chip termination resistors | 85-Ω setting | 85 | Ω | ||
100-Ω setting | 100 | Ω | |||
120-Ω setting | 120 | Ω | |||
150-Ω setting | 150 | Ω | |||
tLTR 49 | — | — | — | 10 | µs |
tLTD 50 | — | 4 | — | — | µs |
tLTD_manual 51 | — | 4 | — | — | µs |
tLTR_LTD_manual 52 | — | 15 | — | — | µs |
Programmable ppm detector53 | — | ±62.5, 100, 125, 200, 250, 300, 500, and 1000 | ppm | ||
Run length | — | — | — | 200 | UI |
Programmable equalization AC and DC gain |
AC gain setting = 0 to 354 DC gain setting = 0 to 1 |
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria® V GX, GT, SX, and ST Devices diagrams. |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O standards | 1.5 V PCML | ||||
Data rate (6-Gbps transceiver) | — | 611 | — | 6553.6 | Mbps |
Data rate (10-Gbps transceiver) | — | 0.611 | — | 10.3125 | Gbps |
VOCM (AC coupled) | — | — | 650 | — | mV |
VOCM (DC coupled) | ≤ 3.2 Gbps48 | 670 | 700 | 730 | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 | — | Ω |
100-Ω setting | — | 100 | — | Ω | |
120-Ω setting | — | 120 | — | Ω | |
150-Ω setting | — | 150 | — | Ω | |
Intra-differential pair skew | TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps | — | — | 15 | ps |
Intra-transceiver block transmitter channel-to-channel skew | ×6 PMA bonded mode | — | — | 180 | ps |
Inter-transceiver block transmitter channel-to-channel skew55 | ×N PMA bonded mode | — | — | 500 | ps |
Symbol/Description | Transceiver Speed Grade 3 | Unit | |
---|---|---|---|
Min | Max | ||
Supported data range | 0.611 | 10.3125 | Gbps |
fPLL supported data range | 611 | 3125 | Mbps |
Symbol/Description | Transceiver Speed Grade 3 | Unit | |
---|---|---|---|
Min | Max | ||
Interface speed (PMA direct mode) | 50 | 153.656, 16157 | MHz |
Interface speed (single-width mode) | 25 | 187.5 | MHz |
Interface speed (double-width mode) | 25 | 163.84 | MHz |
CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain

CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain
Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω
Symbol | VOD Setting 58 | VOD Value (mV) | VOD Setting58 | VOD Value (mV) |
---|---|---|---|---|
VOD differential peak-to-peak typical | 6 59 | 120 | 34 | 680 |
759 | 140 | 35 | 700 | |
859 | 160 | 36 | 720 | |
9 | 180 | 37 | 740 | |
10 | 200 | 38 | 760 | |
11 | 220 | 39 | 780 | |
12 | 240 | 40 | 800 | |
13 | 260 | 41 | 820 | |
14 | 280 | 42 | 840 | |
15 | 300 | 43 | 860 | |
16 | 320 | 44 | 880 | |
17 | 340 | 45 | 900 | |
18 | 360 | 46 | 920 | |
19 | 380 | 47 | 940 | |
20 | 400 | 48 | 960 | |
21 | 420 | 49 | 980 | |
22 | 440 | 50 | 1000 | |
23 | 460 | 51 | 1020 | |
24 | 480 | 52 | 1040 | |
25 | 500 | 53 | 1060 | |
26 | 520 | 54 | 1080 | |
27 | 540 | 55 | 1100 | |
28 | 560 | 56 | 1120 | |
29 | 580 | 57 | 1140 | |
30 | 600 | 58 | 1160 | |
31 | 620 | 59 | 1180 | |
32 | 640 | 60 | 1200 | |
33 | 660 |
Transmitter Pre-Emphasis Levels
The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions:
- Low-frequency data pattern—five 1s and five 0s
- Data rate—2.5 Gbps
The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre-emphasis levels may change with data pattern and data rate.
Arria® V devices only support 1st post tap pre-emphasis with the following conditions:
- The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st post tap pre-emphasis setting.
- |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
- (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
Exception for PCIe* Gen2 design: VOD setting = 43 and pre-emphasis setting = 19 are allowed for PCIe* Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Arria V Hard IP for PCI Express Intel® FPGA IP and PHY for PCI Express (PIPE) Intel® FPGA IP cores.
For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid:
- |B| + |C| ≤ 60→ 40 + 2 = 42
- |B| – |C| > 5→ 40 – 2 = 38
- (VMAX/VMIN – 1)% < 600%→ (42/38 – 1)% = 10.52%
To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Arria® V HSSI HSPICE models.
Intel® Quartus® Prime 1st Post Tap Pre-Emphasis Setting | Intel® Quartus® Prime VOD Setting | Unit | ||||||
---|---|---|---|---|---|---|---|---|
10 (200 mV) | 20 (400 mV) | 30 (600 mV) | 35 (700 mV) | 40 (800 mV) | 45 (900 mV) | 50 (1000 mV) | ||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | dB |
1 | 1.97 | 0.88 | 0.43 | 0.32 | 0.24 | 0.19 | 0.13 | dB |
2 | 3.58 | 1.67 | 0.95 | 0.76 | 0.61 | 0.5 | 0.41 | dB |
3 | 5.35 | 2.48 | 1.49 | 1.2 | 1 | 0.83 | 0.69 | dB |
4 | 7.27 | 3.31 | 2 | 1.63 | 1.36 | 1.14 | 0.96 | dB |
5 | — | 4.19 | 2.55 | 2.1 | 1.76 | 1.49 | 1.26 | dB |
6 | — | 5.08 | 3.11 | 2.56 | 2.17 | 1.83 | 1.56 | dB |
7 | — | 5.99 | 3.71 | 3.06 | 2.58 | 2.18 | 1.87 | dB |
8 | — | 6.92 | 4.22 | 3.47 | 2.93 | 2.48 | 2.11 | dB |
9 | — | 7.92 | 4.86 | 4 | 3.38 | 2.87 | 2.46 | dB |
10 | — | 9.04 | 5.46 | 4.51 | 3.79 | 3.23 | 2.77 | dB |
11 | — | 10.2 | 6.09 | 5.01 | 4.23 | 3.61 | — | dB |
12 | — | 11.56 | 6.74 | 5.51 | 4.68 | 3.97 | — | dB |
13 | — | 12.9 | 7.44 | 6.1 | 5.12 | 4.36 | — | dB |
14 | — | 14.44 | 8.12 | 6.64 | 5.57 | 4.76 | — | dB |
15 | — | — | 8.87 | 7.21 | 6.06 | 5.14 | — | dB |
16 | — | — | 9.56 | 7.73 | 6.49 | — | — | dB |
17 | — | — | 10.43 | 8.39 | 7.02 | — | — | dB |
18 | — | — | 11.23 | 9.03 | 7.52 | — | — | dB |
19 | — | — | 12.18 | 9.7 | 8.02 | — | — | dB |
20 | — | — | 13.17 | 10.34 | 8.59 | — | — | dB |
21 | — | — | 14.2 | 11.1 | — | — | — | dB |
22 | — | — | 15.38 | 11.87 | — | — | — | dB |
23 | — | — | — | 12.67 | — | — | — | dB |
24 | — | — | — | 13.48 | — | — | — | dB |
25 | — | — | — | 14.37 | — | — | — | dB |
26 | — | — | — | — | — | — | — | dB |
27 | — | — | — | — | — | — | — | dB |
28 | — | — | — | — | — | — | — | dB |
29 | — | — | — | — | — | — | — | dB |
30 | — | — | — | — | — | — | — | dB |
31 | — | — | — | — | — | — | — | dB |
Transceiver Compliance Specification
The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Arria® V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Intel Sales Representative.
Protocol | Sub-protocol | Data Rate (Mbps) |
---|---|---|
PCIe* | PCIe* Gen1 | 2,500 |
PCIe* Gen2 | 5,000 | |
PCIe* Cable | 2,500 | |
XAUI | XAUI 2135 | 3,125 |
Serial RapidIO® (SRIO) | SRIO 1250 SR | 1,250 |
SRIO 1250 LR | 1,250 | |
SRIO 2500 SR | 2,500 | |
SRIO 2500 LR | 2,500 | |
SRIO 3125 SR | 3,125 | |
SRIO 3125 LR | 3,125 | |
SRIO 5000 SR | 5,000 | |
SRIO 5000 MR | 5,000 | |
SRIO 5000 LR | 5,000 | |
SRIO_6250_SR | 6,250 | |
SRIO_6250_MR | 6,250 | |
SRIO_6250_LR | 6,250 | |
Common Public Radio Interface (CPRI) | CPRI E6LV | 614.4 |
CPRI E6HV | 614.4 | |
CPRI E6LVII | 614.4 | |
CPRI E12LV | 1,228.8 | |
CPRI E12HV | 1,228.8 | |
CPRI E12LVII | 1,228.8 | |
CPRI E24LV | 2,457.6 | |
CPRI E24LVII | 2,457.6 | |
CPRI E30LV | 3,072 | |
CPRI E30LVII | 3,072 | |
CPRI E48LVII | 4,915.2 | |
CPRI E60LVII | 6,144 | |
CPRI E96LVIII60 | 9,830.4 | |
Gbps Ethernet (GbE) | GbE 1250 | 1,250 |
OBSAI | OBSAI 768 | 768 |
OBSAI 1536 | 1,536 | |
OBSAI 3072 | 3,072 | |
OBSAI 6144 | 6,144 | |
Serial digital interface (SDI) | SDI 270 SD | 270 |
SDI 1485 HD | 1,485 | |
SDI 2970 3G | 2,970 | |
SONET | SONET 155 | 155.52 |
SONET 622 | 622.08 | |
SONET 2488 | 2,488.32 | |
Gigabit-capable passive optical network (GPON) | GPON 155 | 155.52 |
GPON 622 | 622.08 | |
GPON 1244 | 1,244.16 | |
GPON 2488 | 2,488.32 | |
QSGMII | QSGMII 5000 | 5,000 |
Core Performance Specifications
Clock Tree Specifications
Parameter | Performance | Unit | ||
---|---|---|---|---|
–I3, –C4 | –I5, –C5 | –C6 | ||
Global clock and Regional clock | 625 | 625 | 525 | MHz |
Peripheral clock | 450 | 400 | 350 | MHz |
PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | –3 speed grade | 5 | — | 800 61 | MHz |
–4 speed grade | 5 | — | 80061 | MHz | ||
–5 speed grade | 5 | — | 75061 | MHz | ||
–6 speed grade | 5 | — | 62561 | MHz | ||
fINPFD | Integer input clock frequency to the phase frequency detector (PFD) | — | 5 | — | 325 | MHz |
fFINPFD | Fractional input clock frequency to the PFD | — | 50 | — | 160 | MHz |
fVCO 62 | PLL voltage-controlled oscillator (VCO) operating range | –3 speed grade | 600 | — | 1600 | MHz |
–4 speed grade | 600 | — | 1600 | MHz | ||
–5 speed grade | 600 | — | 1600 | MHz | ||
–6 speed grade | 600 | — | 1300 | MHz | ||
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal global or regional clock | –3 speed grade | — | — | 500 63 | MHz |
–4 speed grade | — | — | 50063 | MHz | ||
–5 speed grade | — | — | 50063 | MHz | ||
–6 speed grade | — | — | 40063 | MHz | ||
fOUT_EXT | Output frequency for external clock output | –3 speed grade | — | — | 67063 | MHz |
–4 speed grade | — | — | 67063 | MHz | ||
–5 speed grade | — | — | 62263 | MHz | ||
–6 speed grade | — | — | 50063 | MHz | ||
tOUTDUTY | Duty cycle for external clock output (when set to 50%) | — | 45 | 50 | 55 | % |
tFCOMP | External feedback clock compensation time | — | — | — | 10 | ns |
tDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | Low | — | 0.3 | — | MHz |
Medium | — | 1.5 | — | MHz | ||
High64 | — | 4 | — | MHz | ||
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 65 66 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | ±750 | ps (p-p) | ||
tOUTPJ_DC 67 | Period jitter for dedicated clock output in integer PLL | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tFOUTPJ_DC 67 | Period jitter for dedicated clock output in fractional PLL | FOUT ≥ 100 MHz | — | — | 250 68, 175 69 | ps (p-p) |
FOUT < 100 MHz | — | — | 2568, 17.569 | mUI (p-p) | ||
tOUTCCJ_DC 67 | Cycle-to-cycle jitter for dedicated clock output in integer PLL | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tFOUTCCJ_DC 67 | Cycle-to-cycle jitter for dedicated clock output in fractional PLL | FOUT ≥ 100 MHz | — | — | 25068, 17569 | ps (p-p) |
FOUT < 100 MHz | — | — | 2568, 17.569 | mUI (p-p) | ||
tOUTPJ_IO 67 70 | Period jitter for clock output on a regular I/O in integer PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tFOUTPJ_IO 67 68 70 | Period jitter for clock output on a regular I/O in fractional PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 67 70 | Cycle-to-cycle jitter for clock output on a regular I/O in integer PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tFOUTCCJ_IO 67 68 70 | Cycle-to-cycle jitter for clock output on a regular I/O in fractional PLL | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC 67 71 | Period jitter for dedicated clock output in cascaded PLLs | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tDRIFT | Frequency drift after PFDENA is disabled for a duration of 100 µs | — | — | — | ±10 | % |
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | 8 | 24 | 32 | bits |
kVALUE | Numerator of fraction | — | 128 | 8388608 | 2147483648 | — |
fRES | Resolution of VCO frequency | fINPFD = 100 MHz | 390625 | 5.96 | 0.023 | Hz |
- Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
- Downstream PLL: Downstream PLL BW > 2 MHz
DSP Block Performance Specifications
Mode | Performance | Unit | |||
---|---|---|---|---|---|
–I3, –C4 | –I5, –C5 | –C6 | |||
Modes using One DSP Block | Independent 9 × 9 multiplication | 370 | 310 | 220 | MHz |
Independent 18 × 19 multiplication | 370 | 310 | 220 | MHz | |
Independent 18 × 25 multiplication | 370 | 310 | 220 | MHz | |
Independent 20 × 24 multiplication | 370 | 310 | 220 | MHz | |
Independent 27 × 27 multiplication | 310 | 250 | 200 | MHz | |
Two 18 × 19 multiplier adder mode | 370 | 310 | 220 | MHz | |
18 × 18 multiplier added summed with 36-bit input | 370 | 310 | 220 | MHz | |
Modes using Two DSP Blocks | Complex 18 × 19 multiplication | 370 | 310 | 220 | MHz |
Memory Block Performance Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Resources Used | Performance | Unit | |||
---|---|---|---|---|---|---|---|
ALUTs | Memory | –I3, –C4 | –I5, –C5 | –C6 | |||
MLAB | Single port, all supported widths | 0 | 1 | 500 | 450 | 400 | MHz |
Simple dual-port, all supported widths | 0 | 1 | 500 | 450 | 400 | MHz | |
Simple dual-port with read and write at the same address | 0 | 1 | 400 | 350 | 300 | MHz | |
ROM, all supported width | — | — | 500 | 450 | 400 | MHz | |
M10K Block | Single-port, all supported widths | 0 | 1 | 400 | 350 | 285 | MHz |
Simple dual-port, all supported widths | 0 | 1 | 400 | 350 | 285 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 0 | 1 | 315 | 275 | 240 | MHz | |
True dual port, all supported widths | 0 | 1 | 400 | 350 | 285 | MHz | |
ROM, all supported widths | 0 | 1 | 400 | 350 | 285 | MHz |
Internal Temperature Sensing Diode Specifications
Temperature Range | Accuracy | Offset Calibrated Option | Sampling Rate | Conversion Time72 | Resolution | Minimum Resolution with no Missing Codes |
---|---|---|---|---|---|---|
–40 to 100°C | ±8°C | No | 1 MHz | < 100 ms | 8 bits | 8 bits |
Periphery Performance
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Symbol | Condition | –I3, –C4 | –I5, –C5 | –C6 | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 73 | 5 | — | 800 | 5 | — | 750 | 5 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards74 | Clock boost factor W = 1 to 4073 | 5 | — | 625 | 5 | — | 625 | 5 | — | 500 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards75 | Clock boost factor W = 1 to 4073 | 5 | — | 420 | 5 | — | 420 | 5 | — | 420 | MHz | |
fHSCLK_OUT (output clock frequency) | — | 5 | — | 625 76 | 5 | — | 62576 | 5 | — | 50076 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) | SERDES factor J =3 to 10 77 | 78 | — | 1250 | 78 | — | 1250 | 78 | — | 1050 | Mbps |
SERDES factor J ≥ 877 79, LVDS TX with RX DPA | 78 | — | 1600 | 78 | — | 1500 | 78 | — | 1250 | Mbps | ||
SERDES factor J = 1 to 2, Uses DDR Registers | 78 | — | 80 | 78 | — | 80 | 78 | — | 80 | Mbps | ||
Emulated Differential I/O Standards with Three External Output Resistor Network - fHSDR (data rate) 81 | SERDES factor J = 4 to 10 82 | 78 | — | 945 | 78 | — | 945 | 78 | — | 945 | Mbps | |
Emulated Differential I/O Standards with One External Output Resistor Network - fHSDR (data rate)81 | SERDES factor J = 4 to 1082 | 78 | — | 200 | 78 | — | 200 | 78 | — | 200 | Mbps | |
tx Jitter -True Differential I/O Standards | Total Jitter for Data Rate 600 Mbps – 1.25 Gbps | — | — | 160 | — | — | 160 | — | — | 160 | ps | |
Total Jitter for Data Rate < 600 Mbps | — | — | 0.1 | — | — | 0.1 | — | — | 0.1 | UI | ||
tx Jitter -Emulated Differential I/O Standards with Three External Output Resistor Network | Total Jitter for Data Rate 600 Mbps – 1.25 Gbps | — | — | 260 | — | — | 300 | — | — | 350 | ps | |
Total Jitter for Data Rate < 600 Mbps | — | — | 0.16 | — | — | 0.18 | — | — | 0.21 | UI | ||
tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network | — | — | — | 0.15 | — | — | 0.15 | — | — | 0.15 | UI | |
tDUTY | TX output clock duty cycle for both True and Emulated Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE and tFALL | True Differential I/O Standards83 | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
Emulated Differential I/O Standards with Three External Output Resistor Network | — | — | 250 | — | — | 250 | — | — | 300 | ps | ||
Emulated Differential I/O Standards with One External Output Resistor Network | — | — | 500 | — | — | 500 | — | — | 500 | ps | ||
TCCS | True Differential I/O Standards | — | — | 150 | — | — | 150 | — | — | 150 | ps | |
Emulated Differential I/O Standards | — | — | 300 | — | — | 300 | — | — | 300 | ps | ||
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J =3 to 1077 | 150 | — | 1250 | 150 | — | 1250 | 150 | — | 1050 | Mbps |
SERDES factor J ≥ 8 with DPA77 79 | 150 | — | 1600 | 150 | — | 1500 | 150 | — | 1250 | Mbps | ||
fHSDR (data rate) | SERDES factor J = 3 to 10 | 78 | — | 84 | 78 | — | 84 | 78 | — | 84 | Mbps | |
SERDES factor J = 1 to 2, uses DDR registers | 78 | — | 80 | 78 | — | 80 | 78 | — | 80 | Mbps | ||
DPA Mode | DPA run length | — | — | — | 10000 | — | — | 10000 | — | — | 10000 | UI |
Soft-CDR Mode | Soft-CDR ppm tolerance | — | — | — | 300 | — | — | 300 | — | — | 300 | ±ppm |
Non-DPA Mode | Sampling Window | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions85 | Maximum Data Transition |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 640 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 640 |
10010000 | 4 | 64 | 640 | |
Miscellaneous | 10101010 | 8 | 32 | 640 |
01010101 | 8 | 32 | 640 |
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |
---|---|---|
F1 | 10,000 | 25.000 |
F2 | 17,565 | 25.000 |
F3 | 1,493,000 | 0.350 |
F4 | 50,000,000 | 0.350 |
DLL Frequency Range Specifications
Parameter | –I3, –C4 | –I5, –C5 | –C6 | Unit |
---|---|---|---|---|
DLL operating frequency range | 200 – 667 | 200 – 667 | 200 – 667 | MHz |
DQS Logic Block Specifications
Number of DQS Delay Buffer | –I3, –C4 | –I5, –C5 | –C6 | Unit |
---|---|---|---|---|
2 | 40 | 80 | 80 | ps |
Memory Output Clock Jitter Specifications
Parameter | Clock Network | Symbol | –I3, –C4 | –I5, –C5 | –C6 | Unit | |||
---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | ||||
Clock period jitter | PHYCLK | tJIT(per) | –41 | 41 | –50 | 50 | –55 | 55 | ps |
Cycle-to-cycle period jitter | PHYCLK | tJIT(cc) | 63 | 90 | 94 | ps |
OCT Calibration Block Specifications
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
OCTUSRCLK | Clock required by OCT calibration blocks | — | — | 20 | MHz |
TOCTCAL | Number of OCTUSRCLK clock cycles required for RS OCT/RT OCT calibration | — | 1000 | — | Cycles |
TOCTSHIFT | Number of OCTUSRCLK clock cycles required for OCT code to shift out | — | 32 | — | Cycles |
TRS_RT | Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT | — | 2.5 | — | ns |
Duty Cycle Distortion (DCD) Specifications
Symbol | –I3, –C4 | –C5, –I5 | –C6 | Unit | |||
---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | ||
Output Duty Cycle | 45 | 55 | 45 | 55 | 45 | 55 | % |
HPS Specifications
This section provides HPS specifications and timing for Arria® V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
HPS Clock Performance
Symbol/Description | –I3 | –C4 | –C5, –I5 | –C6 | Unit |
---|---|---|---|---|---|
mpu_base_clk (microprocessor unit clock) | 1050 | 925 | 800 | 700 | MHz |
main_base_clk (L3/L4 interconnect clock) | 400 | 400 | 400 | 350 | MHz |
h2f_user0_clk | 100 | 100 | 100 | 100 | MHz |
h2f_user1_clk | 100 | 100 | 100 | 100 | MHz |
h2f_user2_clk | 200 | 200 | 200 | 160 | MHz |
HPS PLL Specifications
HPS PLL VCO Frequency Range
Description | Speed Grade | Minimum | Maximum | Unit |
---|---|---|---|---|
VCO range | –C5, –I5, –C6 | 320 | 1,600 | MHz |
–C4 | 320 | 1,850 | MHz | |
–I3 | 320 | 2,100 | MHz |
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
Input Reference Clock Period | Divide Value (N) | Maximum Jitter | Unit |
---|---|---|---|
40 ns | 1 | 0.8 | ns |
40 ns | 2 | 1.6 | ns |
40 ns | 4 | 3.2 | ns |
Quad SPI Flash Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Fclk | SCLK_OUT clock frequency (External clock) | — | — | 108 | MHz |
Tqspi_clk | QSPI_CLK clock period (Internal reference clock) | 2.32 | — | — | ns |
Tdutycycle | SCLK_OUT duty cycle | 45 | — | 55 | % |
Tdssfrst | Output delay QSPI_SS valid before first clock edge | — | 1/2 cycle of SCLK_OUT | — | ns |
Tdsslst | Output delay QSPI_SS valid after last clock edge | –1 | — | 1 | ns |
Tdio | I/O data output delay | –1 | — | 1 | ns |
Tdin_start | Input data valid start | — | — | (2 + Rdelay) × Tqspi_clk – 7.52 86 | ns |
Tdin_end | Input data valid end | (2 + Rdelay) × Tqspi_clk – 1.21 86 | — | — | ns |
SPI Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
Tclk | CLK clock period | 16.67 | — | ns |
Tsu | SPI Master-in slave-out (MISO) setup time | 8.35 87 | — | ns |
Th | SPI MISO hold time | 1 | — | ns |
Tdutycycle | SPI_CLK duty cycle | 45 | 55 | % |
Tdssfrst | Output delay SPI_SS valid before first clock edge | 8 | — | ns |
Tdsslst | Output delay SPI_SS valid after last clock edge | 8 | — | ns |
Tdio | Master-out slave-in (MOSI) output delay | –1 | 1 | ns |
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
Tclk | CLK clock period | 20 | — | ns |
Ts | MOSI Setup time | 5 | — | ns |
Th | MOSI Hold time | 5 | — | ns |
Tsuss | Setup time SPI_SS valid before first clock edge | 8 | — | ns |
Thss | Hold time SPI_SS valid after last clock edge | 8 | — | ns |
Td | MISO output delay | — | 6 | ns |
SD/MMC Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
Tsdmmc_clk (internal reference clock) | SDMMC_CLK clock period (Identification mode) | 20 | — | ns |
SDMMC_CLK clock period (Default speed mode) | 5 | — | ns | |
SDMMC_CLK clock period (High speed mode) | 5 | — | ns | |
Tsdmmc_clk_out (interface output clock) | SDMMC_CLK_OUT clock period (Identification mode) | 2500 | — | ns |
SDMMC_CLK_OUT clock period (Default speed mode) | 40 | — | ns | |
SDMMC_CLK_OUT clock period (High speed mode) | 20 | — | ns | |
Tdutycycle | SDMMC_CLK_OUT duty cycle | 45 | 55 | % |
Td | SDMMC_CMD/SDMMC_D output delay | (Tsdmmc_clk × drvsel)/2 – 1.23 88 | (Tsdmmc_clk × drvsel)/2 + 1.69 88 | ns |
Tsu | Input setup time | 1.05 – (Tsdmmc_clk × smplsel)/2 89 | — | ns |
Th | Input hold time | (Tsdmmc_clk × smplsel)/2 89 | — | ns |
USB Timing Characteristics
PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board.
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | USB CLK clock period | — | 16.67 | — | ns |
Td | CLK to USB_STP/USB_DATA[7:0] output delay | 4.4 | — | 11 | ns |
Tsu | Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] | 2 | — | — | ns |
Th | Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] | 1 | — | — | ns |
Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle | TX_CLK duty cycle | 45 | — | 55 | % |
Td | TX_CLK to TXD/TX_CTL output data delay | –0.85 | — | 0.15 | ns |
Symbol | Description | Min | Typ | Unit |
---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | ns |
Tsu | RX_D/RX_CTL setup time | 1 | — | ns |
Th | RX_D/RX_CTL hold time | 1 | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | — | 400 | — | ns |
Td | MDC to MDIO output data delay | 10 | — | 20 | ns |
Ts | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
I2C Timing Characteristics
Symbol | Description | Standard Mode | Fast Mode | Unit | ||
---|---|---|---|---|---|---|
Min | Max | Min | Max | |||
Tclk | Serial clock (SCL) clock period | 10 | — | 2.5 | — | µs |
Tclkhigh | SCL high time | 4.7 | — | 0.6 | — | µs |
Tclklow | SCL low time | 4 | — | 1.3 | — | µs |
Ts | Setup time for serial data line (SDA) data to SCL | 0.25 | — | 0.1 | — | µs |
Th | Hold time for SCL to SDA data | 0 | 3.45 | 0 | 0.9 | µs |
Td | SCL to SDA output data delay | — | 0.2 | — | 0.2 | µs |
Tsu_start | Setup time for a repeated start condition | 4.7 | — | 0.6 | — | µs |
Thd_start | Hold time for a repeated start condition | 4 | — | 0.6 | — | µs |
Tsu_stop | Setup time for a stop condition | 4 | — | 0.6 | — | µs |
NAND Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
Twp 90 | Write enable pulse width | 10 | — | ns |
Twh 90 | Write enable hold time | 7 | — | ns |
Trp 90 | Read enable pulse width | 10 | — | ns |
Treh 90 | Read enable hold time | 7 | — | ns |
Tclesu 90 | Command latch enable to write enable setup time | 10 | — | ns |
Tcleh 90 | Command latch enable to write enable hold time | 5 | — | ns |
Tcesu 90 | Chip enable to write enable setup time | 15 | — | ns |
Tceh 90 | Chip enable to write enable hold time | 5 | — | ns |
Talesu 90 | Address latch enable to write enable setup time | 10 | — | ns |
Taleh 90 | Address latch enable to write enable hold time | 5 | — | ns |
Tdsu 90 | Data to write enable setup time | 10 | — | ns |
Tdh 90 | Data to write enable hold time | 5 | — | ns |
Tcea | Chip enable to data access time | — | 25 | ns |
Trea | Read enable to data access time | — | 16 | ns |
Trhz | Read enable to data high impedance | — | 100 | ns |
Trr | Ready to read enable low | 20 | — | ns |
Arm Trace Timing Characteristics
Description | Min | Max | Unit |
---|---|---|---|
CLK clock period | 12.5 | — | ns |
CLK maximum duty cycle | 45 | 55 | % |
CLK to D0 –D7 output data delay | –1 | 1 | ns |
UART Interface
The maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
The minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. The pulse width is based on a debounce clock frequency of 1 MHz.
HPS JTAG Timing Specifications
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
tJCP | TCK clock period | 30 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 3 | — | ns |
tJPH | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 12 91 | ns |
tJPZX | JTAG port high impedance to valid output | — | 1491 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 1491 | ns |
Configuration Specifications
This section provides configuration specifications and timing for Arria® V devices.
POR Specifications
FPGA JTAG Configuration Timing
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
tJCP | TCK clock period | 30, 16793 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 3 | — | ns |
tJPH | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 12 94 | ns |
tJPZX | JTAG port high impedance to valid output | — | 1494 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 1494 | ns |
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
Configuration Scheme | Encryption | Compression | DCLK-to-DATA[] Ratio (r) |
---|---|---|---|
FPP (8-bit wide) | Off | Off | 1 |
On | Off | 1 | |
Off | On | 2 | |
On | On | 2 | |
FPP (16-bit wide) | Off | Off | 1 |
On | Off | 2 | |
Off | On | 4 | |
On | On | 4 |
FPP Configuration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria® V Devices table.
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 600 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 600 | ns |
tCFG | nCONFIG low pulse width | 2 | — | µs |
tSTATUS | nSTATUS low pulse width | 268 | 150695 | µs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 150696 | µs |
tCF2CK 97 | nCONFIG high to first rising edge on DCLK | 1506 | — | µs |
tST2CK 97 | nSTATUS high to first rising edge of DCLK | 2 | — | µs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | 0 | — | ns |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency (FPP ×8/ ×16) | — | 125 | MHz |
tCD2UM | CONF_DONE high to user mode98 | 175 | 437 | µs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4× maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (Tinit × CLKUSR period) | — | — |
Tinit | Number of clock cycles required for device initialization | 8,576 | — | Cycles |
FPP Configuration Timing when DCLK-to-DATA[] >1
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 600 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 600 | ns |
tCFG | nCONFIG low pulse width | 2 | — | µs |
tSTATUS | nSTATUS low pulse width | 268 | 150699 | µs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 1506100 | µs |
tCF2CK 101 | nCONFIG high to first rising edge on DCLK | 1506 | — | µs |
tST2CK 101 | nSTATUS high to first rising edge of DCLK | 2 | — | µs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | N – 1/fDCLK 102 | — | s |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency (FPP ×8/ ×16) | — | 125 | MHz |
tR | Input rise time | — | 40 | ns |
tF | Input fall time | — | 40 | ns |
tCD2UM | CONF_DONE high to user mode103 | 175 | 437 | µs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (Tinit × CLKUSR period) | — | — |
Tinit | Number of clock cycles required for device initialization | 8,576 | — | Cycles |
Active Serial (AS) Configuration Timing
Symbol | Parameter | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
tCO 104 | DCLK falling edge to the AS_DATA0/ASDO output | — | — | 2 | ns |
tSU 105 | Data setup time before the falling edge on DCLK | — | 1.5 | — | ns |
tDH 105 | Data hold time after the falling edge on DCLK | –3 speed grade | 1.7 | — | ns |
–4 speed grade | 2.0 | — | ns | ||
–5 speed grade | 2.3 | — | ns | ||
–6 speed grade | 2.6 | — | ns | ||
tCD2UM | CONF_DONE high to user mode | — | 175 | 437 | µs |
tCD2CU | CONF_DONE high to CLKUSR enabled | — | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | — | tCD2CU + (Tinit × CLKUSR period) | — | — |
Tinit | Number of clock cycles required for device initialization | — | 8,576 | — | Cycles |
DCLK Frequency Specification in the AS Configuration Scheme
Parameter | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|
DCLK frequency in AS configuration scheme | 5.3 | 7.9 | 12.5 | MHz |
10.6 | 15.7 | 25.0 | MHz | |
21.3 | 31.4 | 50.0 | MHz | |
42.6 | 62.9 | 100.0 | MHz |
Passive Serial (PS) Configuration Timing
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 600 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 600 | ns |
tCFG | nCONFIG low pulse width | 2 | — | µs |
tSTATUS | nSTATUS low pulse width | 268 | 1506106 | µs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 1506107 | µs |
tCF2CK 108 | nCONFIG high to first rising edge on DCLK | 1506 | — | µs |
tST2CK 108 | nSTATUS high to first rising edge of DCLK | 2 | — | µs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | 0 | — | ns |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency | — | 125 | MHz |
tCD2UM | CONF_DONE high to user mode109 | 175 | 437 | µs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (Tinit × CLKUSR period) | — | — |
Tinit | Number of clock cycles required for device initialization | 8,576 | — | Cycles |
Initialization
Initialization Clock Source | Configuration Scheme | Maximum Frequency (MHz) | Minimum Number of Clock Cycles |
---|---|---|---|
Internal Oscillator | AS, PS, and FPP | 12.5 | Tinit |
CLKUSR 110 | PS and FPP | 125 | |
AS | 100 | ||
DCLK | PS and FPP | 125 |
Configuration Files
Variant | Member Code | Configuration .rbf Size (bits) | IOCSR .rbf Size (bits) |
---|---|---|---|
Arria® V GX | A1 | 71,015,712 | 439,960 |
A3 | 71,015,712 | 439,960 | |
A5 | 101,740,800 | 446,360 | |
A7 | 101,740,800 | 446,360 | |
B1 | 137,785,088 | 457,368 | |
B3 | 137,785,088 | 457,368 | |
B5 | 185,915,808 | 463,128 | |
B7 | 185,915,808 | 463,128 | |
Arria® V GT | C3 | 71,015,712 | 439,960 |
C7 | 101,740,800 | 446,360 | |
D3 | 137,785,088 | 457,368 | |
D7 | 185,915,808 | 463,128 | |
Arria® V SX | B3 | 185,903,680 | 450,968 |
B5 | 185,903,680 | 450,968 | |
Arria® V ST | D3 | 185,903,680 | 450,968 |
D5 | 185,903,680 | 450,968 |
Minimum Configuration Time Estimation
Variant | Member Code | Active Serial111 | Fast Passive Parallel112 | ||||
---|---|---|---|---|---|---|---|
Width | DCLK (MHz) | Minimum Configuration Time (ms) | Width | DCLK (MHz) | Minimum Configuration Time (ms) | ||
Arria® V GX | A1 | 4 | 100 | 178 | 16 | 125 | 36 |
A3 | 4 | 100 | 178 | 16 | 125 | 36 | |
A5 | 4 | 100 | 255 | 16 | 125 | 51 | |
A7 | 4 | 100 | 255 | 16 | 125 | 51 | |
B1 | 4 | 100 | 344 | 16 | 125 | 69 | |
B3 | 4 | 100 | 344 | 16 | 125 | 69 | |
B5 | 4 | 100 | 465 | 16 | 125 | 93 | |
B7 | 4 | 100 | 465 | 16 | 125 | 93 | |
Arria® V GT | C3 | 4 | 100 | 178 | 16 | 125 | 36 |
C7 | 4 | 100 | 255 | 16 | 125 | 51 | |
D3 | 4 | 100 | 344 | 16 | 125 | 69 | |
D7 | 4 | 100 | 465 | 16 | 125 | 93 | |
Arria® V SX | B3 | 4 | 100 | 465 | 16 | 125 | 93 |
B5 | 4 | 100 | 465 | 16 | 125 | 93 | |
Arria® V ST | D3 | 4 | 100 | 465 | 16 | 125 | 93 |
D5 | 4 | 100 | 465 | 16 | 125 | 93 |
Remote System Upgrades
User Watchdog Internal Oscillator Frequency Specifications
Parameter | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|
User watchdog internal oscillator frequency | 5.3 | 7.9 | 12.5 | MHz |
I/O Timing
Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel® Quartus® Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Intel® Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.
Programmable IOE Delay
Parameter115 | Available Settings | Minimum Offset116 | Fast Model | Slow Model | Unit | |||||
---|---|---|---|---|---|---|---|---|---|---|
Industrial | Commercial | –C4 | –C5 | –C6 | –I3 | –I5 | ||||
D1 | 32 | 0 | 0.508 | 0.517 | 0.870 | 1.063 | 1.063 | 0.872 | 1.057 | ns |
D3 | 8 | 0 | 1.763 | 1.795 | 2.999 | 3.496 | 3.571 | 3.031 | 3.643 | ns |
D4 | 32 | 0 | 0.508 | 0.518 | 0.869 | 1.063 | 1.063 | 1.063 | 1.057 | ns |
D5 | 32 | 0 | 0.508 | 0.517 | 0.870 | 1.063 | 1.063 | 0.872 | 1.057 | ns |