GPIO Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 19.3 |
IP Version 19.3.0 |
GPIO Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
The GPIO IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP cores.
Release Information for GPIO Intel FPGA IP
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.3.0 |
Intel® Quartus® Prime Version | 19.3 |
Release Date | 2019.09.30 |
GPIO Intel FPGA IP Features
The GPIO IP core provides these components:
- Double data rate input/output (DDIO)—a digital component that doubles or halves the data rate of a communication channel.
- Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure.
- I/O buffers—connect the pads to the FPGA.
GPIO Intel FPGA IP Data Paths
Data Path | Register Mode | |||
---|---|---|---|---|
Bypass | Simple Register | DDR I/O | ||
Full-Rate | Half-Rate | |||
Input | Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Output | Data goes from the core straight to the delay element, bypassing all DDIOs. | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Bidirectional | The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. |
If you use asynchronous clear and preset signals, all DDIOs share these same signals.
Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You can use different phase relationships to meet timing requirements.
Input Path
- The pad receives data.
- DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends the data, signals (A) and (B) in the following waveform figure, at single data rate.
- DDIO IN (2) and DDIO IN (3) halve the data rate.
- dout[3:0] presents the data as a half-rate bus.
In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. The data rate is divided by four and the bus size is increased by the same ratio. The overall throughput through the GPIO IP core remains unchanged.
The actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you choose for the full-rate and half-rate clocks.
Output and Output Enable Paths
Each output path contains two stages of DDIOs, which are half-rate and full-rate.
The difference between the output path and output enable (OE) path is that the OE path does not contain full-rate DDIO. To support packed-register implementations in the OE path, a simple register operates as full-rate DDIO. For the same reason, only one half-rate DDIO is present.
The OE path operates in the following three fundamental modes:
- Bypass—the core sends data directly to the delay element, bypassing all DDIOs.
- Packed Register—bypasses half-rate DDIO.
- SDR output at half-rate—half-rate DDIOs convert data from full-rate to half-rate.
GPIO Intel FPGA IP Interface Signals
Signal Name | Direction | Description |
---|---|---|
pad_in[SIZE-1:0] | Input |
Input signal from the pad. |
pad_in_b[SIZE-1:0] | Input |
Negative node of the differential input signal from the pad. This port is available if you turn on the Use differential buffer option. |
pad_out[SIZE-1:0] | Output | Output signal to the pad. |
pad_out_b[SIZE-1:0] | Output |
Negative node of the differential output signal to the pad. This port is available if you turn on the Use differential buffer option. |
pad_io[SIZE-1:0] | Bidirectional |
Bidirectional signal connection with the pad. |
pad_io_b[SIZE-1:0] | Bidirectional |
Negative node of the differential bidirectional signal connection with the pad. This port is available if you turn on the Use differential buffer option. |
Signal Name | Direction | Description |
---|---|---|
din[DATA_SIZE-1:0] | Input |
Data input from the FPGA core in output or bidirectional mode. DATA_SIZE depends on the register mode:
|
dout[DATA_SIZE-1:0] | Output |
Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode:
|
oe[OE_SIZE-1:0] | Input |
OE input from the FPGA core in output mode with Enable output enable port turned on, or bidirectional mode. OE is active high. When transmitting data, set this signal to 1. When receiving data, set this signal to 0. OE_SIZE depends on the register mode:
|
Signal Name | Direction | Description |
---|---|---|
ck | Input |
In input and output paths, this clock feeds a packed register or DDIO if you turn off the Half Rate logic parameter. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. |
ck_fr | Input |
In input and output paths, these clocks feed the full-rate and half-rate DDIOs if your turn on the Half Rate logic parameter. In bidirectional mode, the input and output paths use these clocks if you turn off the Separate input/output Clocks parameter. |
ck_hr | ||
ck_in | Input |
In bidirectional mode, these clocks feed a packed register or DDIO in the input and output paths if you specify both these settings:
|
ck_out | ||
ck_fr_in | Input |
In bidirectional mode, these clocks feed a full-rate and half-rate DDIOS in the input and output paths if you specify both these settings
For example, ck_fr_out feeds the full-rate DDIO in the output path. |
ck_fr_out | ||
ck_hr_in | ||
ck_hr_out | ||
cke | Input | Clock enable. |
Signal Name | Direction | Description |
---|---|---|
seriesterminationcontrol | Input | Input from the termination control block (OCT) to the buffers. It sets the buffer series impedance value. |
parallelterminationcontrol | Input | Input from the termination control block (OCT) to the buffers. It sets the buffer parallel impedance value. |
Signal Name | Direction | Description |
---|---|---|
sclr | Input | Synchronous clear input. Not available if you enable sset. |
aclr | Input | Asynchronous clear input. Active high. Not available if you enable aset. |
aset | Input | Asynchronous set input. Active high. Not available if you enable aclr. |
sset | Input | Synchronous set input. Not available if you enable sclr. |
Shared Signals
- The input, output, and OE paths share the same clear and preset signals.
- The output and OE path shares the same clock signals.
Data Bit-Order for Data Interface
- If the data bus size value is SIZE, the LSB is at the right-most position.
- If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE .
- If the data bus size value 4 × SIZE, the bus is made of four words of SIZE.
- The LSB is in the right-most position of each word.
- The right-most word specifies the first word going out for output buses and the first word coming in for input buses.
Input and Output Bus High and Low Bits
Input Bus
For the din bus, if datain_h and datain_l are the high and low bits, with each width being datain_width:
- datain_h = din[(2 × datain_width - 1):datain_width]
- datain_l = din[(datain_width - 1):0]
For example, for din[7:0] = 8'b11001010:
- datain_h = 4'b1100
- datain_l = 4'b1010
Output Bus
For the dout bus, if dataout_h and dataout_l are the high and low bits, with each width being dataout_width:
- dataout_h = dout[(2 × dataout_width - 1):dataout_width]
- dataout_l = dout[(dataout_width - 1):0]
For example, for dout[7:0] = 8'b11001010:
- dataout_h = 4'b1100
- dataout_l = 4'b1010
Data Interface Signals and Corresponding Clocks
Signal Name | Parameter Configuration | Clock | ||
---|---|---|---|---|
Register Mode | Half Rate | Separate Clocks | ||
din |
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_in | |
DDIO | On | On | ck_hr_in | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_out | |
DDIO | On | On | ck_hr_out | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_fr | |
|
Off | On |
|
|
DDIO | On | On |
|
Verifying Resource Utilization and Design Performance
- On the menu, click Processing > Start Compilation to run a full compilation.
- After compiling the design, click Processing > Compilation Report.
-
Using the Table of Contents,
navigate to Fitter > Resource Section.
- To view the resource usage information, select Resource Usage Summary.
- To view the resource utilization information, select Resource Utilization by Entity.
GPIO Intel FPGA IP Parameter Settings
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Data Direction | — |
|
Specifies the data direction for the GPIO. |
Data width | — |
1 to 128 |
Specifies the data width. |
Use legacy top-level port names | — |
|
Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices. For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l. Note: The behavior of these ports are different than in the
Stratix® V,
Arria® V, and
Cyclone® V
devices. For the migration guideline, refer to the related
information.
|
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Use differential buffer | — |
|
If turned on, enables differential I/O buffers. |
Use pseudo differential buffer |
|
|
If turned on in output mode, enables pseudo differential output buffers. This option is automatically turned on for bidirectional mode if you turn on Use differential buffer. |
Use bus-hold circuitry |
|
|
If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state will be 1 or 0 but not high-impedance. |
Use open drain output |
|
|
If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system. |
Enable output enable port | Data Direction = Output |
|
If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode. |
Enable seriestermination / paralleltermination ports | — |
|
If turned on, enables the seriesterminationcontrol and parallelterminationcontrol ports of the output buffer. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Register mode | — |
|
Specifies the register mode for the
GPIO IP core:
|
Enable synchronous clear / preset port |
|
|
Specifies how to implement synchronous reset port.
|
Enable asynchronous clear / preset port |
|
|
Specifies how to implement asynchronous reset port.
ACLR and ASET signals are active high. |
Enable clock enable ports | Register mode = DDIO |
|
|
Half Rate logic | Register mode = DDIO |
|
If turned on, enables half-rate DDIO. |
Separate input / output Clocks |
|
|
If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode. |
Register Packing
The GPIO IP core allows you to pack register into the periphery to save area and resource utilization.
You can configure the full-rate DDIO on the input and output path as a flip flop. To do so, add the .qsf assignments listed in this table.
Path | QSF Assignment |
---|---|
Input register packing | set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register> |
Output register packing | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register> |
Output enable register packing | set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register> |
GPIO Intel FPGA IP Timing
Timing Components
- I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
- Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
- Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
Delay Elements
Delay Element | .qsf Assignment |
---|---|
Input Delay Element | set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63> |
Output Delay Element | set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15> |
Output Enable Delay Element | set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15> |
Timing Analysis
Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.
- To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
- To perform proper timing analysis for the core interface paths, define these clock
settings in the .sdc file:
- Clock to the core registers
- Clock to the I/O registers for the simple register and DDIO modes
Single Data Rate Input Register
Command | Command Example | Description |
---|---|---|
create_clock | create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk | Creates clock setting for the input clock. |
set_input_delay | set_input_delay -clock sdr_in_clk 0.15 sdr_in_data | Instructs the Timing Analyzer to analyze the timing of the input I/O with a 0.15 ns input delay. |
Full-Rate or Half-Rate DDIO Input Register
Command | Command Example | Description |
---|---|---|
create_clock |
create_clock -name virtual_clock -period "200 MHz" create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk |
Create clock setting for the virtual clock and the DDIO clock. |
set_input_delay |
set_input_delay -clock virtual_clock 0.25 ddio_in_data set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data |
Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command. |
set_false_path |
set_false_path -fall_from virtual_clock -rise_to ddio_in_clk set_false_path -rise_from virtual_clock -fall_to ddio_in_clk |
Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register. Note: The ck_hr frequency must be half the ck_fr frequency. If the I/O PLL drives the clocks, you can consider using the derive_pll_clocks
.sdc command.
|
Single Data Rate Output Register
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock |
create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk |
Generate the source clock and the output clock to transmit. |
set_output_delay | set_output_delay -clock sdr_out_clk 0.45 sdr_out_data | Instructs the Timing Analyzer to analyze the output data to transmit against the output clock to transmit. |
Full-Rate or Half-Rate DDIO Output Register
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock |
create_clock -name ddio_out_fr_clk -period "200 MHz" ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -name ddio_out_fr_outclk ddio_out_fr_outclk |
Generate the clocks to the DDIO and the clock to transmit. |
set_output_delay |
set_output_delay -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_delay -add_delay -clock_fall -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data |
Instruct the Timing Analyzer to analyze the positive and negative data against the output clock. |
set_false_path |
set_false_path -rise_from ddio_out_fr_clk -fall_to ddio_out_fr_outclk set_false_path -fall_from ddio_out_fr_clk -rise_to ddio_out_fr_outclk |
Instruct the Timing Analyzer to ignore the rising edge of the source clock against the falling edge of the output clock, and the falling edge of source clock against rising edge of output clock |
Timing Closure Guidelines
To meet the hold time, add delay to the input data path using the input delay chain. In general, the input delay chain is around 60 ps per step at the –1 speed grade. To get an approximate input delay chain setting to pass the timing, divide the negative hold slack by 60 ps.
However, if the I/O PLL drives the clocks of the GPIO input registers (simple register or DDIO mode), you can set the compensation mode to source synchronous mode. The Fitter will attempt to configure the I/O PLL for a better setup and hold slack for the input I/O timing analysis.
For the GPIO output and output enable registers, you can add delay to the output data and clock using the output and output enable delay chains.
- If you observe setup time violation, you can increase the output clock delay chain setting.
- If you observe hold time violation, you can increase the output data delay chain setting.
GPIO Intel FPGA IP Design Examples
You can generate the design examples from the GPIO IP core parameter editor. After you have set the parameters that you want, click Generate Example Design. The IP core generates the design example source files in the directory you specify.
GPIO IP Core Synthesizable Intel Quartus Prime Design Example
Generating and Using the Design Example
To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following command:
quartus_sh -t make_qii_design.tcl [device_name]
The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
GPIO IP Core Simulation Design Example
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the GPIO IP core.
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl
To generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDL
The TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.
IP Migration Flow for Arria V, Cyclone V, and Stratix V Devices
This IP migration flow configures the GPIO IP core to match the settings of the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP cores, allowing you to regenerate the IP core.
Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores
To migrate your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP cores to the GPIO Intel® FPGA IP IP core, follow these steps:
- Open your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP core in the IP Parameter Editor.
- In the Currently selected device family, select Intel® Arria® 10 or Intel® Cyclone® 10 GX .
-
Click Finish to open the GPIO IP Parameter Editor.
The IP Parameter Editor configures the GPIO IP core settings similar to the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF core settings.
- If there are any incompatible settings between the two, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP core instantiation in RTL with the GPIO IP core.
Guideline: Swap datain_h and datain_l Ports in Migrated IP
The GPIO IP core drives these ports to the output registers on these clock edges:
- datain_h—on the falling edge of outclock
- datain_l—on the rising edge of outclock
If you migrated your GPIO IP from Stratix® V, Arria® V, and Cyclone® V devices, swap the datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP core.
GPIO Intel FPGA IP User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
IP Core Version | User Guide |
---|---|
18.1 | GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
18.0 | GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
17.1 | Intel® FPGA GPIO IP Core User Guide |
17.0 | Altera GPIO IP Core User Guide |
16.1 | Altera GPIO IP Core User Guide |
16.0 | Altera GPIO IP Core User Guide |
14.1 | Altera GPIO Megafunction User Guide |
13.1 | Altera GPIO Megafunction User Guide |
Document Revision History for GPIO Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.10.01 | 19.3 | Corrected typographical error in the .qsf assignment codes in the topic about delay elements. |
2019.03.04 | 18.1 | In the topics about the input path, and output and output enable
paths:
|
2018.08.28 | 18.0 |
|
Date | Version | Changes |
---|---|---|
November 2017 | 2017.11.06 |
|
May 2017 | 2017.05.08 |
|
October 2016 | 2016.10.31 |
|
August 2016 | 2016.08.05 |
|
August 2014 | 2014.08.18 |
|
November 2013 | 2013.11.29 | Initial release. |