LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.2 |
IP Version 19.4.0 |
LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
The LVDS SERDES IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTLVDS_TX and ALTLVDS_RX IP cores.
Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP version | 19.4.0 |
Intel® Quartus® Prime | 20.2 |
Release Date | 2020.06.30 |
LVDS SERDES IP Core Features
Among the features of the LVDS SERDES IP core:
- Parameterizable data channel widths
- Parameterizable SERDES factors
- Registered input and output ports
- PLL control signals
- Non-DPA mode
- DPA mode
- Soft clock data recovery (CDR) mode
LVDS SERDES IP Core Functional Modes
Functional Mode | Description |
---|---|
Transmitter (TX) |
In the transmitter mode, the SERDES block acts as a serializer. A PLL generates the following signals:
|
Non-DPA Receiver (RX Non-DPA) |
In the RX non-DPA mode, The SERDES block acts as a deserializer that bypasses the DPA and DPA-FIFO. A PLL generates the fast_clock signal. Because the incoming data is captured at the bitslip with the fast_clock signal, you must ensure the correct clock–data alignment. |
DPA-FIFO Receiver (RX DPA-FIFO) |
In the RX DPA-FIFO mode, the SERDES block acts as a deserializer that uses the DPA block. The DPA block uses a set of eight DPA clocks to select the optimal phase for sampling data. These DPA clocks run at the fast_clock frequency with each clock phase-shifted 45° apart. The DPA-FIFO, a circular buffer, samples the incoming data with the selected DPA clock and forwards the data to LVDS clock domain. The bitslip circuitry then samples the data and inserts latencies to realign the data to match the desired word boundary of the deserialized data. |
Soft-CDR Receiver (RX Soft-CDR) |
In the RX soft-CDR mode, the IP core forwards the optimal DPA clock (DPACLK) into the LVDS clock domain as the fast_clock signal. The IP core forwards the rx_divfwdclk, produced by the local clock generator, to the core through a PCLK network. Because you must place RX interfaces in one I/O bank and each bank has only 12 PCLK resources, there are only 12 soft-CDR channels available. To find out which pin pairs can support soft-CDR channels in each bank, refer to the device pin out file. In the device pin out file, the "Dedicated Tx/Rx Channel" column lists the available LVDS pin pairs in a LVDS<bank number>_<pin pair> <p or n> format. If the value of <pin pair> is an even number, the pin pair supports soft-CDR mode. |
LVDS SERDES IP Core Functional Description
Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.
The I/O PLLs drive the LVDS clock tree, providing clocking signals to the LVDS SERDES IP core channel in the I/O bank.
Path | Block | Mode | Clock Domain |
---|---|---|---|
TX Data Path | Serializer | TX | LVDS |
RX Data Path | DPA |
|
DPA |
DPA FIFO | DPA-FIFO | LVDS–DPA domain crossing | |
|
|
LVDS | |
Soft CDR | DPA | ||
Clock Generation and Multiplexers | Local Clock Generator | Soft-CDR | Generates PCLK and load_enable in these modes |
SERDES Clock Multiplexers | All | Selects LVDS clock sources for all modes |
Serializer
The first set of registers captures the parallel data from the core using the LVDS fast clock. The load_enable clock is provided alongside the LVDS fast clock, to enable these capture registers once in each coreclock period.
After the data is captured, it is loaded into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Therefore, higher order bits precede lower order bits in the output bitstream.
Signal | Description |
---|---|
tx_in[7:0] |
Data for serialization (Supported serialization factors: 3–10) |
fast_clock | Clock for the transmitter |
load_enable | Enable signal for serialization |
lvdsout | LVDS output data stream from the LVDS SERDES IP core channel |
DPA FIFO
The DPA clock may shift phase during the initial lock period. To avoid data run-through condition caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.
Bitslip
The data slips one bit for every pulse of the rx_bitslip_ctrl signal. Because it takes at least two core clock cycles to clear the undefined data, wait at least four core clock cycles before checking if the data is aligned.
After enough bitslip signals are sent to rollover the bitslip counter, the rx_bitslip_max status signal is asserted after four core clock cycles to indicate that the bitslip counter rollover point has reached its maximum counter value.
Deserializer
The load_enable is a pulse signal with a frequency equivalent to the fast clock divided by the deserialization factor.
Signal | Description |
---|---|
rx_in | LVDS input data stream to the LVDS SERDES IP core channel |
fast_clock | Clock for the receiver |
load_enable | Enable signal for deserialization |
rx_out[7:0] | Deserialized data |
LVDS SERDES IP Core Initialization and Reset
After you have initialized the IP core in DPA or non-DPA mode, you can perform word boundaries alignment using the bitslip control signal.
Initializing the LVDS SERDES IP Core in Non-DPA Mode
Intel recommends that you follow these steps to initialize the LVDS SERDES IP core in non-DPA mode:
-
During entry into user mode, assert the pll_areset signal for at least 10 ns.
You can also perform this step at any time in user mode operation to reset the interface.
- After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
Initializing the LVDS SERDES IP Core in DPA Mode
Before the PLL lock is stable, use the rx_dpa_reset signal to keep the DPA in reset. When the DPA has determined the optimal phase tap, the rx_dpa_locked signal asserts. The LVDS SERDES IP core asserts the rx_dpa_locked port at the initial DPA lock. If you turn on the Enable DPA loss of lock on one change option, the rx_dpa_locked port deasserts after one phase change. If you turn off this option, the rx_dpa_locked signal deasserts after two phase changes in the same direction.
Intel recommends that you follow these steps to initialize and reset the LVDS SERDES IP core in DPA mode:
-
During entry into user mode, assert the pll_areset and rx_dpa_reset
signals. Keep the pll_areset signal asserted
for at least 10 ns.
You can also perform this step at any time in user mode operation to reset the interface.
- After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
- Deassert the rx_dpa_reset port after the pll_locked port becomes asserted and stable.
-
Apply the DPA training pattern and allow the DPA circuit to
lock.
If a training pattern is not available, any data with transitions is required to allow the DPA to lock. For the DPA lock time specification, refer to the related information.
- After the rx_dpa_locked signal asserts, assert the rx_fifo_reset signal for at least one parallel clock cycle.
- To start receiving data, deassert the rx_fifo_reset signal.
During normal operation, every time the DPA shifts the phase taps to track variations between the reference clock source and the data, the data transfer timing margin between clock domains is reduced.
After the initialization, you can proceed to align the word boundaries (bitslip).
Resetting the DPA
-
Assert the rx_dpa_reset signal to reset the
entire DPA block. After you reset the entire DPA block, the DPA must be
retrained before capturing data.
You can also fix data corruption by resetting only the synchronization FIFO without resetting the DPA circuit, which means that system operation continues without having to retrain the DPA. To reset just the synchronization FIFO, assert the rx_fifo_reset signal.
-
After rx_dpa_locked asserts, the LVDS SERDES IP core is ready to capture
data. The DPA finds the optimal sample location to capture each bit.
Intel recommends that you toggle the rx_fifo_reset signal after rx_dpa_locked asserts. Toggling rx_fifo_reset ensures that the synchronization FIFO is set with the optimal timing to transfer data between the DPA and the high-speed LVDS clock domains.
-
Using custom logic to control the rx_bitslip_ctrl signal on a channel-by-channel basis, set up the
word boundary.
You can reset the bit slip circuit at any time, independent of the PLL or DPA circuit operation. To reset the bit slip circuit, use the rx_bitslip_reset signal.
Word Boundaries Alignment
Aligning with Control Characters
By adding control characters in the data stream, your logic can search for a known pattern to align the word boundaries. You can compare the received data for each channel, and then pulse the rx_bitslip_ctrl signal as required until you receive the control character.
Aligning without Control Characters
Without control characters in the data stream, you need a deterministic relationship between the reference clock and the data. With the deterministic relationship, you can predict the word boundary using timing simulation or laboratory measurement. You can only use deterministic relationship in non-DPA mode.
The only way to ensure a deterministic relationship on the default word position in the SERDES when the device powers up, or anytime the PLL is reset, is to have a reference clock equal to the data rate divided by the deserialization factor. This is important because the PLL locks to the rising edge of the reference clock. If you have one rising edge on the reference clock per serial word received, the deserializer always starts at the same position.
For example, if the data rate is 800 Mbps and the deserialization factor is 8, the PLL requires a 100-MHz reference clock.
Using timing simulation, or lab measurements, monitor the parallel words received and determine how many pulses of the rx_bitslip_ctrl are required to set your word boundaries. You can create a simple state machine to apply the required number of pulses after you enter user mode or at any time after you reset the PLL.
Aligning Word Boundaries
- Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the rx_bitslip_reset port.
- Begin word alignment by applying pulses as required to the rx_bitslip_ctrl port.
After the word boundaries are established on each channel, the interface is ready for operation.
LVDS SERDES IP Core Signals
Signal Name | Width | Direction | Type | Description |
---|---|---|---|---|
inclock | 1 | Input | Clock | PLL reference clock |
pll_areset | 1 | Input | Reset | Active-high asynchronous reset to all blocks in LVDS SERDES IP core and PLL |
pll_locked | 1 | Output | Control | Asserts when internal PLL locks |
Signal Name | Width | Direction | Type | Description |
---|---|---|---|---|
rx_in | N | Input | Data | LVDS serial input data |
rx_bitslip_reset | N | Input | Reset | Asynchronous, active-high reset to the clock-data alignment circuitry (bit slip) |
rx_bitslip_ctrl | N | Input | Control |
|
rx_dpa_hold | N | Input | Control |
|
rx_dpa_reset | N | Input | Reset |
|
rx_fifo_reset | N | Input | Reset |
|
rx_out | N*J | Output | Data | Receiver parallel data output
|
rx_bitslip_max | N | Output | Control |
|
rx_coreclock | 1 | Output | Clock |
|
rx_divfwdclk | N | Output | Clock |
The per channel and divided clock with the ideal DPA phase
The rx_divfwdclk signals may not be edge-aligned with each other because each channel may have a different ideal sampling phase. Each rx_divfwdclk must drive the core logic with data from the same channel. |
rx_dpa_locked | N | Output | Control |
Asserted when the DPA block selects the ideal phase
Ignore all toggling of the rx_dpa_locked signal after rx_dpa_hold asserts. |
Signal Name | Width | Direction | Type | Description |
---|---|---|---|---|
tx_in | N*J | Input | Data | Parallel data from the core |
tx_out | N | Output | Data | LVDS serial output data |
tx_outclock | 1 | Output | Clock |
|
tx_coreclock | 1 | Output | Clock |
|
Signal Name | Width | Direction | Type | Description |
---|---|---|---|---|
ext_fclk | 1 | Input | Clock |
LVDS fast clock
For more information about connecting this port with the signal from the IOPLL Intel® FPGA IP, refer to the related information. |
ext_loaden | 1 | Input | Clock |
LVDS load enable
For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information. |
ext_coreclock | 1 | Input | Clock |
|
ext_vcoph[7:0] | 8 | Input | Clock |
For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information. |
ext_pll_locked | 1 | Input | Data |
PLL lock signal Required for RX DPA-FIFO and RX Soft-CDR modes only
|
ext_tx_outclock_fclk | 1 | Input | Clock |
Phase-shifted version of fast clock Required for TX outclock phase shifts that are not multiples of 180° |
ext_tx_outclock_ loaden | 1 | Input | Clock |
Phase-shifted version of load_enable Required for TX outclock phase shifts that are not multiples of 180° |
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core PLL Settings
Parameter | Value | Description |
---|---|---|
Use external PLL | On, Off |
Turn on to use an external PLL:
This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration. Note: You must turn on this option if you want to place combined LVDS transmitter and receiver interfaces in the same I/O bank.
|
Desired inclock frequency | — | Specifies the inclock frequency in MHz. |
Actual inclock frequency | — | Displays the closest inclock frequency to the desired frequency that can source the interface. |
FPGA/PLL speed grade | — | Specifies the FPGA/PLL speed grade which determines the operation range of the PLL. |
Enable pll_areset port | On, Off | Turn on to expose the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface. |
Core clock resource type | — | Specifies onto which clock network the
IP core exports an internally generated coreclock. Note: This feature will be supported in a future version
of the
Intel®
Quartus® Prime software.
Currently, use QSF assignments to manually specify this
parameter.
|
LVDS SERDES IP Core Receiver Settings
Parameter | Value | Description |
---|---|---|
Enable bitslip mode | On, Off |
Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel). Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel. |
Enable rx_bitslip_reset port | On, Off | Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip. |
Enable rx_bitslip_max port | On, Off |
Turn on to expose the rx_bitslip_max port (one output per channel). When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero. |
Bitslip rollover value | Deserialization factor |
Specifies the maximum latency that the bit slip can inject. When the bit slip reaches the specified value, it rolls over and the rx_bitslip_max signal asserts. The rollover value is set automatically to the deserialization factor. |
Parameter | Value | Description |
---|---|---|
Enable rx_dpa_reset port | On, Off |
Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently. (Formerly known as rx_reset.) |
Enable rx_fifo_reset port | On, Off | Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block. |
Enable rx_dpa_hold port | On, Off |
Turn on to expose the rx_dpa_hold input port (one input per channel). If set high, the DPA logic in the corresponding channel does not switch sampling phases. (Formerly known as rx_dpll_hold.) |
Enable DPA loss of lock on one change | On, Off |
Deassertion of rx_dpa_locked does not indicate that the data is invalid. Instead, it indicates that the DPA has changed phase taps to track variations between the inclock and rx_in data. Intel recommends that you use data checkers to verify data accuracy. |
Enable DPA alignment only to rising edges of data | On, Off |
Note:
Intel recommends
that you use this port only for high jitter systems and turn it off
for typical applications.
|
(Simulation only) Specify PPM drift on the recovered clock(s) | — | Specifies the amount of phase drift the LVDS SERDES IP core simulation model should add to the recovered rx_divfwdclks. Note: This feature will be supported in a future version of the
Intel®
Quartus® Prime software.
|
Parameter | Value | Description |
---|---|---|
Desired receiver inclock phase shift (degrees) | — | Specifies, in degrees of the LVDS fast clock, the ideal phase delay of the inclock with respect to transitions in the incoming serial data. For example, specifying 180° implies that the inclock is center aligned to the incoming data. |
Actual receiver inclock phase shift (degrees) |
Depends on the fast_clock and inclock frequencies. Refer to the related information. |
Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift. |
Receiver Input Clock Parameters Setup
You can specify the inclock to rx_in phase relationship value in the Desired receiver inclock phase shift (degrees) parameter setting. The value must be evenly divisible by 45. If the value is not divisible by 45, the actual phase shift appears in the Actual receiver inclock phase shift (degrees) parameter setting.
Edge-Aligned inclock to rx_in
For rising inclock edge-aligned to the rx_in data, specify 0° as the desired receiver clock phase shift. Specifying 0° phase shift sets the PLL with the required phase shift from fast_clock to center it at the SERDES receiver.
The phase shift you specify is relative to the fast_clock, which operates at the serial data rate. Use phase shift values between 0° and 360° to specify the rising edge of the inclock within a single bit period. If you specify phase shift values greater than 360°, the MSB location within the parallel data changes.
This equation determines the maximum phase shift value: (Number of fast_clock periods per inclock period x 360) – 1.
Center-Aligned inclock to rx_in
To specify a center-aligned relationship between inclock and rx_in, specify a 180° phase shift.
The inclock to rx_in phase shift relationship you specify is independent of the inclock frequency.
To specify a center-aligned DDR inclock to rx_in relationship, specify a 180° phase shift.
LVDS SERDES IP Core Transmitter Settings
Parameter | Value | Description |
---|---|---|
TX core registers clock |
|
Selects the clock that clocks the core registers:
This parameter is available only in the TX functional mode. |
Enable tx_coreclock port | On, Off |
Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter. The tx_coreclock signal is a feedthrough of the ext_coreclock input. Intel recommends that you use the tx_coreclock output signal if it is requested. Note: This option is disabled if the Use external PLL option in the PLL Settings tab is turned on. To turn the Enable tx_coreclock port option on or off, turn off Use external PLL option first. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
|
Enable tx_outclock port | On, Off |
Turn on to expose the tx_outclock port.
Turning on this parameter reduces the maximum number of channels per TX interface by one channel. |
Desired tx_outclock phase shift (degrees) | Refer to related information. | Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock. |
Actual tx_outclock phase shift (degrees) | Depends on fast_clock and tx_outclock frequencies. Refer to related information. |
Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift. |
Tx_outclock division factor | Depends on the serialization factor. | Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle. |
Setting the Transmitter Output Clock Parameters
You can specify the relationship of tx_outclock to the tx_out data using these parameters:
- Desired tx_outclock phase shift (degrees)
- Tx_outclock division factor
The parameters set the phase and frequency of the tx_outclock based on the fast_clock, which operates at the serial data rate. You can specify the desired tx_outclock phase shift relative to the tx_out data at 45° increments of the fast_clock. You can set the tx_outclock frequency using the available division factors from the drop-down list.
Edge-Aligned tx_outclock to tx_out
For rising tx_outclock edge-aligned to the MSB of the serial data on tx_out, specify 0° phase shift.
Center-Aligned tx_outclock to tx_out
To specify center-aligned relationship between tx_outclock and the MSB of the serial data on tx_out, specify 180° phase shift.
- Phase shift values from 0° to 315° position the rising edge of tx_outclock within the MSB of the tx_out data.
- Phase shift values starting from 360° position the rising edge of tx_outclock in serial bits after the MSB. For example, a phase shift of 540° positions the rising edge in the center of the bit after the MSB.
Use the Tx_outclock division factor drop-down list to set the tx_outclock frequency.
LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES IP Core General Settings
Parameter | Value | Description |
---|---|---|
Functional mode |
|
Specifies the functional mode of the interface. |
Number of channels |
|
Specifies the number of serial channels in the interface.
For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver. For an LVDS TX design:
|
Data rate | 150.0 to 1600.0 | Specifies the data rate (in Mbps) of a single serial channel. The value is dependent on the Functional mode parameter settings. |
SERDES factor | 3, 4, 5, 6, 7, 8, 9, and 10 | Specifies the serialization rate or deserialization rate for the LVDS interface. |
Use backwards-compatible port names | On, Off | Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IP cores. |
LVDS SERDES IP Core Timing
Timing Component | Description |
---|---|
Source Synchronous Paths | The source synchronous paths are
paths where clock and data signals are passed from the transmitting
devices to the receiving devices. For example:
|
Dynamic Phase Alignment Paths | A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data. |
Internal FPGA Paths |
The internal FPGA paths are the paths inside the FPGA fabric:
The Timing Analyzer reports the corresponding timing margins. |
File Name | Description |
---|---|
<variation_name>_altera_lvds_core20_<quartus_version>_<random_id>.sdc |
This .sdc file allows the Intel® Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design. The IP core uses the .sdc for the following operations:
You can locate this file in the .qip generated during IP generation. |
sdc_util.tcl | This .tcl file is a library of functions and procedures that the .sdc uses. |
I/O Timing Analysis
Receiver Timing Analysis in Soft-CDR and DPA-FIFO Modes
The DPA hardware dynamically captures the received data in soft-CDR and DPA-FIFO modes. For these modes, the Timing Analyzer does not perform static I/O timing analysis.
Receiver Timing Analysis in Non-DPA Mode
In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.
To obtain accurate RSKM results in the Timing Analyzer, add this line of code to your .sdc to specify the RCCS value: set ::RCCS <RCCS value in nanoseconds> . For example, set ::RCCS 0.0.
Transmitter Timing Analysis
For LVDS transmitters, the Timing Analyzer provides the transmitter channel-to-channel skew (TCCS) value in the TCCS report (report_TCCS) in the Intel® Quartus® Prime compilation report, which shows TCCS values for serial output ports. You can also get the TCCS value from the device datasheet.
TCCS is the maximum skew observed across the channels of data and TX output clock—the difference between the fastest and slowest data output transitions, including the TCO variation and clock skew.
Obtaining RSKM Report
To obtain the RSKM report (report_rskm), follow these steps:
-
On the
Intel®
Quartus® Prime menu, select
Tools > Timing Analyzer.
The Timing Analyzer window appears.
- On the Timing Analyzer menu, select Reports > Device Specific > Report RSKM.
Obtaining TCCS Report
To obtain the TCCS report (report_tccs), follow these steps:
-
On the
Intel®
Quartus® Prime menu, select
Tools > Timing Analyzer.
The Timing Analyzer window appears.
- On the Timing Analyzer menu, select Reports > Device Specific > Report TCCS.
FPGA Timing Analysis
Clock | Clock Name |
---|---|
Core clock | <pll_instance_name>_*_outclk[*] |
LVDS fast clock | <pll_instance_name>_*_lvds_clk[*] |
Clock | Clock Name |
---|---|
Core clock | <lvds_instance_name>_core_ck_name_<channel_num> |
DPA fast clock | <lvds_instance_name>_dpa_ck_name_<channel_num> |
- For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
- For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg
With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–Core interface transfer and within the core transfer.
Timing Analysis for the External PLL Mode
Some of the SERDES constraints are derived from the PLL clocks. Therefore, the external PLL clock settings must be generated before the LVDS SERDES IP core clock settings. In you project's .qsf, ensure that the line for the IOPLL IP core's .qip appears before the line for the LVDS SERDES IP core's .qip.
derive_pll_clocks -create_base_clocks
Timing Closure Guidelines for Internal FPGA Paths
If you observe setup violation from core registers to LVDS transmitter hardware, check the TX core registers clock parameter:
- If the parameter is set to inclock, consider changing it to tx_coreclock. Core registers that use tx_coreclock have less clock delay. Because of the PLL compensation delay on the tx_coreclock path, there is less source clock delay and more setup slack for the transfer.
- If the parameter is set to tx_coreclock, consider lowering the data rate or increasing the SERDES factor to reduce the core frequency requirement and provide more setup slack.
If you observe hold violation from the LVDS receiver to core registers, consider checking the setup slack of the transfer. If there is ample setup slack, you can attempt to over-constraint the hold for the transfer. Normally, the Fitter attempts to correct the hold violation by adding delay. Under certain circumstances, the Fitter may have calculated that adding more delay for avoiding hold violation at the fast corner can negatively affect setup at the slow corner.
LVDS SERDES IP Core Design Examples
You can generate the design examples from the LVDS SERDES IP core parameter editor. After you have set the parameters that you want, click Generate Example Design. The IP core generates the design example source files in the directory you specify.
LVDS SERDES IP Core Synthesizable Intel Quartus Prime Design Examples
The design example uses the parameter settings you configured in the IP core parameter editor:
- Basic LVDS SERDES IP core system with transmitters or receivers
- LVDS SERDES IP core system with transmitters or receivers connected to an external PLL
If you configured the IP core to use an external PLL, the generated design example connects a properly configured IOPLL Intel® FPGA IP.
To demonstrate how to configure the PLL, the design example also provides the lvds_external_pll.qsys Platform Designer file containing a standalone version of the IOPLL IP core configured to work as an external PLL. You can use lvds_external_pll.qsys, modified or unmodified, to build an LVDS design with external PLL.
Generating and Using the Design Example
To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth
The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
For more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -help
LVDS SERDES IP Core Simulation Design Example
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the LVDS SERDES IP core.
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VERILOGTo generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDLThe TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.
Combined LVDS SERDES IP Core Transmitter and Receiver Design Example
If your LVDS SERDES IP core configuration implements a transmitter, the design example adds a DPA-FIFO receiver. If your LVDS SERDES IP core configuration implements any of the receiver interfaces, the design example adds a transmitter.
Generating and Using the Design Example
To generate the combined transmitter and receiver design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth_tx_rxThe TCL script creates a qii_ed_synth_tx_rx directory that contains the ed_synth_tx_rx.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
For more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -helpLVDS SERDES IP Core Dynamic Phase Shift Design Example
You can use this example in LVDS-specific applications such as debugging non-DPA receiver capture where you can repeatedly shift the capture clock to find the best operational phase shift.
You can also use the design example as a general example of using the In-System Sources and Probes feature with Signal Tap to interface with your hardware through TCL scripting. This method allows you to use manual switches to test a board without being physically present.
The dynamic phase shift design example uses LVDS SERDES IP core parameter settings and connects the IP core to an external PLL. The PLL has an exposed dynamic phase shift interface that connects to in-system sources and probes. This connection allows you to control the PLL using the In-System Sources and Probes editor or the provided TCL script in conjunction with Signal Tap.
A part of the LVDS SERDES IP core in the design example is also connected to the in-system sources and probes. The provided TCL script shows an example of how you can shift a selected PLL clock and also provides you some utility functions. You can use this example script as a start towards accomplishing the testing function that you want.
Generating and Using the Design Example
To generate the combined dynamic phase shift design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth_dpsThe TCL script creates a qii_ed_synth_dps directory that contains the ed_synth_dps.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
To use the provided TCL script to control the in-system sources and probes, run the following command:
quartus_stp -t dps_issp.tcl qii_ed_synth_dps/ed_synth_dpsFor more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -helpAdditional LVDS SERDES IP Core References
IP Migration Flow for Arria V, Cyclone V, and Stratix V Devices
This IP migration flow configures the LVDS SERDES IP core to match the settings of the ALTLVDS_TX and ALTLVDS_RX IP cores, allowing you to regenerate the IP core.
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
To migrate your ALTLVDS_TX and ALTLVDS_RX IP cores to the LVDS SERDES Intel® FPGA IP, follow these steps:
- Open your ALTLVDS_TX or ALTLVDS_RX core in the IP parameter editor.
- In the Currently selected device family, select Arria 10 or Cyclone 10 GX.
- Click Finish to open the LVDS SERDES IP core parameter editor. The parameter editor configures the LVDS SERDES IP core settings similar to the ALTLVDS_TX or ALTLVDS_RX IP core settings.
- If there are any incompatible settings between the two IP cores, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTLVDS_TX or ALTLVDS_RX IP core instantiation in RTL with the LVDS SERDES IP core.
LVDS Interface with External PLL Mode
The LVDS SERDES IP core parameter editor provides an option for implementing the LVDS interface with the Use External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings.
If you enable the Use External PLL option with the LVDS SERDES IP core transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:
- Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP core transmitter and receiver
- Load enable to the SERDES of the LVDS SERDES IP core transmitter and receiver
- Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
- Asynchronous PLL reset port of the LVDS SERDES IP core receiver
- PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP core receiver
The Clock Resource Summary tab in the LVDS SERDES IP core parameter editor provides the details for the signals in the preceding list.
You must instantiate an IOPLL IP core to generate the various clocks and load enable signals. You must configure these settings in IOPLL IP core parameter editor:
- LVDS External PLL options in the Settings tab
- Output Clocks options in the PLL tab
- Compensation Mode option in the PLL tab
LVDS Functional Mode | IOPLL IP Core Setting |
---|---|
TX, RX DPA, RX Soft-CDR | Direct mode |
RX non-DPA | LVDS compensation mode |
IOPLL IP Core Signal Interface with LVDS SERDES IP Core
From the IOPLL IP core | To the LVDS SERDES IP core transmitter | To the LVDS SERDES IP core receiver |
---|---|---|
lvds_clk[0] (serial clock output signal)
The serial clock output can only drive ext_fclk on the LVDS SERDES IP core transmitter and receiver. This clock cannot drive the core logic. |
ext_fclk (serial clock input to the transmitter) |
ext_fclk (serial clock input to the receiver) |
loaden[0] (load enable output)
|
ext_loaden (load enable to the transmitter) |
ext_loaden (load enable for the deserializer) This signal is not required for LVDS receiver in soft-CDR mode. |
outclk2 (parallel clock output) |
ext_coreclock (parallel core clock) |
ext_coreclock (parallel core clock) |
locked |
— |
pll_areset (asynchronous PLL reset port) |
phout[7:0]
|
— |
ext_vcoph This signal is required only for LVDS receiver in DPA or soft-CDR mode. |
IOPLL Parameter Values for External PLL Mode
The following examples show the clocking requirements to generate output clocks for LVDS SERDES IP core using the IOPLL IP core. The examples set the phase shift with the assumption that the clock and data are edge aligned at the pins of the device.
Parameter |
outclk0 (Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core transmitter or receiver) |
outclk1 (Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core transmitter or receiver) |
outclk2 (Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core) |
---|---|---|---|
Frequency |
data rate |
data rate/serialization factor |
data rate/serialization factor |
Phase shift |
180° |
[(deserialization factor – 1)/deserialization factor] x 360° |
180/serialization factor (outclk0 phase shift divided by the serialization factor) |
Duty cycle |
50% |
100/serialization factor |
50% |
The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.
Parameter |
outclk0 (Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core transmitter or receiver) |
outclk1 (Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core transmitter or receiver) Not required for the soft-CDR receiver. |
outclk2 (Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core) |
VCO Frequency (Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP core) |
---|---|---|---|---|
Frequency |
data rate |
data rate/serialization factor |
data rate/serialization factor |
data rate |
Phase shift |
180° |
[(deserialization factor - 1)/deserialization factor] x 360° |
180/serialization factor (outclk0 phase shift divided by the serialization factor) |
— |
Duty cycle |
50% |
100/serialization factor |
50% |
— |
Parameter |
outclk0 (Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core receiver) |
outclk1 (Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core receiver) Not required for the soft-CDR receiver. |
outclk4 (Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core) |
VCO Frequency (Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP core) |
---|---|---|---|---|
outclk2 (Connects as lvds_clk[1] to the ext_fclk port of LVDS SERDES IP core transmitter) |
outclk3 (Connects as loaden[1] to the ext_loaden port of LVDS SERDES IP core transmitter) |
|||
Frequency |
data rate |
data rate/serialization factor |
data rate/serialization factor |
data rate |
Phase shift |
180° |
[(deserialization factor - 1)/deserialization factor] x 360° |
180/serialization factor (outclk0 phase shift divided by the serialization factor) |
— |
Duty cycle |
50% |
100/serialization factor |
50% |
— |
Connection between IOPLL IP Core and LVDS SERDES IP Core in External PLL Mode
The ext_coreclock port is automatically enabled in the LVDS SERDES IP core in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.
LVDS Transmitters and Receivers in the Same I/O Bank
- To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
- You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
- In each instance, you can use up to the following number of
channels:
- 71 transmitters
- 23 DPA or non-DPA receivers
- 12 soft-CDR receivers
- Connect the same PLL to both the transmitter and receiver instances.
Comparison of LVDS SERDES IP Core with Stratix V SERDES
Features | Intel® Arria® 10/ Intel® Cyclone® 10 GX Devices | Stratix® V Devices |
---|---|---|
Operation Frequency Range | 150 MHz - 1.6 GHz1 | |
Serialization/Deserialization Factors | 3 to 10 | |
Regular DPA and non-DPA mode | Supported | |
Clock Forwarding for Soft-CDR | Supported | |
RX Resource | Every I/O pair (Every two I/O pairs for CDR) |
Every two I/O pairs on every side without HSSI transceivers |
TX Resource | Every I/O pair | Every two I/O pairs every side without HSSI transceivers |
PLL Resource | TX channels can span three adjacent banks, driven by
the IOPLL in the middle bank. RX channels are driven by the IOPLL in the same bank. |
RX and TX channels placed on one edge can be driven by the corner or center PLL. |
Number of DPA Clock Phase | 8 | |
I/O Standard | True LVDS | True LVDS, pseudo-differential output |
LVDS SERDES Intel FPGA IP User Guide Archives
IP Core Version | User Guide |
---|---|
19.3.0 | LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
19.1 | LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
18.1 | LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
18.0 | LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
17.1 | Intel® FPGA LVDS SERDES IP Core User Guide |
17.0 | Altera LVDS SERDES IP Core User Guide |
16.0 | Altera LVDS SERDES IP Core User Guide |
15.1 | Altera LVDS SERDES IP Core User Guide |
14.1 | Altera LVDS SERDES IP Core User Guide |
13.1 | Altera LVDS SERDES Megafunction User Guide |
Document Revision History for LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2020.09.25 | 20.2 | 19.4.0 | Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings. |
2020.07.10 | 20.2 | 19.4.0 |
|
2020.05.06 | 19.4 | 19.3.0 | Added the Tcl error: ERROR: Argument <clk_object> is a collection with more than one object. Specify a collection with one object. while executing "get_clock_info -period [get_clocks [lindex $fclk_setting_name 0]] KDB link in the Timing Analysis for the External PLL Mode topic. |
2020.03.10 | 19.4 | 19.3.0 |
|
2019.05.03 | 19.1 | 19.1 |
|
2019.01.30 | 18.1 | 18.1 | Added Usage Modes Summary of the LVDS SERDES table in LVDS IP Core Features topic. |
2018.12.05 | 18.1 | 18.1 |
|
2018.09.06 | 18.0 | 18.0 |
|
Date | Version | Changes |
---|---|---|
November 2017 | 2017.11.06 |
|
May 2017 | 2017.05.08 |
|
August 2016 | 2016.08.05 |
|
December 2015 | 2015.12.14 |
|
August, 2014 | 2014.08.18 |
|
November, 2013 | 2013.11.29 | Initial release. |