Remote Update Intel FPGA IP User Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 18.0 |
1. Remote Update Intel FPGA IP User Guide
The Remote Update Intel® FPGA IP core implements a device reconfiguration using dedicated remote system upgrade circuitry available in supported devices. Remote system upgrade helps you deliver feature enhancements and bug fixes without recalling your product, reduces time-to-market, and extends product life. The Remote Update Intel® FPGA IP core commands the configuration circuitry to start a reconfiguration cycle.
The dedicated circuitry performs error detection during and after the configuration process. When the dedicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe, default factory configuration image and then provides error status information.
The following figures shows a functional diagram for a typical remote system upgrade process.
- 10 MHz—for Arria® II and Stratix® IV devices
- 20 MHz—for other supported devices
1.1. Avalon-MM in Remote Update Intel FPGA IP Core
1.2. Intel Arria 10 and Intel Cyclone 10 GX Devices
1.2.1. Remote System Configuration Mode
Remote configuration supports “Direct to application” (DTA) and “Application to Application” update. Remote configuration only supports a 4-byte address scheme so there is no support for devices with densities smaller than 128 Mbit.
The CRC check on the application image is done taking only image data into consideration. Dummy bytes in programming files are not taken into account during CRC checks.
When you use low-voltage quad-serial configuration (EPCQ-L) devices, the remote update mode allows a configuration space to start at any flash sector boundary. This capability allows a maximum of 512 pages in the EPCQ-L256 device and 1024 pages in the EPCQ-L512 device, in which the minimum size of each page is 512 kilobits (Kb). Additionally, the remote update mode features an optional user watchdog timer that can detect functional errors in an application configuration.
1.2.1.1. Remote System Upgrade State Machine
After power-up and exit POR, the remote system upgrade registers are reset to 0 and the factory or application configuration image is loaded based on the start address stored at 0x00 to 0x1F in the configuration device or QSPI flash. The Remote Update Intel® FPGA IP core enables you to perform the following remote update functions once the factory or an application image is loaded successfully:
- Switch from factory image to application image
- In DTA mode, switch from initial application image to others application image
The configuration mode (AnF) bit is by default set to 0 in the DTA mode, the AnF bit cannot be used to indicate the type (such as factory or application image) of image loaded into the FPGA. In the DTA mode, the watchdog timer is disabled by default. You cannot enable the watchdog timer in the initial or first application image loaded upon powering up the device. You can enable the watchdog timer feature when you perform remote update from the initial application image to other application image.
1.2.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
Follow these steps to switch from factory to application image or from initial application image to other application image:
- Write the AnF bit to 1 via RU_RECONFIG register.
- Write the start address of the application image to be loaded via the RU_PAGE_SELECT register.
-
Enable the watchdog timer settings:
- Write the timeout value to RU_WATCHDOG_TIMEOUT register.
- Enable watchdog timeout via RU_WATCHDOG_ENABLE register.
- Writes RU_RECONFIG to “1” to trigger reconfiguration to application image. After successful reconfiguration, the system stays in the application configuration. If error occurs during reconfiguration, the RSU state machine falls back to the factory image.
- Optional step. Read the configuration status via the RU_RECONFIG_TRIGGER_CONDITIONS register.
- Write a falling edge signal to reset the watchdog timer.
-
Repeat steps 1 to 6 to perform remote update to other
application image.
Note: It is optional to instantiate the Remote Update Intel® FPGA IP core in the application image if you do not need to update the application image in user mode. Without this IP core instantiated in the application image, the device is still able to revert back to factory image if there is an error in loading the application image.
1.2.2. Remote System Configuration Components
Components | Details |
---|---|
Page mode feature |
The dedicated 32-bit start address register PGM[31..0] holds the start address. |
Factory configuration |
Factory configuration can be set as the default configuration setup depending on the address pointer set. The factory configuration loads into the device upon power-up. If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load. |
Application configuration |
Application configuration can be the default configuration setup depending on the address pointer set. The application configuration loads into the device upon power-up. The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory page. |
Watchdog timer |
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly. Intel® Arria® 10 and Intel® Cyclone® 10 GX devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or most-significant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer. |
Remote update sub-block |
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers. |
Remote configuration registers |
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The control register is 38-bits wide. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook or the Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook. |
1.2.3. Parameter Settings
GUI Name | Values | Description |
---|---|---|
Which operation mode will you be using? | REMOTE | Specifies the configuration mode of the Remote Update Intel® FPGA IP core. |
Which configuration device will you be using? | EPCQ-L device | Choose the configuration device you are using. |
Add support for writing configuration parameters | — | Enable this if you need to write configuration parameters. |
Add support for Avalon Interface | — | Enable this if you are using Avalon interface. |
Enable reconfig POF checking | — | Not available as this option is handled by the FPGA AS controller instead of the Remote Update Intel® FPGA IP core. The same application image is loaded for three times before reverting to factory application image, to ensure no unexpected system failure occurred. |
1.2.4. Ports
Name | Port | Required? | Description |
---|---|---|---|
read_param | Input | No |
Read signal for the parameter specified in param[] input port and fed to data_out[] output port. Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle. The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated and data_out[] has a valid data, another parameter can be read. |
write_param | Input | No |
Write signal for parameter specified in param[] and with value specified in data_in[]. Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type. The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_ in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in Application configuration mode. |
param[] | Input | No |
Bus that specifies which parameter need to be read or updated. A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000. |
data_in[] | Input | No |
Data input for writing parameter data into the remote update block. Input bus for parameter data. For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]). If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration. A 32-bit bus width (4-bytes addressing configuration device, for example EPCQ-L256) in the Intel® Quartus® Prime software version 14.0 or later. |
reconfig | Input | Yes |
Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored if the busy signal is asserted to ensure all parameters are completely written before reconfiguration begins. |
reset_timer | Input |
No |
Reset signal for watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted. A falling edge of this signal triggers a reset of the user watchdog timer. For the timing specification of this parameter, refer to the specific device handbook. |
clock |
Input | Yes |
Clock input to the remote update block. Clock input to control the machine and to drive the remote update block during the update of parameters. This port must be connected to a valid clock. |
reset | Input | Yes |
This is an active high signal. Asserting this signal high will reset the IP core. Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid. |
busy | Output | No |
Busy signal that indicates when remote update block is reading or writing data. While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy. This signal goes high when read_param or write_ param is asserted, and remains high until the read or write operation completes. |
data_out[] | Output | No |
Data output when reading parameters. This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted. If left unconnected, the default value for the port is 0. The width of this bus is device-dependent. For the Intel® Quartus® Prime software version 14.0 and later, the bus width is 32-bit—using 4-byte addressing configuration device, for example EPCQL-256. |
ctl_nupdt | Input | Yes |
This port allows you to select which register to be read whenever read_param operation is running.
|
1.2.5. Parameters
Bit | Parameter | Width | Comments |
---|---|---|---|
000 | Reconfiguration trigger conditions (Read Only) | 5 |
|
001 | Illegal Value | ||
010 | Watchdog Timeout Value | 12 | Width of 12 when writing. The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value. When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001. |
29 | Width of 29 when reading. | ||
011 | Watchdog Enable | 1 | — |
100 | Page Select | 32 |
For the Intel® Quartus® Prime software version 14.0 and later:
|
101 | Configuration Mode (AnF) | 1 |
This parameter is set to 1 in application page and is set to 0 in factory page. In remote update mode, this parameter can be read and written. Before loading the application page in remote update mode, Intel® recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so. |
110 | Illegal Value | ||
111 | Illegal Value |
1.2.6. Avalon-MM Interface
1.2.6.1. Control Status Register Signals
Name | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Clock input. |
reset | 1 | Input | Reset input. |
avl_csr_address | 3 | Input | Address bus. |
avl_csr_read | 1 | Input | Perform a read transaction. |
avl_csr_write | 1 | Input | Perform a write transaction. |
avl_csr_readdata | 32 | Output | Read data from IP. |
avl_csr_readdata_valid | 1 | Output | Indicate when read data is valid. |
avl_csr_writedata | 32 | Input | Write data to IP. |
avl_csr_waitrequest | 1 | Output | Waitrequest signal high indicates the core is busy. |
1.2.6.1.1. Control Status Register Write Operation
To execute the write operation for the control status register, perform the following steps:
- Asserts the avl_csr_write high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Write data into the avl_csr_writedata bus.
1.2.6.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps:
- Asserts avl_csr_read high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Wait for the avl_csr_readdata_valid signal to go high.
- Retrieve read data from avl_csr_readdata.
1.2.6.1.3. Operations Example Waveforms
1.2.6.2. Register Map
Register Name | Address Offset | Width | R/W | Description |
---|---|---|---|---|
RU_RECONFIG_TRIGGER_CONDITIONS | 0x0 | 5 | Read | Read configuration trigger conditions.
|
RU_WATCHDOG_TIMEOUT | 0x1 | 12 | Read/Write | Read or write watchdog timeout value. |
RU_WATCHDOG_ENABLE | 0x2 | 1 | Read/Write | Enable or disable watchdog timeout.
|
RU_PAGE_SELECT | 0x3 | 24 or 32 | Read/Write | Read or write start address of the configuration image. |
RU_CONFIGURATION_MODE | 0x4 | 1 | Read/Write | Write configuration mode set to 1 in application page and 0 in factory page. |
RU_RESET_TIMER | 0x5 | 1 | Write |
Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to the reset timer pin of the remote update. |
RU_RECONFIG | 0x6 | 1 | Write |
Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to the reconfig pin of the remote update and hold this value until the process done. |
RU_CTL_NUPDT | 0x7 | 1 | Write | Allow capturing of data from either Control/Update register by
controlling ctl_nupdt.
|
1.2.7. Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, select Active Serial or Configuration Device from the Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software.
Intel-provided Remote Update Intel® FPGA IP core provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Intel® Arria® 10 and Intel® Cyclone® 10 GX device logic.
When using the Remote Update Intel® FPGA IP core and the Direct to Application (DTA) mode in the Intel® Arria® 10 devices, you must enable the Auto-restart configuration after error option from the General page of the Device and Pin Option dialog box to enable the factory fall back mechanism.
1.2.8. Generating Initial RSU Image
To convert .sof files to one .jic/.rpd files and to generate the initial RSU image, follow these steps:
- Programming File type: JTAG Indirect Configuration File (.jic).
- Configuration Device: <Select the Configuration Device used in your board>.
- Mode: Select either Active Serial/Active Serial x4.
- File_name: Set the file name and your desired location.
- Optional:
- Check the Create Memory File to generate the .map file
- Check the Create config data RPD to generate the .rpd file
- Flash loader: Click Add Device, select Arria 10 and choose the Device name used in your design
- SOF DATA PAGE_0: click Add File and assign Factory image (.sof) to Page_0.
- Click Add Sof Page to add SOF Data Page_1. You can add more SOF Data Page according to the number of application images in this initial RSU image.
- SOF DATA PAGE_1: click Add File and select the application image file (.sof).
- Setting Boot Page Selection for enabling the device to boot either from factory image or application image
- To select the boot page, click the Option/Boot Info button in Convert Programming File.
- In the Options window, select the page available from the Boot from page drop down menu.
- By default, the page number will be set at Page_0.
- To allow the FPGA to boot directly from application image (DTA), change the page number to Page_1 and so on.
- Click Generate.
- Click OK when the dialog box of .jic file successfully generated appears.
1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.3.1. Remote System Configuration Mode
Remote Configuration Mode
When using with serial configuration (EPCS) or quad-serial configuration (EPCQ) devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512 Kb. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.
1.3.2. Remote System Configuration Components
Components | Details |
---|---|
Page mode feature |
The dedicated 24-bit start address register PGM[23..0] holds the start address. |
Factory configuration |
Factory configuration is the default configuration setup. In remote configuration mode, the factory configuration loads into the device upon power-up. If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load. |
Application configuration |
The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory default page. |
Watchdog timer |
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly. Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or most-significant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation. |
Remote update sub-block |
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers. |
Remote configuration registers |
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The control register is 38-bit wide. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook. |
1.3.3. Parameter Settings
GUI Name | Values | Description |
---|---|---|
Which operation mode will you be using? | REMOTE | Specifies the configuration mode. |
Which configuration device will you be using? |
|
Choose the configuration device you are using. |
Add support for writing configuration parameters | — | Enable this if you need to write configuration parameters. |
Add support for Avalon Interface 1 | — | Enable this if you are using Avalon interface. |
Enable reconfig POF checking | — | Allows you to enable .pof checking, which allows the remote update block to verify the existence of an application configuration image before the image is loaded. When you turn on this parameter, the Remote Update Intel® FPGA IP core checks the .pof and sends the reconfig signal. This option is disabled by default. |
The POF checking feature detects and verifies the existence of an application configuration image before the image is loaded. Loading an invalid application configuration image may lead to unexpected behavior of the FPGA including system failure. Examples of invalid application configuration images are:
- A partially programmed application image
- A blank application image
- An application image assigned with a wrong start address
1.3.4. Ports
Name | Port | Required? | Description |
---|---|---|---|
read_param | Input | No |
Read signal for the parameter specified in param[] input port and fed to data_out[] output port. Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle. The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated, data_out[] is valid, another parameter can be read. |
write_param | Input | No |
Write signal for parameter specified in param[] and with value specified in data_in[]. Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type. The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in application configuration mode. |
param[] | Input | No |
Bus that specifies which parameter need to be read or updated. A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000. For more information, refer to Parameters. |
data_in[] | Input | No |
Data input for writing parameter data into the remote update block. Input bus for parameter data. For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]). If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration. A 24-bit bus width in the Intel® Quartus® Prime software version 13.0 or earlier. For the Intel® Quartus® Prime software version 13.1 and later, the bus widths are as follow:
|
reconfig | Input | Yes |
Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored while the busy signal is asserted to ensure all parameters are completely written before reconfiguration begins. |
reset_timer |
Input | No |
Reset signal for watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted. A falling edge of this signal triggers a reset of the user watchdog timer. For the timing specification of this parameter, refer to the specific device handbook. |
clock | Input | Yes |
Clock input to the remote update block. Clock input to control the machine and to drive the remote update block during the update of parameters. This port must be connected to a valid clock. |
reset | Input | Yes |
This is an active high signal. Asserting this signal high will reset the IP core. Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid. |
busy | Output | No |
Busy signal that indicates when remote update block is reading or writing data. While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy. This signal goes high when read_param or write_param is asserted, and remains high until the read or write operation completes. |
data_out[] | Output | No |
Data output when reading parameters. This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted. If left unconnected, the default value for the port is 0. The width of this bus is device-dependent: For the Intel® Quartus® Prime software version 13.0 or earlier, the bus widths is 24 bits. For the Intel® Quartus® Prime software version 13.1 and later are as follow:
|
asmi_busy | Input | No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. A logic high on this pin indicates that the ASMI Parallel Intel® FPGA IP core is busy processing the operation. The Remote Update Intel® FPGA IP core waits for this pin to go low before initiating another operation. Wire this pin to the asmi_busy output port of the ASMI Parallel Intel® FPGA IP core. |
asmi_data_valid | Input | No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. A logic high on this pin indicates valid data in the asmi_dataout[7..0] output port of the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_data_valid output port of the ASMI Parallel Intel® FPGA IP core. |
asmi_dataout | Input | No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core. |
pof_error | Output | No |
Detects an invalid application configuration image. Available when the check_app_pof parameter is set to TRUE. A logic high on this pin indicates that the Remote Update Intel® FPGA IP core detects an invalid application configuration image. If asserted high, you must take corrective action by reloading a new application configuration image or specifying a different address location in the EPCS or EPCQ that contains a valid application configuration image. Wire this pin based on your system requirement. |
asmi_addr | Output | No |
Address signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core. |
asmi_read | Output | No |
Read signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. A logic high on this pin initiates the read operation on the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_read input port of the ASMI Parallel Intel® FPGA IP core. |
asmi_rden | Output | No |
Read enable signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. This pin enables the read operation on the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_rden input port of the ASMI Parallel Intel® FPGA IP core. |
1.3.5. Parameters
Bit | Parameter | Width | Comments |
---|---|---|---|
000 | Reconfiguration trigger conditions (Read Only) | 5 |
The POR value for all bits are 0. |
001 | Illegal Value | ||
010 | Watchdog Timeout Value | 12 | Width of 12 when writing. The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value. When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001. |
29 | Width of 29 when reading. | ||
011 | Watchdog Enable | 1 | — |
100 | Page Select | 24 or 32 |
For the Intel® Quartus® Prime software version 13.1 and later:
For the Intel® Quartus® Prime software version 13.0 and earlier:
|
101 | Configuration Mode (AnF) | 1 |
This parameter is set to 1 in application page and is set to 0 in factory page. In remote update mode, this parameter can be read and written. Before loading the application page in remote update mode, Intel® recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so. |
110 | Illegal Value | ||
111 | Illegal Value |
1.3.6. Avalon-MM Interface
The Avalon® -MM interface in Remote Update Intel® FPGA IP core is not supported in Stratix® II devices.
1.3.6.1. Control Status Register Signals
Name | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Clock input. |
reset | 1 | Input | Reset input. |
avl_csr_address | 3 | Input | Address bus. |
avl_csr_read | 1 | Input | Perform a read transaction. |
avl_csr_write | 1 | Input | Perform a write transaction. |
avl_csr_readdata | 32 | Output | Read data from IP. |
avl_csr_readdata_valid | 1 | Output | Indicate when read data is valid. |
avl_csr_writedata | 32 | Input | Write data to IP. |
avl_csr_waitrequest | 1 | Output | Waitrequest signal high indicates the core is busy. |
1.3.6.1.1. Control Status Register Write Operation
To execute the write operation for control the status register, perform the following steps:
- Asserts the avl_csr_write high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Write data into the avl_csr_writedata bus.
1.3.6.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps:
- Asserts avl_csr_read high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Wait for the avl_csr_readdata_valid signal to go high.
- Retrieve read data from avl_csr_readdata.
1.3.6.2. Register Map
Register Name | Address Offset | Width | R/W | Description |
---|---|---|---|---|
RU_RECONFIG_TRIGGER_CONDITIONS | 0x0 | 5 | Read | Read configuration trigger conditions.
|
RU_WATCHDOG_TIMEOUT | 0x1 | 12 | Read/Write | Read or write watchdog timeout value. |
RU_WATCHDOG_ENABLE | 0x2 | 1 | Read/Write | Enable or disable watchdog timeout.
|
RU_PAGE_SELECT | 0x3 | 24 or 32 | Read/Write | Read or write start address of configuration image. |
RU_CONFIGURATION_MODE | 0x4 | 1 | Read/Write | Write configuration mode set to 1 in application page and 0 in factory page. |
RU_RESET_TIMER | 0x5 | 1 | Write |
Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to reset timer pin of the remote update. |
RU_RECONFIG | 0x6 | 1 | Write |
Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to reconfig pin of the remote update and hold this value until the process done. |
1.3.7. Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, follow these steps:
- Select Active Serial x1/x4 or Configuration Device from the Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software.
- Select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software.
Enabling this feature automatically turns on the Auto-restart configuration after error option.
Remote Update Intel® FPGA IP core provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the device logic.
1.4. Cyclone IV and Intel Cyclone 10 LP Devices
1.4.1. Remote System Configuration Mode
Remote Configuration Mode
Only Cyclone IV E devices support both the active parallel (AP) and active serial (AS) configuration scheme for remote system upgrade. Intel® Cyclone® 10 LP and other Cyclone IV devices support only the AS configuration scheme for remote system upgrade.
When using with EPCS or EPCQ devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512 Kb. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.
1.4.2. Remote System Configuration Components
Components | Details |
---|---|
Page mode feature |
Cyclone® IV and Intel® Cyclone® 10 LP devices use a 24-bit boot start address for AS configuration in which you set the most significant 22 bits. Similar setting applies for AP configuration in Cyclone® IV E devices. In addition, Cyclone® IV and Intel® Cyclone® 10 LP devices do not support pgmout ports. |
Factory configuration |
Factory configuration is the default configuration setup. In remote configuration mode, the factory configuration loads into Cyclone® IV and Intel® Cyclone® 10 LP devices upon power-up. If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load. Upon power-up in remote update in the AP configuration scheme, Cyclone® IV E devices load the default factory configuration located at the following address: boot_address[23:0] = 24'h010000 = 24'b1 0000 0000 0000 0000. You can change the default factory configuration address to any address using the APFC_BOOT_ADDR JTAG instruction. The factory image is stored in non-volatile memory and is never updated or modified using remote access. This corresponds to the default start address location 0x010000 (or the updated address if the default address is changed) in the supported parallel flash memory. Note that 0x010000 is the 16-bit word address for the AP flash memory. However, the Intel® Quartus® Prime software implements 8-bit byte addressing. Therefore, the correct Intel® Quartus® Prime software setting for this address is 0x020000. |
Application configuration |
The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory default page. |
Watchdog timer |
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly. The devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or most-significant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation. |
Remote update sub-block |
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers. |
Remote configuration registers |
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The remote system upgrade status register has additional capabilities. Three sets of registers store the status for the current application configuration and the two previous application configurations. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook. |
1.4.3. Parameter Settings
GUI Name | Legal Value in GUI | Description |
---|---|---|
Which operation mode will you be using? | REMOTE | Specifies the configuration mode of the Remote Update Intel® FPGA IP core. |
Which configuration device will you be using? |
|
Choose the configuration device that you are using. |
Add support for writing configuration parameters | — | Enable this if you need to write configuration parameters. |
Enable reconfig POF checking | — | Allows you to enable .pof checking, which allows the remote update block to verify the existence of an application configuration image before the image is loaded. When you turn on this parameter, the Remote Update Intel® FPGA IP core checks the .pof and sends the reconfig signal. This option is disabled by default. |
1.4.4. Ports
Name | Port | Required? | Description |
---|---|---|---|
read_param |
Input |
No |
Read signal for the parameter specified in param[] input port and fed to data_out[] output port. Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle. The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated, data_out[] becomes valid and another parameter can be read. |
write_param |
Input |
No |
Write signal for parameter specified in param[] and with value specified in data_in[]. Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type. The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in application configuration mode. |
param[] |
Input |
No |
Bus that specifies which parameter need to be read or updated. A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000. For more information, refer to Parameters. |
data_in[] |
Input |
No |
Data input for writing parameter data into the remote update block. Input bus for parameter data. For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]). If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the application configuration. For the Intel® Quartus® Prime software version 13.0 or earlier, the bus width is 22-bit. For the Intel® Quartus® Prime software version 13.1 and later, the bus widths are as follow:
|
reconfig |
Input |
Yes |
Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored while busy is asserted to ensure all parameters are completely written before reconfiguration begins. |
reset_timer |
Input |
No |
Reset signal for the watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted. A falling edge of this signal triggers a reset of the user watchdog timer. For the timing specification of this parameter, refer to the specific device handbook. |
read_source |
Input |
Yes |
Specifies whether a parameter value is read from the current or a previous state. This 2-bit port specifies the state from which a parameter value is read. This signal is valid only when the read_param signal is valid. Mapping read_source[1..0] to Selected Source is defined as follow:
For details, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook. |
clock |
Input |
Yes |
Clock input to the remote update block. Clock input to control the machine and to drive the remote update block during the update of parameters. This port must be connected to a valid clock. |
reset |
Input |
Yes |
This is an active high signal. Asserting this signal high will reset the IP core. Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid. |
busy |
Output |
No |
Busy signal that indicates when remote update block is reading or writing data. While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy. This signal goes high when read_param or write_param is asserted, and remains high until the read or write operation completes. |
data_out[] |
Output |
No |
Data output when reading parameters. This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted. If left unconnected, the default value for the port is 000. The width of this bus is device-dependent: For the Intel® Quartus® Prime software version 13.0 or earlier, the bus width is 29-bit. For the Intel® Quartus® Prime software version 13.1 and later, the bus widths are as follow:
|
asmi_busy |
Input |
No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. A logic high on this pin indicates that the ASMI Parallel Intel® FPGA IP core is busy processing the operation. The Remote Update Intel® FPGA IP core waits for this pin to go low before initiating another operation. Wire this pin to the asmi_busy output port of the ASMI Parallel Intel® FPGA IP core. |
asmi_data_valid |
Input |
No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. A logic high on this pin indicates valid data in the asmi_dataout[7..0] output port of the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_data_valid output port of the ASMI Parallel Intel® FPGA IP core. |
asmi_dataout |
Input |
No |
Input from the altasmi_parallel component. Available when the check_app_pof parameter is set to true. The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core. |
pof_error |
Output |
No |
Detects an invalid application configuration image. Available when the check_app_pof parameter is set to TRUE. A logic high on this pin indicates that the Remote Update Intel® FPGA IP core detects an invalid application configuration image. If asserted high, you must take corrective action by reloading a new application configuration image or specifying a different address location in the EPCS or EPCQ that contains a valid application configuration image. Wire this pin based on your system requirement. |
asmi_addr |
Output |
No |
Address signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_addr input port of the ASMI Parallel Intel® FPGA IP core. |
asmi_read |
Output |
No |
Read signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. A logic high on this pin initiates the read operation on the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_read input port of the ASMI Parallel Intel® FPGA IP core. |
asmi_rden |
Output |
No |
Read enable signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. This pin enables the read operation on the ASMI Parallel Intel® FPGA IP core. Wire this pin to the asmi_rden input port of the ASMI Parallel Intel® FPGA IP core. |
1.4.5. Parameters
Bit | Parameter | Width | Comments |
---|---|---|---|
000 | Master State Machine Current State Mode (Read Only) | 2 |
00—Factory mode. 01—Application mode. 11—Application mode with the master state machine user watchdog timer enabled. |
001 | Force early CONF_DONE (cd_early) check | 1 | — |
010 | Watchdog Timeout Value | 12 | Width of 12 when writing. The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value. When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001. |
29 | Width of 29 when reading. | ||
011 | Watchdog Enable | 1 | — |
100 | Boot Address | — |
For the Intel® Quartus® Prime software version 13.1 and later:
For the Intel® Quartus® Prime software version 13.0 or earlier:
|
101 | Illegal Value | ||
110 | Force the internal oscillator as startup state machine clock (osc_int) option bit | 1 | — |
111 | Reconfiguration trigger conditions (Read Only) | 5 |
Bit 4 (nconfig_source)—external configuration reset (nconfig) assertion. Bit 3 (crcerror_source)—CRC error during application configuration. Bit 2 (nstatus_source)—nstatus asserted by an external device as the result of an error. Bit 1 (wdtimer_source)—User watchdog timer timeout. Bit 0 (runconfig_source)—Configuration reset triggered from logic array. |
1.4.6. Remote Update Operation
The operation defined in the Remote Update Operation column should only be performed in the corresponding master state machine (MSM) mode.
read_ param | write_ param | read_source | param | Remote Update Operation | data_out width (bits) | MSM Mode |
---|---|---|---|---|---|---|
1 | 0 | [00] | [000] | Master State Machine Current State Mode (Read Only)
|
2 | Factory or Application |
1 | 0 | [00] | [100] | Read factory boot address | 24 | Factory |
1 | 0 | [01] | [100] |
Read Past Status 1 boot address. For more information, refer to Figure 11. |
24 | Factory |
1 | 0 | [01] | [111] |
Read Past Status 1 reconfiguration trigger condition source. For more information, refer to Figure 11. |
5 | Factory |
1 | 0 | [10] | [100] |
Read Past Status 2 boot address. For more information, refer to Figure 11. |
24 | Factory |
1 | 0 | [10] | [111] |
Read Past Status 2 reconfiguration trigger condition source For more information, refer to Figure 11. |
5 | Factory |
1 | 0 | [01] | [010] | Read current application mode watchdog value | 29 | Application |
1 | 0 | [01] | [011] | Read current application mode watchdog enable | 1 | Application |
1 | 0 | [10] | [100] | Read current application mode boot address | 24 | Application |
0 | 1 | [00] | [001] |
Write the early confdone check bit. All parameters can be written in factory mode only. |
1 | Factory |
0 | 1 | [00] | [010] |
Write the watchdog time-out value. All parameters can be written in factory mode only. |
12 | Factory |
0 | 1 | [00] | [011] |
Write the watchdog enable bit. All parameters can be written in factory mode only. |
1 | Factory |
0 | 1 | [00] | [100] |
Write application boot address. All parameters can be written in factory mode only. |
22 | Factory |
0 | 1 | [00] | [110] | Write to force the internal oscillator as startup state machine clock. All parameters can be written in factory mode only. | 1 | Factory |
1 | 0 | [11] | [001] | Read the early confdone check bits | 1 | Factory |
1 | 0 | [11] | [010] | Read watchdog time-out value | 12 | Factory |
1 | 0 | [11] | [011] | Read watchdog enable bit | 1 | Factory |
1 | 0 | [11] | [100] | Read boot address | 22 | Factory |
1 | 0 | [11] | [110] | Read to check whether the internal oscillator is set as startup state machine clock | 1 | Factory |
read_source
The following table lists the details for read_source. read_source specifies whether a parameter value is read from the current or a previous state. When you trigger the read operation, all contents in the status register or input register latched to the data_out node in the Remote Update Intel® FPGA IP core.
read_source | Description |
---|---|
00 | Current state contents in status register |
01 | Previous state register 1 contents in status register |
10 | Previous state register 2 contents in status register |
11 | Current contents is in input register |
The previous state register 1 reflects the current application configuration and the previous state register 2 reflects the previous application configuration.
1.4.7. Avalon-MM Interface
1.4.7.1. Control Status Register Signals
Name | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Clock input. |
reset | 1 | Input | Reset input. |
avl_csr_address | 3 | Input | Address bus. |
avl_csr_read | 1 | Input | Perform a read transaction. |
avl_csr_write | 1 | Input | Perform a write transaction. |
avl_csr_readdata | 32 | Output | Read data from IP. |
avl_csr_readdata_valid | 1 | Output | Indicate when read data is valid. |
avl_csr_writedata | 32 | Input | Write data to IP. |
avl_csr_waitrequest | 1 | Output | Waitrequest signal high indicates the core is busy. |
1.4.7.1.1. Control Status Register Write Operation
To execute the write operation for the control status register, perform the following steps:
- Asserts the avl_csr_write high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Write data into the avl_csr_writedata bus.
1.4.7.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps:
- Asserts avl_csr_read signal high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Wait for the avl_csr_readdata_valid signal to go high.
- Retrieve read data from avl_csr_readdata.
1.4.7.2. Register Map
Register Name | Address Offset | Width | R/W | Description |
---|---|---|---|---|
RU_MASTER_SM_CURRENT_STATE_MODE | 0x0 | 2 | Read |
Read current state of the state machine 00: Factory mode 01: Application mode 11: Application mode with the master state machine user watchdog timer enabled. |
RU_FORCE_EARLY_CONF_DONE | 0x4 | 1 | Read/Write | Force early CONF_DONE |
RU_WATCHDOG_TIMEOUT | 0x8 | 29 or 12 | Read/Write | Read or write watchdog timeout value.
|
RU_WATCHDOG_ENABLE | 0xC | 1 | Read/Write | Enable or disable watchdog timeout.
|
RU_BOOT_ADDRESS |
0x10 | 24, 29 or 32 | Read/Write |
|
RU_FORCE_INTERNAL_OSC | 0x14 | 1 | Read/Write | Force the internal oscillator as startup state machine clock (osc_int) option bit |
RU_RECONFIG_TRIGGER_CONDITIONS | 0x18 | 5 | Read | Read configuration trigger conditions.
|
RU_RESET_TIMER | 0x1C | 1 | Write |
Write a value of 1 to this register to trigger reset timer of the remote update. The IP core will automatically trigger a reset pulse to reset timer pin of the remote update. |
RU_RECONFIG | 0x1D | 1 | Write |
Write to this address with value of 1 to trigger reconfiguration from a new image. The IP core will set 1 to reconfig pin of the remote update and hold this value until the process done. |
1.4.7.3. Read Source Mapping
Name | Address offset | Read source value |
---|---|---|
RU_MASTER_SM_CURRENT_STATE_MODE |
0x0 0x1 0x2 0x3 |
00 01 10 11 |
RU_FORCE_EARLY_CONF_DONE |
0x4 0x5 0x6 0x7 |
00 01 10 11 |
RU_WATCHDOG_TIMEOUT |
0x8 0x9 0xA 0xB |
00 01 10 11 |
RU_WATCHDOG_ENABLE |
0xC 0xD 0xE 0xF |
00 01 10 11 |
RU_BOOT_ADDRESS |
0x10 0x11 0x12 0x13 |
00 01 10 11 |
RU_FORCE_INTERNAL_OSC |
0x14 0x15 0x16 0x17 |
00 01 10 11 |
RU_RECONFIG_TRIGGER_CONDITIONS |
0x18 0x19 0x1A 0x1B |
00 01 10 11 |
RU_RESET_TIMER | 0x1C | N/A |
RU_RECONFIG | 0x1D | N/A |
1.4.8. Enabling Remote System Upgrade Circuitry
To enable remote update in the compiler settings of the project, perform the following steps:
- On the Assignments menu, click Device.
- In the Settings dialog box, Click Device and Pin Options.
- In the Device and Pin Options dialog box , click the Configuration tab.
- From the Configuration Mode list, select Remote.
- Click OK.
- In the Settings dialog box, click OK.
1.5. Flash Memory Programming Files
You can program the flash memory, EPCS, EPCQ, and EPCQ-L using the JTAG interface or Active Serial interface. Depending on the interface, you need to generate either a JTAG indirect configuration (.jic) file or a raw programming data (.rpd) file.
Programming Interface | Flash Memory Programming File Used | Description |
---|---|---|
JTAG Interface | .jic | The .jic file instantiates the Serial Flash Loader IP core in the design to form a bridge between the flash and the JTAG Interface. |
Active Serial Interface | .rpd | Programming data is transferred directly between the flash and download cable. |
To update the application image only, you can do either one of the following:
- Recompile the .jic file and choose new application image only in the convert programming file tool.
- Generate the .rpd file and program the EPCQ-L with ASMI IP or external controller.
1.6. Design Examples
1.6.1. Intel Arria 10 Remote Update Design Example
This Intel® Arria® 10 design example uses the Avalon® -MM interface. Intel® uses the following hardware and software to create the design example:
- Intel® Quartus® Prime Version : 15.0
- Intel® Arria® 10 Development Kit with 10AX115S3F45I2SGE2 FPGA Device
Follow these steps to perform the design example tasks:
- Unzip the contents of the design example to your working directory on your PC.
-
Convert the three .sof files into one
.jic by using Convert Programming File. On the
File Menu, click Convert Programming Files and select the details
as shown below:
- Programming File type: JTAG Indirect Configuration File (.jic).
- Select Configuration Device: EPCQL1024.
- Mode: Active Serial.
- Set the file name you your desired location.
- Flash loader: click add device and choose 10AX115S2E2.
- SOFT DATA PAGE_0: click Add File and select the factory image with start address set to <auto>.
- SOFT DATA PAGE_1: click Add File and select the application image file with start address 0x2000000. Compression is enabled for this application image file.
- SOFT DATA PAGE_2: click Add File and select the application image file with start address 0x4000000. Compression is enabled for this application image file.
- Click Generate.
- Click OK when the dialog box of .jic file successfully generated appears.
-
Please follow the steps below to run the simple design:
- After programming the .jic file, power cycle the board, all LED is lighted up. It indicates you are currently at factory image.
- Go to system console and direct to the directory where your FI_SysConsole_try.tcl is located. Type source FI_SysConsole_try.tcl.
Only one LED is lighted up which indicates successfully go to application image 1. After the watchdog timeout, all LED will light up and go back to factory image.Note: To go to application image 2 directly form the factory image, comment out the write boot address to App1 and uncomment the write boot address App2 in the FI_SysConsole_try.tcl file. -
Setting Boot Page Selection for design with more than one SOF page:
- To select the boot page, click the Option/Boot Info button in Convert Programming File.
- In the Active Serial Boot Info window, select the page available from the Boot from page drop down menu. By default, the page number will be set at page_0.
- For application to application image, change the page number to page_1 or page_2.
1.6.2. Cyclone V Remote Update Design Example
Intel® uses the following hardware and software to create the design example:
- Intel® Quartus® Prime Version : 13.0
- Cyclone® V Development Kit with 5CEFA7F31C7ES FPGA Device
Follow these steps to perform the design example tasks:
- Unzip the contents of the design example to your working directory on your PC.
- In the Intel® Quartus® Prime software, click Open Project in the File menu.
-
Compile the application image:
- Browse to the folder in which you unzipped the files and open the Application_Image.qpf.
- Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
- On the Processing menu, choose Start Compilation.
- Click OK when the full compilation successful dialog box appears. The Application_Image.sof will be generated in c:\your working directory\output_files.
- Click close project in the file menu.
-
Compile the factory image:
- Browse to the folder in which you unzipped the files and open the SVRSU.qpf.
- Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
- Choose Start Compilation on the Processing menu.
- Click OK when the full compilation successful dialog box appears. The Factory_Image.sof will be generated in c:\your working directory\output_files.
-
On the File Menu, click Convert Programming Files and select the details
as shown below:
- Programming File type: JTAG Indirect Configuration File (.jic)
- Select Configuration Device: EPCQ 128
- Mode: Active Serial x4
- File name: c:/your working directory/output_file.jic
- Flash loader: click add device and choose 5CEFA7ES
- SOFT DATA PAGE_0: click Add File and select the factory image file (SVRSU.sof)
- SOFT DATA PAGE_1: click Add File and select the Application image file (Application_Image.sof)
- Click Generate.
- Click OK when the dialog box of .jic file successfully generated appears.
-
On the Tool Menu, click Programmer and
follow these steps:
- Make sure the board is power up and the Intel® FPGA Download Cable is connected between computer and the board. This design example uses the Intel® FPGA Download Cable and JTAG mode.
- Click Auto Detect.
- Right-click on the 5CEFA7ES and select change file.
- Browse to the output_file.jic that was generated in previous steps.
- Turn on the Program/Configure checkbox and click Start.
- Configuration successful indicates the FPGA is configured successfully.
1.7. Remote Update Intel FPGA IP User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
IP Core Version | User Guide |
---|---|
16.0 | Altera Remote Update IP Core User Guide |
15.1 | Altera Remote Update IP Core User Guide |
15.0 | Altera Remote Update IP Core User Guide |
14.0 | Altera Remote Update IP Core User Guide |
1.8. Document Revision History for the Remote Update Intel FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.02.11 | 18.0 | Updated the Enabling Remote System Upgrade Circuitry topic. |
2019.12.24 | 18.0 |
|
2019.10.22 | 18.0 |
|
2019.04.26 | 18.0 |
|
2019.01.09 | 18.0 |
|
2018.11.26 | 18.0 |
|
Date | Version | Changes |
---|---|---|
April 2017 | 2017.04.10 |
|
October 2016 | 2016.10.31 |
|
June 2016 | 2016.06.01 |
|
May 2016 | 2016.05.02 |
|
December 2015 | 2015.12.14 | Updated RU_RECONFIG_TRIGGER_CONDITIONS description for Cyclone V Avalon-MM interface register. |
November 2015 | 2015.11.17 |
|
June 2015 | 2015.06.15 |
|
April 2015 | 2015.04.07 | Added design example link. |
January 2015 | 2015.01.23 | Updated Arria 10 remote system configuration mode flow diagram. |
December 2014 | 2014.12.15 |
|
June 2014 | 2014.06.30 |
|
May 2014 | 2014.05.13 |
|
August 2013 | 2013.08.16 | Added Cyclone IV devices support for Active Serial Remote Configuration Mode in Parameters, Output Ports, and Active Serial Remote Configuration Mode. |
July 2013 | 2013.07.12 |
|
July 2013 | 2013.07.12 |
|
February 2012 | 3.0 | Add Cyclone IV support for param[] parameter. |
August 2010 | 2.5 |
Updated for Quartus II software v10.0, including:
|
April 2009 | 2.4 |
Updated for Quartus II software v9.0, including:
|
May 2007 | 2.3 |
Updated for Quartus II software v7.1, including:
|
March 2007 | 2.2 | Updated Chapter 1 to include Cyclone III support. |
December 2006 | 2.1 | Updated Chapter 1 to include Stratix® III support. |
September 2006 | 2.0 | General update for Quartus II software version 6.0, including screenshots; added ModelSim®-Altera simulation tool section to Chapter 3. |
March 2005 | 1.0 | Initial release. |