The data_valid signal starts low in the
initial state where no data is being read from the device. After feeding a clock signal
to the clkin input port, the chip ID IP core reads the
unique chip ID. After reading, the IP core asserts the data_valid signal to indicate that the unique chip ID value at the output
port is ready for retrieval. The operation repeats only when you reset the IP core.
The chip_id[63:0] output port holds the
value of the unique chip ID until you reconfigure the device or reset the IP core.
Figure 1. Chip ID Ports
Table 2. Chip ID Ports
Feeds clock signal to the chip ID block. The maximum
supported frequencies are
Equivalent to your system clock.
Cyclone® 10 GX: 30 MHz.
Arria® V and
Cyclone® V: 100 MHz.
When you provide a clock signal, the IP core reads
the value of the unique chip ID and sends the value to the chip_id output port.
Synchronous reset that resets the IP
devices other than the
reset the IP core, assert the reset
signal high for at least 10 clkin
[63:0]output port holds the value of the unique chip ID
until you reconfigure the device or reset the IP core.
Indicates that the unique chip ID is ready for retrieval. If the
signal is low, the IP core is in initial state or in progress to load data from
a fuse ID. After the IP core asserts the signal, the data is ready for
retrieval at the
chip_id[63..0] output port.
Indicates the unique chip ID according to its respective fuse ID
location. The data is only valid after the IP core asserts the
The value at power-up resets to
Stratix® 10 devices only.
Reads the device ID.
the device ID, drive the signal high for at least 10 clkin cycles, then pull the signal
Accessing Intel Arria 10 and Intel Cyclone 10 GX Chip ID through JTAG
Arria® 10 and
Cyclone® 10 GX chip ID is inaccessible if you have
other systems or IP cores accessing the JTAG simultaneously. For example, the SignalTap II Logic Analyzer, Transceiver
Toolkit, in-system signals or probes, and the SmartVID Controller IP core.
When you toggle the reset signal, the chip ID IP core starts reading the chip
ID from the
Arria® 10 or
Cyclone® 10 GX
device. When the chip ID is ready, the chip ID IP core asserts the data_valid signal and ends the JTAG access.
Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the
unique chip ID. Refer
the respective device
datasheet for tCD2UM value.
Resetting the IP Core
To reset the IP core, you must assert the reset signal for at least ten clock
cycles. After you deassert the reset signal, the IP core rereads the unique chip ID
from the fuse ID block. The IP core asserts the data_valid signal after completing the operation.
Arria® V, and
devices, do not reset the IP core until at least tCD2UM
after full chip initialization. Refer the respective device datasheet for tCD2UM value.
Document Revision History for Chip ID Intel FPGA IP Cores User Guide
Quartus® Prime Version
Updated the readid port
Updated the reset port
Added readid port for Chip ID Intel® Stratix 10 FPGA IP core.
Updated document title from Altera Unique Chip ID IP Core
Added Device Support section.
Combined and added information from Altera Arria 10 Unique
Chip ID IP Core User Guide and Stratix 10
Unique Chip ID IP Core User Guide.
Updated Functional Description.
Cyclone® 10 GX device support.
Removed standard IP core information and added
link to Quartus Prime Handbook.
Updated note about Arria 10 device support.
document title to reflect new name of "Altera Unique Chip ID" IP
parameterization steps for legacy parameter editor.
note that this IP core does not support Arria 10 designs.
Replaced MegaWizard Plug-In Manager information with IP
standard information about upgrading IP cores.
standard installation and licensing information.
outdated device support level information. IP core device
support is now available in IP Catalog and parameter editor.
Updated to reword "Acquiring the chip ID of an FPGA
device" to "Acquiring the unique chip ID of an FPGA device"