Intel Arria 10 Core Fabric and General Purpose I/Os Handbook
Logic Array Blocks and Adaptive Logic Modules in Intel Arria 10 Devices
You can use a quarter of the available LABs in the Intel® Arria® 10 devices as a memory LAB (MLAB). Certain devices may have higher MLAB ratio.
The Intel® Quartus® Prime software and other supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.
This chapter contains the following sections:
- LAB
- ALM Operating Modes
LAB
MLAB is a superset of the LAB and includes all the LAB features.
MLAB
You can configure each ALM in an MLAB as a 32 (depth) × 2 (width) memory block, resulting in a configuration of 32 (depth) × 20 (width) simple dual-port SRAM block.
MLAB supports the following 64-deep modes in soft implementation using the Intel® Quartus® Prime software:
- 64 (depth) × 8 (width)
- 64 (depth) × 9 (width)
- 64 (depth) × 10 (width)
Local and Direct Link Interconnects
The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility.
The local interconnect drives ALMs in the same LAB using column and row interconnects, and ALM outputs in the same LAB.
Neighboring LABs, MLABs, M20K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB’s local interconnect using the direct link connection.
Shared Arithmetic Chain and Carry Chain Interconnects
LAB Control Signals
The LAB control block generates up to three clocks using the two clock sources and three clock enable signals. An inverted clock source is considered as an individual clock source. Each clock and the clock enable signals are linked.
Deasserting the clock enable signal turns off the corresponding LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. The inherent low skew of the MultiTrack interconnect allows clock and control signal distribution in addition to data. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear signal. The ALM directly supports an asynchronous clear function. The register preset is implemented as the NOT-gate push-back logic in the Intel® Quartus® Prime software. Each LAB supports up to two clears.
Intel® Arria® 10 devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. You can enable the DEV_CLRn pin in the Intel® Quartus® Prime software before compilation. The device-wide reset signal overrides all other control signals.
ALM Resources
With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input functions.
One ALM contains four programmable registers. Each register has the following ports:
- Data
- Clock
- Synchronous and asynchronous clear
- Synchronous load
Global signals, general purpose I/O (GPIO) pins, or any internal logic can drive the clock enable signal and the clock and clear control signals of an ALM register.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.
ALM Output
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output while the register drives another output.
Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. The ALM can also drive out registered and unregistered versions of the LUT or adder output.
ALM Operating Modes
The Intel® Arria® 10 ALM operates in any of the following modes:
- Normal mode
- Extended LUT mode
- Arithmetic mode
- Shared arithmetic mode
Normal Mode
Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
The Intel® Quartus® Prime Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.
For the packing of two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab).
In the case of implementing two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. In a sparsely used device, functions that could be placed in one ALM may be implemented in separate ALMs by the Intel® Quartus® Prime software to achieve the best possible performance. As a device begins to fill up, the Intel® Quartus® Prime software automatically uses the full potential of the Intel® Arria® 10 ALM. The Intel® Quartus® Prime Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments.
You can implement any six-input function using the following inputs:
- dataa
- datab
- datac
- datad
- datae0 and dataf1, or datae1 and dataf0
If you use datae0 and dataf1 inputs, you can obtain the following outputs:
- Output driven to register0 or register0 is bypassed
- Output driven to register1 or register1 is bypassed
You can use the datae1 or dataf0 input, whichever is available, as the packed register input to register2 or register3.
If you use datae1 and dataf0 inputs, you can obtain the following outputs:
- Output driven to register2 or register2 is bypassed
- Output driven to register3 or register3 is bypassed
You can use the datae0 or dataf1 input, whichever is available, as the packed register input to register0 or register1.
Extended LUT Mode
A seven-input function can be implemented in a single ALM using the following inputs:
- dataa
- datab
- datac
- datad
- datae0
- datae1
- dataf0 or dataf1
If you use dataf0 input, you can obtain the following outputs:
- Output driven to register0 or register0 is bypassed
- Output driven to register1 or register1 is bypassed
You can use the dataf1 input as the packed register input to register2 or register3.
If you use dataf1 input, you can obtain the following outputs:
- Output driven to register2 or register2 is bypassed
- Output driven to register3 or register3 is bypassed
You can use the dataf0 input as the packed register input to register0 or register1.
Arithmetic Mode
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output of two four-input functions.
The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs. The adder output is ignored in this operation.
Using the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this mode.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, and synchronous load.
The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down, and add/subtract control signals. These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM.
The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each register. The Intel® Quartus® Prime software automatically places any registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode.
The two-bit carry select feature in Intel® Arria® 10 devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.
To avoid routing congestion in one small area of the device if a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Intel® Quartus® Prime Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
Shared Arithmetic Mode
This mode configures the ALM with four four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated connection called the shared arithmetic chain.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a four-input adder. This significantly reduces the resources necessary to implement large adder trees or correlator functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Intel® Quartus® Prime Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column.
LAB Power Management Techniques
Use the following techniques to manage static and dynamic power consumption within the LAB:
- Intel® Arria® 10 LABs operate in high-performance mode or low-power mode. The Intel® Quartus® Prime software automatically optimizes the LAB power consumption mode based on your design.
- Clocks, especially LAB clocks, consumes a significant portion of dynamic power. Each LAB's clock and clock enable signals are linked and can be controlled by a shared, gated clock. Use the LAB-wide clock enable signal to gate the LAB-wide clock without disabling the entire clock tree. In your HDL code for registered logic, use a clock-enable construct.
Logic Array Blocks and Adaptive Logic Modules in Intel Arria 10 Devices Revision History
Date | Version | Changes |
---|---|---|
March 2017 | 2017.03.15 | Rebranded as Intel. |
October 2016 | 2016.10.31 | Added description on clock source in the LAB Control Signals section. |
November 2015 | 2015.11.02 | Changed instances of Quartus II to Quartus Prime. |
December 2013 | 2013.12.02 | Initial release. |
Embedded Memory Blocks in Intel Arria 10 Devices
The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements.
Types of Embedded Memory
The Intel® Arria® 10 devices contain two types of memory blocks:
- 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are ideal for larger memory arrays while still providing a large number of independent ports.
- 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Intel® Arria® 10 devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Embedded Memory Capacity in Intel Arria 10 Devices
Variant | Product Line | M20K | MLAB | Total RAM Bit (Kb) | ||
---|---|---|---|---|---|---|
Block | RAM Bit (Kb) | Block | RAM Bit (Kb) | |||
Intel® Arria® 10 GX | GX 160 | 440 | 8,800 | 1,680 | 1,050 | 9,850 |
GX 220 | 587 | 11,740 | 2,703 | 1,690 | 13,430 | |
GX 270 | 750 | 15,000 | 3,922 | 2,452 | 17,452 | |
GX 320 | 891 | 17,820 | 4,363 | 2,727 | 20,547 | |
GX 480 | 1,431 | 28,620 | 6,662 | 4,164 | 32,784 | |
GX 570 | 1,800 | 36,000 | 8,153 | 5,096 | 41,096 | |
GX 660 | 2,131 | 42,620 | 9,260 | 5,788 | 48,408 | |
GX 900 | 2,423 | 48,460 | 15,017 | 9,386 | 57,846 | |
GX 1150 | 2,713 | 54,260 | 20,774 | 12,984 | 67,244 | |
Intel® Arria® 10 GT | GT 900 | 2,423 | 48,460 | 15,017 | 9,386 | 57,846 |
GT 1150 | 2,713 | 54,260 | 20,774 | 12,984 | 67,244 | |
Intel® Arria® 10 SX | SX 160 | 440 | 8,800 | 1,680 | 1,050 | 9,850 |
SX 220 | 587 | 11,740 | 2,703 | 1,690 | 13,430 | |
SX 270 | 750 | 15,000 | 3,922 | 2,452 | 17,452 | |
SX 320 | 891 | 17,820 | 4,363 | 2,727 | 20,547 | |
SX 480 | 1,431 | 28,620 | 6,662 | 4,164 | 32,784 | |
SX 570 | 1,800 | 36,000 | 8,153 | 5,096 | 41,096 | |
SX 660 | 2,131 | 42,620 | 9,260 | 5,788 | 48,408 |
Embedded Memory Design Guidelines for Intel Arria 10 Devices
There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
Consider the Memory Block Selection
The Intel® Quartus® Prime software automatically partitions the user-defined memory into the memory blocks based on your design's speed and size constraints. For example, the Intel® Quartus® Prime software may spread out the memory across multiple available memory blocks to increase the performance of the design.
To assign the memory to a specific block size manually, use the RAM IP core in the parameter editor.
For the MLABs, you can implement single-port SRAM through emulation using the Intel® Quartus® Prime software. Emulation results in minimal additional use of logic resources.
Because of the dual purpose architecture of the MLAB, only data input registers, output registers, and write address registers are available in the block. The MLABs gain read address registers from the ALMs.
Guideline: Implement External Conflict Resolution
In the true dual-port RAM mode, you can perform two write operations to the same memory location. However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data being written to the address, implement external conflict resolution logic to the memory block.
Guideline: Customize Read-During-Write Behavior
Customize the read-during-write behavior of the memory blocks to suit your design requirements.
Same-Port Read-During-Write Mode
The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port RAM.
Output Mode | Memory Type | Description |
---|---|---|
"new data"
(flow-through) |
M20K | The new data is available on the rising edge of the same clock cycle on which the new data is written. |
"don't care" | M20K, MLAB | The RAM outputs "don't care" values for a read-during-write operation. |
Mixed-Port Read-During-Write Mode
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports perform read and write operations on the same memory address using the same clock—one port reading from the address, and the other port writing to it.
Output Mode | Memory Type | Description |
---|---|---|
"new data" | MLAB |
A read-during-write operation to different ports causes the MLAB registered output to reflect the “new data” on the next rising edge after the data is written to the MLAB memory. This mode is available only if the output is registered. |
"old data" | M20K, MLAB |
A read-during-write operation to different ports causes the RAM output to reflect the “old data” value at the particular address. For MLAB, this mode is available only if the output is registered. |
"don't care" | M20K, MLAB |
The RAM outputs “don’t care” or “unknown” value.
|
"constrained don't care" | MLAB |
The RAM outputs “don’t care” or “unknown” value. The Intel® Quartus® Prime software analyzes the timing between write and read operations in the MLAB. |
In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input registers have the same clock.
Guideline: Consider Power-Up State and Memory Initialization
Consider the power up state of the different types of memory blocks if you are designing logic that evaluates the initial power-up values, as listed in the following table.
Memory Type | Output Registers | Power Up Value |
---|---|---|
MLAB | Used | Zero (cleared) |
Bypassed | Read memory contents | |
M20K | Used | Zero (cleared) |
Bypassed | Zero (cleared) |
By default, the Intel® Quartus® Prime software initializes the RAM cells in Intel® Arria® 10 devices to zero unless you specify a .mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Intel® Quartus® Prime software and specify their use with the RAM IP core when you instantiate a memory in your design. Even if a memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.
Guideline: Control Clocking to Reduce Power Consumption
Reduce AC power consumption of each memory block in your design:
- Use Intel® Arria® 10 memory block clock-enables to allow you to control clocking of each memory block.
- Use the read-enable signal to ensure that read operations occur only when necessary. If your design does not require read-during-write, you can reduce your power consumption by deasserting the read-enable signal during write operations, or during the period when no memory operations occur.
- Use the Intel® Quartus® Prime software to automatically place any unused memory blocks in low-power mode to reduce static power.
Embedded Memory Features
Features | M20K | MLAB |
---|---|---|
Maximum operating frequency |
730 MHz |
700 MHz |
Total RAM bits (including parity bits) |
20,480 |
640 |
Parity bits | Supported | — |
Byte enable | Supported | Supported |
Packed mode | Supported | — |
Address clock enable | Supported | — |
Simple dual-port mixed width | Supported | — |
True dual-port mixed width | Supported | — |
FIFO buffer mixed width | Supported | — |
Memory Initialization File (.mif) | Supported | Supported |
Mixed-clock mode | Supported | Supported |
Fully synchronous memory | Supported | Supported |
Asynchronous memory | — | Only for flow-through read memory operations. |
Power-up state |
Output ports are cleared. |
|
Asynchronous clears | Output registers and output latches | Output registers and output latches |
Write/read operation triggering | Rising clock edges | Rising clock edges |
Same-port read-during-write |
Output ports set to "new data" or "don't care". |
Output ports set to "don't care". |
Mixed-port read-during-write | Output ports set to "old data" or "don't care". | Output ports set to "old data", "new data", "don't care", or "constrained don't care". |
ECC support |
Soft IP support using the Intel® Quartus® Prime software. Built-in support in x32-wide simple dual-port mode. |
Soft IP support using the Intel® Quartus® Prime software. |
Embedded Memory Modes
Memory Mode | M20K Support | MLAB Support | Description |
---|---|---|---|
Single-port RAM | Yes | Yes |
You can perform only one read or one write operation at a time. Use the read enable port to control the RAM output ports behavior during a write operation:
|
Simple dual-port RAM | Yes | Yes |
You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B. |
True dual-port RAM | Yes | — |
You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. |
Shift-register | Yes | Yes |
You can use the memory blocks as a shift-register block to save logic cells and routing resources. This is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers. The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers. |
ROM | Yes | Yes |
You can use the memory blocks as ROM.
|
FIFO | Yes | Yes |
You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO megafunctions to implement single- and dual-clock asynchronous FIFO buffers in your design. For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode. |
Embedded Memory Configurations for Single-port Mode
Memory Block | Depth (bits) | Programmable Width |
---|---|---|
MLAB | 32 | x16, x18, or x20 |
64 1 | x8, x9, x10 | |
M20K | 512 | x40, x32 |
1K | x20, x16 | |
2K | x10, x8 | |
4K | x5, x4 | |
8K | x2 | |
16K | x1 |
Embedded Memory Configurations for Dual-port Modes
Read Port | Write Port | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
16K×1 | 8K×2 | 4K×4 | 4K×5 | 2K×8 | 2K×10 | 1K×16 | 1K×20 | 512×32 | 512×40 | |
16K×1 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
8K×2 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
4K×4 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
4K×5 | — | — | — | Yes | — | Yes | — | Yes | — | Yes |
2K×8 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
2K×10 | — | — | — | Yes | — | Yes | — | Yes | — | Yes |
1K×16 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
1K×20 | — | — | — | Yes | — | Yes | — | Yes | — | Yes |
512×32 | Yes | Yes | Yes | — | Yes | — | Yes | — | Yes | — |
512×40 | — | — | — | Yes | — | Yes | — | Yes | — | Yes |
Port A | Port B | |||||||
---|---|---|---|---|---|---|---|---|
16K×1 | 8K×2 | 4K×4 | 4K×5 | 2K×8 | 2K×10 | 1K×16 | 1K×20 | |
16K×1 | Yes | Yes | Yes | — | Yes | — | Yes | — |
8K×2 | Yes | Yes | Yes | — | Yes | — | Yes | — |
4K×4 | Yes | Yes | Yes | — | Yes | — | Yes | — |
4K×5 | — | — | — | Yes | — | Yes | — | Yes |
2K×8 | Yes | Yes | Yes | — | Yes | — | Yes | — |
2K×10 | — | — | — | Yes | — | Yes | — | Yes |
1K×16 | Yes | Yes | Yes | — | Yes | — | Yes | — |
1K×20 | — | — | — | Yes | — | Yes | — | Yes |
Embedded Memory Clocking Modes
This section describes the clocking modes for the Intel® Arria® 10 memory blocks.
Clocking Modes for Each Memory Mode
Clocking Mode | Memory Mode | ||||
---|---|---|---|---|---|
Single-Port | Simple Dual-Port | True Dual-Port | ROM | FIFO | |
Single clock mode | Yes | Yes | Yes | Yes | Yes |
Read/write clock mode | — | Yes | — | — | Yes |
Input/output clock mode | Yes | Yes | Yes | Yes | — |
Independent clock mode | — | — | Yes | Yes | — |
Single Clock Mode
In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
Read/Write Clock Mode
In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.
Input/Output Clock Mode
In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode
In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.
Asynchronous Clears in Clocking Modes
In all clocking modes, asynchronous clears are available only for output latches and output registers. For the independent clock mode, this is applicable on both ports.
Output Read Data in Simultaneous Read/Write
If you perform a simultaneous read/write to the same address location using the read/write clock mode, the output read data is unknown. If you require the output read data to be a known value, use single-clock or input/output clock mode and select the appropriate read-during-write behavior in the IP core parameter editor.
Independent Clock Enables in Clocking Modes
Independent clock enables are supported in the following clocking modes:
- Read/write clock mode—supported for both the read and write clocks.
- Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
Parity Bit in Embedded Memory Blocks
The following describes the parity bit support for M20K blocks:
- The parity bit is the fifth bit associated with each 4 data bits in data widths of 5, 10, 20, and 40 (bits 4, 9, 14, 19, 24, 29, 34, and 39).
- In non-parity data widths, the parity bits are skipped during read or write operations.
- Parity function is not performed on the parity bit.
Byte Enable in Embedded Memory Blocks
The embedded memory blocks support byte enable controls:
- The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
- The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
- The byte enable registers do not have a clear port.
- If you are using parity bits, on the M20K blocks, the byte enable function controls 8 data bits and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
- The LSB of the byteena signal corresponds to the LSB of the data bus.
- The byte enable signals are active high.
Byte Enable Controls in Memory Blocks
byteena[1:0] | Data Bits Written | |
---|---|---|
11 (default) | [19:10] | [9:0] |
10 | [19:10] | — |
01 | — | [9:0] |
byteena[3:0] | Data Bits Written | |||
---|---|---|---|---|
1111 (default) | [39:30] | [29:20] | [19:10] | [9:0] |
1000 | [39:30] | — | — | — |
0100 | — | [29:20] | — | — |
0010 | — | — | [19:10] | — |
0001 | — | — | — | [9:0] |
Data Byte Output
In M20K blocks or MLABs, when you set a byte-enable bit to 0, the embedded memory IP sets the corresponding data byte output to a “don't care” value. You must ensure that the option Get X's for write masked bytes instead of old data when byte enable is always selected.
RAM Blocks Operations
Memory Blocks Packed Mode Support
The M20K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The Intel® Quartus® Prime software automatically implements packed mode where appropriate by placing the physical RAM block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM blocks. The size of each independent single-port RAM must not exceed half of the target block size.
Memory Blocks Address Clock Enable Support
The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).
Memory Blocks Asynchronous Clear
The M20K memory blocks support asynchronous clear on output latches and output registers. If your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear.
The clear is an asynchronous signal and it is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the clear is asserted, the outputs are cleared and stay cleared until the next read cycle.
Memory Blocks Error Correction Code Support
ECC allows you to detect and correct data errors at the output of the memory. ECC can perform single-error correction, double-adjacent-error correction, and triple-adjacent-error detection in a 32-bit word. However, ECC cannot detect four or more errors.
The M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode:
- The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged. However, you can enable optional ECC pipeline registers before the output decoder to achieve higher performance compared to non-pipeline ECC mode at the expense of one cycle of latency.
- The M20K ECC status is communicated with two ECC status flag signals—e (error) and ue (uncorrectable error). The status flags are part of the regular output from the memory block. When ECC is engaged, you cannot access two of the parity bits because the ECC status flag replaces them.
Error Correction Code Truth Table
e (error) eccstatus[1] |
ue (uncorrectable error) eccstatus[0] |
Status |
---|---|---|
0 | 0 | No error. |
0 | 1 | Illegal. |
1 | 0 | A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated. |
1 | 1 | An uncorrectable error occurred and uncorrectable data appears at the outputs. |
If you engage ECC:
- You cannot use the byte enable feature.
- Read-during-write old data mode is not supported.
Embedded Memory Blocks in Intel Arria 10 Devices Revision History
Date | Version | Changes |
---|---|---|
December 2017 | 2017.12.15 |
|
March 2017 | 2017.03.15 |
|
October 2016 | 2016.10.31 |
|
December 2015 | 2015.12.14 |
|
November 2015 | 2015.11.02 |
|
June 2015 | 2015.06.15 | Updated links. |
May 2015 | 2015.05.04 |
|
August 2014 | 2014.08.18 |
|
December 2013 | 2013.12.02 | Initial release. |
Variable Precision DSP Blocks in Intel Arria 10 Devices
This chapter describes how the variable-precision digital signal processing (DSP) blocks in Intel® Arria® 10 devices are optimized to support higher bit precision in high-performance DSP applications.
Supported Operational Modes in Intel Arria 10 Devices
Variable-Precision DSP Block Resource | Operation Mode | Supported Operation Instance | Pre-Adder Support | Coefficient Support | Input Cascade Support | Chainin Support | Chainout Support |
---|---|---|---|---|---|---|---|
1 variable precision DSP block | Fixed-point independent 18 x 19 multiplication | 2 | Yes | Yes | Yes 2 | No | No |
Fixed-point independent 27 x 27 multiplication | 1 | Yes | Yes | Yes 3 | Yes | Yes | |
Fixed-point two 18 x 19 multiplier adder mode | 1 | Yes | Yes | Yes2 | Yes | Yes | |
Fixed-point 18 x 18 multiplier adder summed with 36-bit input | 1 | No | No | No | Yes | Yes | |
Fixed-point 18 x 19 systolic mode | 1 | Yes | Yes | Yes2 | Yes | Yes | |
1 variable precision DSP block | Floating-point multiplication mode | 1 | No | No | No | No | Yes |
Floating-point adder or subtract mode | 1 | No | No | No | No | Yes | |
Floating-point multiplier adder or subtract mode | 1 | No | No | No | Yes | Yes | |
Floating-point multiplier accumulate mode | 1 | No | No | No | No | Yes | |
Floating-point vector one mode | 1 | No | No | No | Yes | Yes | |
Floating-point vector two mode | 1 | No | No | No | Yes | Yes | |
2 Variable precision DSP blocks | Complex 18x19 multiplication | 1 | No | No | Yes | No | No |
Variable-Precision DSP Block Resource | Operation Mode | Dynamic ACCUMULATE | Dynamic LOADCONST | Dynamic SUB | Dynamic NEGATE |
---|---|---|---|---|---|
1 variable precision DSP block | Fixed-point independent 18 x 19 multiplication | No | No | No | No |
Fixed-point independent 27 x 27 multiplication | Yes | Yes | No | Yes | |
Fixed-point two 18 x 19 multiplier adder mode | Yes | Yes | Yes | Yes | |
Fixed-point 18 x 18 multiplier adder summed with 36-bit input | Yes | Yes | Yes | Yes | |
Fixed-point 18 x 19 systolic mode | Yes | Yes | Yes | Yes | |
Floating-point multiplication mode | No | No | No | No | |
Floating-point adder or subtract mode | No | No | No | No | |
Floating-point multiplier adder or subtract mode | No | No | No | No | |
Floating-point multiplier accumulate mode | Yes | No | No | No | |
Floating-point vector one mode | No | No | No | No | |
Floating-point vector two mode | No | No | No | No | |
2 variable precision DSP blocks | Complex 18 x 19 multiplication | No | No | No | No |
Features
The Intel® Arria® 10 variable precision DSP blocks support fixed-point arithmetic and floating-point arithmetic.
Features for fixed-point arithmetic:
- High-performance, power-optimized, and fully registered multiplication operations
- 18-bit and 27-bit word lengths
- Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
- Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
- Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
- Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
- Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
- Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
- 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
- Biased rounding support
Features for floating-point arithmetic:
- A completely hardened architecture that supports multiplication, addition, subtraction, multiply-add, and multiply-subtract
- Multiplication with accumulation capability and a dynamic accumulator reset control
- Multiplication with cascade summation capability
- Multiplication with cascade subtraction capability
- Complex multiplication
- Direct vector dot product
- Systolic FIR filter
Resources
Variant | Product Line |
Variable-precision DSP Block |
Independent Input and Output Multiplications Operator |
18 x 19 Multiplier Adder Sum Mode |
18 x 18 Multiplier Adder Summed with 36 bit Input |
|
---|---|---|---|---|---|---|
18 x 19 Multiplier |
27 x 27 Multiplier |
|||||
A Intel® Arria® 10 GX | GX 160 | 156 | 312 | 156 | 156 | 156 |
GX 220 | 192 | 384 | 192 | 192 | 192 | |
GX 270 | 830 | 1,660 | 830 | 830 | 830 | |
GX 320 | 984 | 1,968 | 984 | 984 | 984 | |
GX 480 | 1,368 | 2,736 | 1,368 | 1,368 | 1,368 | |
GX 570 | 1,523 | 3,046 | 1,523 | 1,523 | 1,523 | |
GX 660 | 1,687 | 3,374 | 1,687 | 1,687 | 1,687 | |
GX 900 | 1,518 | 3,036 | 1,518 | 1,518 | 1,518 | |
GX 1150 | 1,518 | 3,036 | 1,518 | 1,518 | 1,518 | |
Intel® Arria® 10 GT | GT 900 | 1,518 | 3,036 | 1,518 | 1,518 | 1,518 |
GT 1150 | 1,518 | 3,036 | 1,518 | 1,518 | 1,518 | |
Intel® Arria® 10 SX | SX 160 | 156 | 312 | 156 | 156 | 156 |
SX 220 | 192 | 384 | 192 | 192 | 192 | |
SX 270 | 830 | 1,660 | 830 | 830 | 830 | |
SX 320 | 984 | 1,968 | 984 | 984 | 984 | |
SX 480 | 1,368 | 2,736 | 1,368 | 1,368 | 1,368 | |
SX 570 | 1,523 | 3,046 | 1,523 | 1,523 | 1,523 | |
SX 660 | 1,687 | 3,374 | 1,687 | 1,687 | 1,687 |
Variant | Product Line |
Variable-precision DSP Block |
Single Precision Floating-Point Multiplication Mode | Single-Precision Floating-Point Adder Mode | Single-Precision Floating-Point Multiply Accumulate Mode |
Peak Giga Floating-Point Operations per Second (GFLOPs) |
---|---|---|---|---|---|---|
Intel® Arria® 10 GX | GX 160 | 156 | 156 | 156 | 156 | 140 |
GX 220 | 192 | 192 | 192 | 192 | 173 | |
GX 270 | 830 | 830 | 830 | 830 | 747 | |
GX 320 | 984 | 984 | 984 | 984 | 886 | |
GX 480 | 1,369 | 1,368 | 1,368 | 1,368 | 1,231 | |
GX 570 | 1,523 | 1,523 | 1,523 | 1,523 | 1,371 | |
GX 660 | 1,687 | 1,687 | 1,687 | 1,687 | 1,518 | |
GX 900 | 1,518 | 1,518 | 1,518 | 1,518 | 1,366 | |
GX 1150 | 1,518 | 1,518 | 1,518 | 1,518 | 1,366 | |
Intel® Arria® 10 GT | GT 900 | 1,518 | 1,518 | 1,518 | 1,518 | 1,366 |
GT 1150 | 1,518 | 1,518 | 1,518 | 1,518 | 1,366 | |
Intel® Arria® 10 SX | SX 160 | 156 | 156 | 156 | 156 | 140 |
SX 220 | 192 | 192 | 192 | 192 | 173 | |
SX 270 | 830 | 830 | 830 | 830 | 747 | |
SX 320 | 984 | 984 | 984 | 984 | 886 | |
SX 480 | 1,369 | 1,368 | 1,368 | 1,368 | 1,231 | |
SX 570 | 1,523 | 1,523 | 1,523 | 1,523 | 1,371 | |
SX 660 | 1,687 | 1,687 | 1,687 | 1,687 | 1,518 |
Design Considerations
You should consider the following elements in your design:
DSP Implementation | Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|---|
Design elements |
|
|
Operational Mode | Available Design Templates |
---|---|
18 x 18 Independent Multiplier Mode | Single Multiplier with Preadder and Coefficient |
27 x 27 Independent Multiplier Mode |
|
Multiplier Adder Sum Mode |
|
18 x 19 Multiplication Summed with 36-Bit Input Mode |
|
18-bit Systolic FIR Mode |
|
- In Intel® Quartus® Prime software, open a new Verilog HDL or VHDL file.
- From Edit tab, click Insert Template.
- From the Insert Template window prompt, you may select Verilog HDL or VHDL depending on your preferred design language.
- Click Full Designs to expand the options.
- From the options, click Arithmetic > DSP Features > > DSP Features for 20-nm Device.
- Choose the design template that match your system requirement and click Insert to append the design template to a new .v or .vhd file.
Operational Modes
The Intel® Quartus® Prime software includes IP cores that you can use to control the operation mode of the multipliers. After entering the parameter settings with the IP Catalog, the Intel® Quartus® Prime software automatically configures the variable precision DSP block.
Variable-precision DSP block can also be implemented using DSP Builder for Intel® FPGAs and OpenCL™.
Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|
Intel provides two methods for implementing various modes of the Intel® Arria® 10 variable precision DSP block in a design—using the Intel® Quartus® Prime DSP IP core and HDL inferring. The following
Intel®
Quartus® Prime IP cores are supported
for the
Intel®
Arria® 10 variable precision DSP
blocks in the fixed-point arithmetic implementation:
|
Intel provides one
method for implementing various modes of the
Intel®
Arria® 10 variable precision DSP block in a
design—using the
Intel®
Quartus® Prime DSP IP
core. The following
Intel®
Quartus® Prime IP cores are supported for the
Intel®
Arria® 10 variable precision DSP blocks in the
floating-point arithmetic implementation:
|
Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic
When you enable input register for the pre-adder feature, these input registers must have the same clock setting.
The input cascade support is only available for 18-bit mode when you enable the pre-adder feature.
In both 18-bit and 27-bit modes, you can use the coefficient feature and pre-adder feature independently.
When internal coefficient feature is enabled in 18-bit modes, you must enable both top and bottom coefficient.
When pre-adder feature is enabled in 18-bit modes, you must enable both top and bottom pre-adder.
Accumulator for Fixed-Point Arithmetic
The accumulator in the Intel® Arria® 10 devices supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator.
Chainout Adder
Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|
You can use the output chaining path to add results from another DSP block. |
You can use the output chaining path to add results from another DSP block. Support for certain operation modes:
|
Block Architecture
The Intel® Arria® 10 variable precision DSP block consists of the following elements:
DSP Implementation | Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|---|
Block architecture |
|
|
If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both systolic registers are bypassed.
Input Register Bank
Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|
|
|
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable precision DSP block:
- CLK[2..0]
- ENA[2..0]
- ACLR[0]
In fixed-point arithmetic 18 x 19 mode, you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features.
The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in fixed-point arithmetic 18 x 19 mode and dataa_y0 only in fixed-point arithmetic 27 x 27 mode, from the general routing or cascade chain.
Two Sets of Delay Registers for Fixed-Point Arithmetic
The two delay registers along with the input cascade chain that can be used in fixed-point arithmetic 18 x 19 mode are the top delay registers and bottom delay registers. Delay registers are not supported in 18 × 19 multiplication summed with 36-bit input mode and 27 × 27 mode.
Pipeline Register
Pipeline register is used to get the maximum Fmax performance. Pipeline register can be bypassed if high Fmax is not needed.
- CLK[2..0]
- ENA[2..0]
- ACLR[1]
- Bypass all latency layers of pipeline registers
- Use either one latency layers of pipeline registers
- Use both latency layers of pipeline registers
Pre-Adder for Fixed-Point Arithmetic
Each variable precision DSP block has two 19-bit pre-adders. You can configure these pre-adders in the following configurations:
- Two independent 19-bit pre-adders
- One 27-bit pre-adder
The pre-adder supports both addition and subtraction in the following input configurations:
- 18-bit (signed or unsigned) addition or subtraction for 18 x 19 mode
- 26-bit addition or subtraction for 27 x 27 mode
When both pre-adders within the same DSP block are used, they must share the same operation type (either addition or subtraction).
Internal Coefficient for Fixed-Point Arithmetic
The Intel® Arria® 10 variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient.
The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and 27-bit modes. When you enable the internal coefficient feature, COEFSELA/COEFSELB are used to control the selection of the coefficient multiplexer.
Multipliers
A single variable precision DSP block can perform many multiplications in parallel, depending on the data width of the multiplier and implementation.
There are two multipliers per variable precision DSP block. You can configure these two multipliers in several operational modes:
Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|
|
One floating-point arithmetic single precision multiplier |
Adder
Depending on the operational mode, you can use the adder as follows:
- One 55-bit or 38-bit adder
- One floating-point arithmetic single precision adder
DSP Implementation | Addition Using Dynamic SUB Port | Subtraction Using Dynamic SUB Port |
---|---|---|
Fixed-Point Arithmetic | Yes | Yes |
Floating-Point Arithmetic | No | No |
Accumulator and Chainout Adder for Fixed-Point Arithmetic
The Intel® Arria® 10 variable precision DSP block supports a 64-bit accumulator and a 64-bit adder for fixed-point arithmetic.
The following signals can dynamically control the function of the accumulator:
- NEGATE
- LOADCONST
- ACCUMULATE
The accumulator supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator.
The accumulator and chainout adder features are not supported in two fixed-point arithmetic independent 18 x 19 modes.
Function | Description | NEGATE | LOADCONST | ACCUMULATE |
---|---|---|---|---|
Zeroing | Disables the accumulator. | 0 | 0 | 0 |
Preload | The result is always added to the preload value. Only one bit of the 64-bit preload value can be “1”. It can be used as rounding the DSP result to any position of the 64-bit result. | 0 | 1 | 0 |
Accumulation | Adds the current result to the previous accumulate result. | 0 | X | 1 |
Decimation + Accumulate | This function takes the current result, converts it into two’s complement, and adds it to the previous result. | 1 | X | 1 |
Decimation + Chainout Adder | This function takes the current result, converts it into two’s complement, and adds it to the output of previous DSP block. | 1 | 0 | 0 |
Systolic Registers for Fixed-Point Arithmetic
There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both systolic registers are bypassed.
The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit and 19-bit inputs of the upper multiplier, respectively.
The second set of systolic registers are used to delay the chainin input from the previous variable precision DSP block.
You must clock all the systolic registers with the same clock source as the output register. Output registers must be turned on.
Double Accumulation Register for Fixed-Point Arithmetic
The double accumulation register is an extra register in the feedback path of the accumulator. Enabling the double accumulation register causes an extra clock cycle delay in the feedback path of the accumulator.
This register has the same CLK, ENA, and ACLR settings as the output register bank.
By enabling this register, you can have two accumulator channels using the same number of variable precision DSP block. This is useful when processing interleaved complex data (I, Q).
Output Register Bank
The positive edge of the clock signal triggers the 74-bit bypassable output register bank and is cleared after power up.
The following variable precision DSP block signals control the output register per variable precision DSP block:
- CLK[2..0]
- ENA[2..0]
- ACLR[1]
Operational Mode Descriptions
This section describes how you can configure an Intel® Arria® 10 variable precision DSP block to efficiently support the fixed-point arithmetic and floating-point arithmetic operational modes.
Fixed-Point Arithmetic | Floating-Point Arithmetic |
---|---|
|
|
Operational Modes for Fixed-Point Arithmetic
Independent Multiplier Mode
In independent input and output multiplier mode, the variable precision DSP blocks perform individual multiplication operations for general purpose multipliers.
Configuration | Multipliers per Block |
---|---|
18 (signed) x 19 (signed) | 2 |
18 (unsigned) x 18 (unsigned) | 2 |
27 (signed or unsigned) x 27 (signed or unsigned) | 1 |
18 x 18 or 18 x 19 Independent Multiplier
In this figure, the variables are defined as follows:
- n = 19 and m = 37 for 18 x 19 operand
- n = 18 and m = 36 for 18 x 18 operand
27 x 27 Independent Multiplier
Independent Complex Multiplier
The Intel® Arria® 10 devices support the 18 x 19 complex multiplier mode using two fixed-point arithmetic multiplier adder sum mode.
The imaginary part [(a × d) + (b × c)] is implemented in the first variable-precision DSP block, while the real part [(a × c) - (b × d)] is implemented in the second variable-precision DSP block.
18 x 19 Complex Multiplier
Multiplier Adder Sum Mode
18 x 19 Multiplication Summed with 36-Bit Input Mode
Intel® Arria® 10 variable precision DSP blocks support one 18 x 19 multiplication summed to a 36-bit input.
Use the upper multiplier to provide the input for an 18 x 19 multiplication, while the bottom multiplier is bypassed. The datab_y1[17..0] and datab_y1[35..18] signals are concatenated to produce a 36-bit input.
Systolic FIR Mode
The basic structure of a FIR filter consists of a series of multiplications followed by an addition.
Depending on the number of taps and the input sizes, the delay through chaining a high number of adders can become quite large. To overcome the delay performance issue, the systolic form is used with additional delay elements placed per tap to increase the performance at the cost of increased latency.
Intel® Arria® 10 variable precision DSP blocks support the following systolic FIR structures:
- 18-bit
- 27-bit
In systolic FIR mode, the input of the multiplier can come from four different sets of sources:
- Two dynamic inputs
- One dynamic input and one coefficient input
- One coefficient input and one pre-adder output
- One dynamic input and one pre-adder output
Mapping Systolic Mode User View to Variable Precision Block Architecture View
The following figure shows that the user view of the systolic FIR filter (a) can be implemented using the Intel® Arria® 10 variable precision DSP blocks (d) by retiming the register and restructuring the adder. Register B can be retimed into systolic registers at the chainin, dataa_y0 and dataa_x0 input paths as shown in (b). The end result of the register retiming is shown in (c). The summation of two multiplier results by restructuring the inputs and location of the adder are added to the chainin input by the chainout adder as shown in (d).
18-Bit Systolic FIR Mode
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 7 bits of overhead when using an 18 x 19 operation mode, resulting 37-bit result. This allows a total sixteen 18 x 19 multipliers or eight Intel® Arria® 10 variable precision DSP blocks to be cascaded as systolic FIR structure.
27-Bit Systolic FIR Mode
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of eleven 27 x 27 multipliers or eleven Intel® Arria® 10 variable precision DSP blocks to be cascaded as systolic FIR structure.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block. Systolic registers are not required in this mode.
Operational Modes for Floating-Point Arithmetic
Single Floating-Point Arithmetic Functions
- Multiplication mode
- Adder or subtract mode
- Multiply accumulate mode
Multiplication Mode
This mode allows you to apply basic floating-point multiplication (y*z).
Adder or Subtract Mode
This mode allows you to apply basic floating-point addition (x+y) or basic floating-point subtraction (y-x).
Multiply Accumulate Mode
This mode performs floating-point multiplication followed by floating-point addition with the previous multiplication result { ((y*z) + acc) or ((y*z) - acc) }
Multiple Floating-Point Arithmetic Functions
- Multiply-add or multiply-subtract mode which uses single floating-point arithmetic DSP if the chainin parameter is turn off
- Vector one mode
- Vector two mode
- Direct vector dot product
- Complex multiplication
Multiply-Add or Multiply-Subtract Mode
This mode performs floating-point multiplication followed by floating-point addition or floating-point subtraction { ((y*z) + x) or ((y*z) - x) }. The chainin parameter allows you to enable a multiple-chain mode.
Vector One Mode
This mode performs floating-point multiplication followed by floating-point addition with the chainin input from the previous variable DSP Block. Input x is directly fed into chainout. (result = y*z + chainin , where chainout = x)
Vector Two Mode
This mode performs floating-point multiplication where the multiplication result is directly fed to chainout. The chainin input from the previous variable DSP Block is then added to input x as the output result. (result = x + chainin, where chainout = y*z)
Direct Vector Dot Product
- Multiply-add and subtract mode with chainin parameter turned on
- Vector one
- Vector two
Complex Multiplication
The Intel® Arria® 10 devices support the floating-point arithmetic single precision complex multiplier using four Intel® Arria® 10 variable-precision DSP blocks.
The imaginary part [(a × d) + (b × c)] is implemented in the first two variable-precision DSP blocks, while the real part [(a × c) - (b × d)] is implemented in the second variable-precision DSP block.
Variable Precision DSP Blocks in Intel Arria 10 Devices Revision History
Date | Version | Changes |
---|---|---|
March 2017 | 2017.03.15 |
|
December 2015 | 2015.11.14 |
|
November 2015 | 2015.11.02 |
|
May 2015 | 2015.05.04 |
|
January 2015 | 2015.01.23 |
|
August 2014 | 2014.08.18 |
|
December 2013 | 2013.12.02 | Initial release. |
Clock Networks and PLLs in Intel Arria 10 Devices
This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Intel® Arria® 10 devices. The Intel® Quartus® Prime software enables the PLLs and their features without external devices.
Clock Networks
The Intel® Arria® 10 devices contain the following clock networks that are organized into a hierarchical structure:
- Global clock (GCLK) networks
- Regional clock (RCLK) networks
- Periphery clock (PCLK)
networks
- Small periphery clock (SPCLK) networks
- Large periphery clock (LPCLK) networks
Clock Resources in Intel Arria 10 Devices
Clock Input Pins | ||
---|---|---|
Device | Number of Resources Available | Source of Clock Resource |
|
|
For high-speed
serial interface (HSSI):
REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T][p,n]
pins For I/O: CLK_[2,3][A..L]_[0,1][p,n] pins |
|
|
|
|
|
|
|
|
|
|
|
|
GCLK Networks | ||
Device | Number of Resources Available | Source of Clock Resource |
All | 32 |
|
RCLK Networks | ||
Device | Number of Resources Available | Source of Clock Resource |
|
8 |
|
|
12 | |
|
16 | |
SPCLK Networks | ||
Device | Number of Resources Available | Source of Clock Resource |
|
144 | For HSSI:
For I/O:
|
|
216 | |
|
288 | |
|
384 | |
LPCLK Networks | ||
Device | Number of Resources Available | Source of Clock Resource |
|
24 | For HSSI:
For I/O:
|
|
36 | |
|
48 | |
|
64 |
For more information about the clock input pins connections, refer to the pin connection guidelines.
Hierarchical Clock Networks
Intel® Arria® 10 devices cover 3 levels of clock networks hierarchy. The sequence of the hierarchy is as follows:
- GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks
- Section clock (SCLK)
- Row clocks
Each HSSI and I/O column contains clock drivers to drive down shared buses to the respective GCLK, RCLK, and PCLK clock networks.
Intel® Arria® 10 clock networks (GCLK, RCLK, and PCLK) are routed through SCLK before each clock is connected to the clock routing for each HSSI or I/O bank. The settings for SCLK are transparent. The Intel® Quartus® Prime software automatically routes the SCLK based on the GCLK, RCLK, and PCLK networks.
Each SCLK spine has a consistent height, matching that of HSSI and I/O banks. The number of SCLK spine in a device depends on the number of HSSI and I/O banks.
Intel® Arria® 10 devices provide a maximum of 33 SCLK networks in the SCLK spine region. The SCLK networks can drive six row clocks in each row clock region. The row clocks are the clock resources to the core functional blocks, PLLs, and I/O interfaces, and HSSI interfaces of the device. Six unique signals can be routed into each row clock region. The connectivity pattern of the multiplexers that drive each SCLK limits the clock sources to the SCLK spine region. Each SCLK can select the clock resources from GCLK, RCLK, LPCLK, or SPCLK lines.
The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or GCLK and RCLK feedback clock networks in each SCLK spine region. The GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks share the same SCLK routing resources. To ensure successful design fitting in the Intel® Quartus® Prime software, the total number of clock resources must not exceed the SCLK limits in each SCLK spine region.
Types of Clock Networks
Global Clock Networks
GCLK networks serve as low-skew clock sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP), embedded memory, and PLLs. Intel® Arria® 10 I/O elements (IOEs) and internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out control signals, such as synchronous or asynchronous clear and clock enable signals.
Intel® Arria® 10 devices provide GCLKs that can drive throughout the device. GCLKs cover every SCLK spine region in the device. Each GCLK is accessible through the direction as indicated in the Symbolic GCLK Networks diagram.
Regional Clock Networks
RCLK networks provide low clock insertion delay and skew for logic contained within a single RCLK region. The Intel® Arria® 10 IOEs and internal logic within a given region can also drive RCLKs to create internally-generated regional clocks and other high fan-out signals.
Intel® Arria® 10 devices provide RCLKs that can drive through the chip horizontally. RCLKs cover all the SCLK spine regions in the same row of the device. The top and bottom HSSI and I/O banks have RCLKs that cover 2 rows vertically. The other intermediate HSSI and I/O banks have RCLKs that cover 6 rows vertically. The following figure shows the RCLK network coverage.
Periphery Clock Networks
PCLK networks provide the lowest insertion delay and the same skew as RCLK networks.
Small Periphery Clock Networks
Each HSSI or I/O bank has 12 SPCLKs. SPCLKs cover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to each other in the same row.
Large Periphery Clock Networks
Each HSSI or I/O bank has 2 LPCLKs. LPCLKs have larger network coverage compared to SPCLKs. LPCLKs cover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to each other in the same row. Top and bottom HSSI and I/O banks have LPCLKs that cover 2 rows vertically. The other intermediate HSSI and I/O banks have LPCLKs that cover 4 rows vertically.
Clock Network Sources
This section describes the clock network sources that can drive the GCLK, RCLK, and PCLK networks.
Dedicated Clock Input Pins
The sources of dedicated clock input pins are as follows:
- fPLL— REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T][p,n] from HSSI column
- I/O PLL— CLK_[2,3][A..L]_[0,1][p,n] from I/O column
You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
The dedicated clock input pins can be either differential clocks or single-ended clocks for I/O PLL. When you use the dedicated clock input pins as single-ended clock inputs, only CLK_[2,3][A..L]_[0,1][p,n] pins have dedicated connections to the PLL. fPLLs only support differential clock inputs.
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL is not be able to fully compensate for the global or regional clock. Intel recommends using the dedicated clock input pins for optimal performance to drive the PLLs.
Internal Logic
You can drive each GCLK and RCLK network using core routing to enable internal logic to drive a high fan-out, low-skew signal.
DPA Outputs
Each DPA can drive the PCLK networks.
HSSI Clock Outputs
HSSI clock outputs can drive the GCLK, RCLK, and PCLK networks.
PLL Clock Outputs
The fPLL and I/O PLL clock outputs can drive all clock networks.
Clock Control Block
Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the following features:
- Clock source selection (dynamic selection available only for GCLKs)
- Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)
Pin Mapping in Intel Arria 10 Devices
Clock | Fed by |
---|---|
inclk[0] | PLL counters C0 and C2 from adjacent fPLLs. |
inclk[1] | PLL counters C1 and C3 from adjacent fPLLs. |
inclk[2] and inclk[3] | Any of the two dedicated clock pins on the same HSSI bank. |
Clock | Fed by |
---|---|
inclk[0] | CLK_[2,3][A..L]_0p or any counters from adjacent I/O PLLs. |
inclk[1] | CLK_[2,3][A..L]_0n or any counters from adjacent I/O PLLs. |
inclk[2] | CLK_[2,3][A..L]_1p or any counters from adjacent I/O PLLs. |
inclk[3] | CLK_[2,3][A..L]_1n or any counters from adjacent I/O PLLs. |
GCLK Control Block
You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.
When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
You can set the input clock sources and the clkena signals for the GCLK network multiplexers through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.
When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal.
RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Intel® Quartus® Prime software.
You can set the input clock sources and the clkena signals for the RCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.
PCLK Control Block
PCLK control block drives both SPCLK and LPCLK networks.
To drive the HSSI PCLK, select the HSSI output, fPLL output, or clock input pin.
To drive the I/O PCLK, select the DPA clock output, I/O PLL output, or clock input pin.
You can set the input clock sources and the clkena signals for the PCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.
Clock Power Down
You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.
When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the Intel® Quartus® Prime software.
The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the GCLK and RCLK networks. This feature is independent of the PLL and is applied directly on the clock network.
Clock Enable Signals
You cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK output drives the input of a PLL.
The clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when you are not using a PLL. You can also use the clkena signals to control the dedicated external clocks from the PLLs.
Intel® Arria® 10 devices have an additional metastability register that aids in asynchronous enable and disable of the GCLK and RCLK networks. You can optionally bypass this register in the Intel® Quartus® Prime software.
The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.
Intel Arria 10 PLLs
PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.
The Intel® Arria® 10 device family contains the following PLLs:
- fPLLs—can function as fractional PLLs or integer PLLs
- I/O PLLs—can only function as integer PLLs
The fPLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank contains two fPLLs. You can configure each fPLL independently in conventional integer mode or fractional mode. In fractional mode, the fPLL can operate with third-order delta-sigma modulation. Each fPLL has four C counter outputs and one L counter output.
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs. In some specific device package, you can use the I/O PLLs in the I/O banks that are not bonded out in your design. These I/O PLLs must take their reference clock source from the FPGA core or through a dedicated cascade connection from another I/O PLL in the same I/O column.
Intel® Arria® 10 devices have up to 32 fPLLs and 16 I/O PLLs in the largest densities. Intel® Arria® 10 PLLs have different core analog structure and features support.
Feature | Fractional PLL | I/O PLL |
---|---|---|
Integer mode | Yes | Yes |
Fractional mode | Yes | — |
C output counters | 4 | 9 |
M counter divide factors | 8 to 127 | 4 to 160 |
N counter divide factors | 1 to 32 | 1 to 80 |
C counter divide factors | 1 to 512 | 1 to 512 |
L counter divide factors | 1, 2, 4, 8 | — |
Dedicated external clock outputs | — | Yes |
Dedicated clock input pins | Yes | Yes |
External feedback input pin | — | Yes |
Spread-spectrum input clock tracking 4 | Yes | Yes |
Source synchronous compensation | — | Yes |
Direct compensation | Yes | Yes |
Normal compensation | — | Yes |
Zero-delay buffer compensation | — | Yes |
External feedback compensation | — | Yes |
LVDS compensation | — | Yes |
Feedback compensation bonding | Yes | — |
Voltage-controlled oscillator (VCO) output drives the DPA clock | — | Yes |
Phase shift resolution 5 | 72 ps | 78.125 ps |
Programmable duty cycle | Fixed 50% duty cycle | Yes |
Power down mode | Yes | Yes |
PLL Usage
fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clock frequencies. You can use the fPLLs as follows:
- Reduce the number of required oscillators on the board
- Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
- Compensate clock network delay
- Transmit clocking for transceivers
I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs as follows:
- Reduce the number of required oscillators on the board
- Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
- Simplify the design of external memory interfaces and high-speed LVDS interfaces
- Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
- Compensate clock network delay
- Zero delay buffering
PLL Architecture
PLL Control Signals
You can use the reset signal to control PLL operation and resynchronization, and use the locked signal to observe the status of the PLL.
Reset
The reset signal port of the IP core for each PLL is as follows:
- fPLL—pll_powerdown
- I/O PLL—reset
The reset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.
When the reset signal is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again, the PLL resynchronizes to its input clock source as it re-locks.
You must assert the reset signal every time the PLL loses lock to guarantee the correct phase relationship between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a loss-of-lock condition using the Intel® Quartus® Prime parameter editor.
You must include the reset signal if either of the following conditions is true:
- PLL reconfiguration or clock switchover is enabled in the design
- Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock condition
- If the input clock to the PLL is not toggling or is unstable when the FPGA transitions into user mode, reset the PLL after the input clock is stable and within specifications, even when the self-reset feature is enabled.
- If the PLL is not able to lock to the reference clock after reconfiguring the PLL or the external clock source, reset the PLL after the input clock is stable and within specifications, even when the self-reset feature is enabled.
- For fPLL, after device power-up, you must reset the fPLL when the fPLL power-up calibration process has completed (pll_cal_busy signal deasserts).
Locked
The locked signal port of the IP core for each PLL is as follows:
- fPLL—pll_locked
- I/O PLL—locked
The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.
Clock Feedback Modes
Clock feedback modes compensate for clock network delays to align the PLL clock input rising edge with the rising edge of the clock output. Select the appropriate type of compensation for the timing critical clock path in your design.
PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.
The default clock feedback mode is direct compensation mode.
fPLLs support the following clock feedback modes:
- Direct compensation
- Feedback compensation bonding
I/O PLLs support the following clock feedback modes:
- Direct compensation
- Normal compensation
- Source synchronous compensation
- LVDS compensation
- Zero delay buffer (ZDB) compensation
- External feedback (EFB) compensation
Clock Multiplication and Division
An Intel® Arria® 10 PLL output frequency is related to its input reference clock source by a scale factor of M/(N × C) in integer mode. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).
The Intel® Quartus® Prime software automatically chooses the appropriate scale factors according to the input frequency, multiplication, and division values entered into the Altera IOPLL IP core for I/O PLL and Arria 10 FPLL IP core for fPLL.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M. The M and N counters do not use duty-cycle control because the only purpose of these counters is to calculate frequency division.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C. For multiple C counter outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. For example, if the output frequencies required from one I/O PLL are 55 MHz and 100 MHz, the Intel® Quartus® Prime software sets the VCO frequency to 1.1 GHz (the least common multiple of 55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale counters, C, scale down the VCO frequency for each output port.
Post-Scale Counter, L
The fPLL has an additional post-scale counter, L. The L counter synthesizes the frequency from its clock source using the M/(N × L) scale factor. The L counter generates a differential clock pair (0 degree and 180 degree) and drives the HSSI clock network.
Delta-Sigma Modulator
The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the fPLL to operate in fractional mode. The DSM dynamically changes the M counter factor on a cycle-to-cycle basis. The different M counter factors allow the "average" M counter factor to be a non-integer.
Fractional Mode
In fractional mode, the M counter value equals to the sum of the M feedback factor and the fractional value. The fractional value is equal to K/232 , where K is an integer between 0 and (232 – 1).
Integer Mode
For a fPLL operating in integer mode, M is an integer value and DSM is disabled.
The I/O PLL can only operate in integer mode.
Programmable Phase Shift
The programmable phase shift feature allows both fPLLs and I/O PLLs to generate output clocks with a fixed phase offset.
The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift increment is 1/8 (for I/O PLL) or 1/4 (for fPLL) of the VCO period. For example, if an I/O PLL operates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.
The Intel® Quartus® Prime software automatically adjusts the VCO frequency according to the user-specified phase shift values entered into the IP core.
Programmable Duty Cycle
The programmable duty cycle feature allows I/O PLLs to generate clock outputs with a variable duty cycle. This feature is only supported by the I/O PLL post-scale counters, C. fPLLs do not support the programmable duty cycle feature and only have fixed 50% duty cycle.
The I/O PLL C counter value determines the precision of the duty cycle. The precision is 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle options from 5% to 90%. If the I/O PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%.
The Intel® Quartus® Prime software automatically adjusts the VCO frequency according to the required duty cycle that you enter in the Intel® FPGA IOPLL IP core parameter editor.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.
PLL Cascading
Intel® Arria® 10 devices support PLL-to-PLL cascading. You can only cascade a maximum of two PLLs. The cascaded PLLs must be adjacent PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.
If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting and the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of the source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies.
Intel® Arria® 10 devices only support I/O-PLL-to-I/O-PLL cascading via dedicated cascade path for core applications. In this mode, upstream I/O PLL and downstream I/O PLL must be located within the same I/O column.
Intel® Arria® 10 fPLL does not support PLL cascading mode for core applications.
Reference Clock Sources
There are three possible reference clock sources to the I/O PLL. The clock can come from a dedicated pin, a core clock network, or the dedicated cascade network.
Intel recommends providing the I/O PLL reference clock using a dedicated pin when possible. If you want to use a non-dedicated pin for the PLL reference clock, you have to explicitly promote the clock to a global signal in the Intel® Quartus® Prime software.
You can provide up to two reference clocks to the I/O PLL.
- Both reference clocks can come from dedicated pins.
- Only one reference clock can come from a core clock.
- Only one reference clock can come from a dedicated cascade network.
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns to the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user control signal, extswitch.
Intel® Arria® 10 PLLs support the following clock switchover modes:
- Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
- Manual clock switchover—Clock switchover is controlled using the extswitch signal. When the extswitch signal pulse stays low for at least three clock cycles for the inclk being switched to, the reference clock to the PLL is switched from inclk0 to inclk1, or vice-versa.
- Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the extswitch signal goes low, it overrides the automatic clock switchover function. As long as the extswitch signal is low, further switchover action is blocked.
Automatic Switchover
Intel® Arria® 10 PLLs support a fully configurable clock switchover capability.
When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design.
The clock switchover circuit sends out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad0 and clkbad1 signals indicate the status of the two clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal.
Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In this case, inclk1 becomes the reference clock for the PLL.
When using automatic clock switchover mode, the following requirements must be satisfied:
- Both clock inputs must be running when the FPGA is configured.
- The period of the two clock inputs can differ by no more than 20%.
The input clocks must meet the input jitter specifications to ensure proper operation of the status signals. Glitches in the input clock may be seen as a greater than 20% difference in frequency between the input clocks.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL may lose lock after the switchover is completed and needs time to relock.
Automatic Switchover with Manual Override
In automatic switchover with manual override mode, you can use the extswitch signal for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch between inputs of different frequencies.
For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the extswitch signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1) frequencies with a frequency difference of more than 100% (2×).
This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation.
You must choose the backup clock frequency and set the M, N, C, L, and K counters so that the VCO operates within the recommended operating frequency range. The Altera IOPLL (for I/O PLL) and Arria 10 FPLL (for fPLL) parameter editors notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.
In automatic override with manual switchover mode, the activeclock signal inverts after the extswitch signal transitions from logic high to logic low. Since both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the switchover circuit is negative-edge sensitive, the rising edge of the extswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the extswitch signal goes low again, the process repeats.
The extswitch signal and automatic switch work only if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.
Manual Clock Switchover
In manual clock switchover mode, the extswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the extswitch signal transitions from logic high to logic low, and being held low for at least three inclk cycles for the inclk being switched to.
You must bring the extswitch signal back high again to perform another switchover event. If you do not require another switchover event, you can leave the extswitch signal in a logic low state after the initial switch.
Pulsing the extswitch signal low for at least three inclk cycles for the inclk being switched to performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the extswitch signal minimum low time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
You can delay the clock switchover action by specifying the switchover delay in the Altera IOPLL (for I/O PLL) and Arria 10 FPLL (for fPLL) IP cores. When you specify the switchover delay, the extswitch signal must be held low for at least three inclk cycles for the inclk being switched to plus the number of the delay cycles that has been specified to initiate a clock switchover.
Guidelines
When implementing clock switchover in Intel® Arria® 10 PLLs, use the following guidelines:
- Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each other. Failing to meet this requirement causes the clkbad0 and clkbad1 signals to not function properly.
- When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2×). However, differences in frequency, phase, or both, of the two clock sources is likely to cause the PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the input and output clocks.
- Both inclk0 and inclk1 must be running when the extswitch signal goes low to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
- Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time.
- After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The time it takes for the PLL to relock depends on the PLL configuration.
- The phase relationship between the input clock to the PLL and the output clock from the PLL is important in your design. Assert the reset signal for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL.
- The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.
PLL Reconfiguration and Dynamic Phase Shift
fPLLs and I/O PLLs support PLL reconfiguration and dynamic phase shift with the following features:
- PLL reconfiguration—Reconfigure the M, N, and C counters. Able to reconfigure the fractional settings (for fPLL).
- Dynamic phase shift—Perform positive or negative phase shift. fPLLs support only single phase step in one dynamic phase shift operation, where each phase step is equal to 1/4 of the VCO period. I/O PLLs support multiple phase steps in one dynamic phase shift operation, where each phase step is equal to 1/8 of the VCO period.
Clock Networks and PLLs in Intel Arria 10 Devices Revision History
Date | Version | Changes |
---|---|---|
December 2017 | 2017.12.15 |
|
May 2017 | 2017.05.08 |
|
March 2017 | 2017.03.15 | Rebranded as Intel. |
October 2016 | 2016.10.31 |
|
May 2016 | 2016.05.02 |
|
November 2015 | 2015.11.02 |
|
May 2015 | 2015.05.04 |
|
January 2015 | 2015.01.23 |
|
August 2014 | 2014.08.18 |
|
December 2013 | 2013.12.02 | Initial release. |
I/O and High Speed I/O in Intel Arria 10 Devices
The Intel® Arria® 10 I/Os support the following features:
- Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
- Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, SSTL, and POD I/O standards
- Serializer/deserializer (SERDES)
- Programmable output current strength
- Programmable slew rate
- Programmable bus-hold
- Programmable weak pull-up resistor
- Programmable pre-emphasis for DDR4 and LVDS standards
- Programmable I/O delay
- Programmable differential output voltage (VOD)
- Open-drain output
- On-chip series termination (RS OCT) with and without calibration
- On-chip parallel termination (RT OCT)
- On-chip differential termination (RD OCT)
- HSTL and SSTL input buffer with dynamic power down
- Dynamic on-chip parallel termination for all I/O banks
- Internally generated VREF with DDR4 calibration
I/O and Differential I/O Buffers in Intel Arria 10 Devices
The general purpose I/Os (GPIOs) consist of LVDS I/O and 3 V I/O banks:
- LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, if you use 30 channels of the available 72 channels as transmitters, you can use the remaining 42 channels as receivers.
-
3 V I/O bank—supports single-ended and differential
SSTL, HSTL, and HSUL I/O standards up to 3
V. Single-ended I/O within this I/O bank
support all programmable I/O element (IOE) features except:
- Programmable pre-emphasis
- RD on-chip termination (OCT)
- Calibrated RS and RT OCT
- Internal VREF generation
Intel® Arria® 10 devices support LVDS on all LVDS I/O banks:
- All LVDS I/O banks support true LVDS input with RD OCT and true LVDS output buffer.
- The devices do not support emulated LVDS channels.
- The devices support both single-ended and differential I/O reference clock for the I/O PLL that drives the SERDES.
I/O Standards and Voltage Levels in Intel Arria 10 Devices
I/O Standards Support for FPGA I/O in Intel Arria 10 Devices
I/O Standard | Device Variant Support | I/O Buffer Type Support | Application | Standard Support | |
---|---|---|---|---|---|
LVDS I/O | 3V I/O | ||||
3.0 V LVTTL/3.0 V LVCMOS | Devices with 3 V I/O banks only. Refer to related information. | No | Yes | General purpose | JESD8-B |
2.5 V LVCMOS | Devices with 3 V I/O banks only. Refer to related information. | No | Yes | General purpose | JESD8-5 |
1.8 V LVCMOS | All | Yes | Yes | General purpose | JESD8-7 |
1.5 V LVCMOS | All | Yes | Yes | General purpose | JESD8-11 |
1.2 V LVCMOS | All | Yes | Yes | General purpose | JESD8-12 |
SSTL-18 Class I and Class II | All | Yes | Yes | DDR2 | JESD8-15 |
SSTL-15 Class I and Class II | All | Yes | Yes | DDR3 | — |
SSTL-15 | All | Yes | Yes | DDR3 | JESD79-3D |
SSTL-135, SSTL-135 Class I and Class II | All | Yes | Yes | DDR3L | — |
SSTL-125, SSTL-125 Class I and Class II | All | Yes | Yes | DDR3U | — |
SSTL-12, SSTL-12 Class I and Class II | All | Yes | No | RLDRAM 3 | — |
POD12 | All | Yes | No | DDR4 | JESD8-24 |
1.8 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
1.5 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
1.2 V HSTL Class I and Class II | All | Yes | Yes | General purpose | JESD8-16A |
HSUL-12 | All | Yes | Yes | LPDDR2 | — |
Differential SSTL-18 Class I and Class II | All | Yes | Yes | DDR2 | JESD8-15 |
Differential SSTL-15 Class I and Class II | All | Yes | Yes | DDR3 | — |
Differential SSTL-15 | All | Yes | Yes | DDR3 | JESD79-3D |
Differential SSTL-135, SSTL-135 Class I and Class II | All | Yes | Yes | DDR3L | — |
Differential SSTL-125, SSTL-125 Class I and Class II | All | Yes | Yes | DDR3U | — |
Differential SSTL-12, SSTL-12 Class I and Class II | All | Yes | No | RLDRAM 3 | — |
Differential POD12 | All | Yes | No | DDR4 | JESD8-24 |
Differential 1.8 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
Differential 1.5 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
Differential 1.2 V HSTL Class I and Class II | All | Yes | Yes | General purpose | JESD8-16A |
Differential HSUL-12 | All | Yes | Yes | LPDDR2 | — |
LVDS | All | Yes | No | SGMII, SFI, and SPI | ANSI/TIA/EIA-644 |
Mini-LVDS | All | Yes | No | SGMII, SFI, and SPI | — |
RSDS | All | Yes | No | SGMII, SFI, and SPI | — |
LVPECL | All | Yes | No | SGMII, SFI, and SPI | — |
I/O Standards Support for HPS I/O in Intel Arria 10 Devices
I/O Standard | Application | Standard Support |
---|---|---|
3.0 V LVTTL/3.0 V LVCMOS | General purpose | JESD8-B |
2.5 V LVCMOS | General purpose | JESD8-5 |
1.8 V LVCMOS | General purpose | JESD8-7 |
I/O Standards Voltage Levels in Intel Arria 10 Devices
- The I/O buffers are powered by VCC, VCCPT and VCCIO.
- Each I/O bank has its own VCCIO supply and supports only one VCCIO voltage.
- In all I/O banks, you can use any of the listed VCCIO voltages except 2.5 V and 3.0 V.
- The 2.5 V and 3.0 V VCCIO voltages are supported only on the 3 V I/O banks.
- For the maximum and minimum input voltages allowed, refer to the device datasheet.
I/O Standard | VCCIO(V) |
VCCPT(V) (Pre-Driver Voltage) |
VREF(V) (Input Ref Voltage) |
VTT(V) (Board Termination Voltage) |
|
---|---|---|---|---|---|
Input6 | Output | ||||
3.0 V LVTTL/3.0 V LVCMOS | 3.0/2.5 | 3.0 | 1.8 | — | — |
2.5 V LVCMOS | 3.0/2.5 | 2.5 | 1.8 | — | — |
1.8 V LVCMOS | 1.8 | 1.8 | 1.8 | — | — |
1.5 V LVCMOS | 1.5 | 1.5 | 1.8 | — | — |
1.2 V LVCMOS | 1.2 | 1.2 | 1.8 | — | — |
SSTL-18 Class I and Class II | VCCPT | 1.8 | 1.8 | 0.9 | 0.9 |
SSTL-15 Class I and Class II | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
SSTL-15 | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
SSTL-135, SSTL-135 Class I and Class II | VCCPT | 1.35 | 1.8 | 0.675 | — |
SSTL-125, SSTL-125 Class I and Class II | VCCPT | 1.25 | 1.8 | 0.625 | — |
SSTL-12, SSTL-12 Class I and Class II | VCCPT | 1.2 | 1.8 | 0.6 | — |
POD12 | VCCPT | 1.2 | 1.8 | 0.84 | 1.2 |
1.8 V HSTL Class I and Class II | VCCPT | 1.8 | 1.8 | 0.9 | 0.9 |
1.5 V HSTL Class I and Class II | VCCPT | 1.5 | 1.8 | 0.75 | 0.75 |
1.2 V HSTL Class I and Class II | VCCPT | 1.2 | 1.8 | 0.6 | 0.6 |
HSUL-12 | VCCPT | 1.2 | 1.8 | 0.6 | — |
Differential SSTL-18 Class I and Class II | VCCPT | 1.8 | 1.8 | — | 0.9 |
Differential SSTL-15 Class I and Class II | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential SSTL-15 | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential SSTL-135, SSTL-135 Class I and Class II | VCCPT | 1.35 | 1.8 | — | 0.675 |
Differential SSTL-125, SSTL-125 Class I and Class II | VCCPT | 1.25 | 1.8 | — | 0.625 |
Differential SSTL-12, SSTL-12 Class I and Class II | VCCPT | 1.2 | 1.8 | — | 0.6 |
Differential POD12 | VCCPT | 1.2 | 1.8 | — | 1.2 |
Differential 1.8 V HSTL Class I and Class II | VCCPT | 1.8 | 1.8 | — | 0.9 |
Differential 1.5 V HSTL Class I and Class II | VCCPT | 1.5 | 1.8 | — | 0.75 |
Differential 1.2 V HSTL Class I and Class II | VCCPT | 1.2 | 1.8 | — | 0.6 |
Differential HSUL-12 | VCCPT | 1.2 | 1.8 | — | — |
LVDS | VCCPT | 1.8 | 1.8 | — | — |
Mini-LVDS | VCCPT | 1.8 | 1.8 | — | — |
RSDS | VCCPT | 1.8 | 1.8 | — | — |
LVPECL (Differential clock input only) | VCCPT | — | 1.8 | — | — |
Intel FPGA I/O IP Cores for Intel Arria 10 Devices
- Intel® FPGA GPIO—supports operations of the GPIO components.
- Intel® FPGA LVDS SERDES—supports operations of the high-speed source-synchronous SERDES.
- Intel FPGA OCT—supports the OCT calibration block.
- Intel FPGA PHYlite for Parallel Interfaces —supports dynamic OCT and I/O delays for strobe-based capture I/O elements. This IP core can also be used for generic source synchronous interfaces using single ended I/O.
I/O Resources in Intel Arria 10 Devices
GPIO Banks, SERDES, and DPA Locations in Intel Arria 10 Devices
The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.
For more details about the I/O banks available in each device package, refer to the related information.
GPIO Buffers and LVDS Channels in Intel Arria 10 Devices
FPGA I/O Resources in Intel Arria 10 GX Packages
Product Line | Package | GPIO | LVDS Channels | |||
---|---|---|---|---|---|---|
Code | Type | 3 V I/O | LVDS I/O | Total | ||
GX 160 | U19 | 484-pin UBGA | 48 | 148 | 196 | 74 |
F27 | 672-pin FBGA | 48 | 192 | 240 | 96 | |
F29 | 780-pin FBGA | 48 | 240 | 288 | 120 | |
GX 220 | U19 | 484-pin UBGA | 48 | 148 | 196 | 74 |
F27 | 672-pin FBGA | 48 | 192 | 240 | 96 | |
F29 | 780-pin FBGA | 48 | 240 | 288 | 120 | |
GX 270 | F27 | 672-pin FBGA | 48 | 192 | 240 | 96 |
F29 | 780-pin FBGA | 48 | 312 | 360 | 156 | |
F34 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
F35 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
GX 320 | F27 | 672-pin FBGA | 48 | 192 | 240 | 96 |
F29 | 780-pin FBGA | 48 | 312 | 360 | 156 | |
F34 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
F35 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
GX 480 | F29 | 780-pin FBGA | 48 | 312 | 360 | 156 |
F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 | |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
GX 570 | F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
NF40 | 1,517-pin FBGA | 48 | 540 | 588 | 270 | |
KF40 | 1,517-pin FBGA | 96 | 600 | 696 | 300 | |
GX 660 | F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
NF40 | 1,517-pin FBGA | 48 | 540 | 588 | 270 | |
KF40 | 1,517-pin FBGA | 96 | 600 | 696 | 300 | |
GX 900 | F34 | 1,152-pin FBGA | 0 | 504 | 504 | 252 |
NF40 | 1,517-pin FBGA | 0 | 600 | 600 | 300 | |
RF40 | 1,517-pin FBGA | 0 | 342 | 342 | 154 | |
NF45 | 1,932-pin FBGA | 0 | 768 | 768 | 384 | |
SF45 | 1,932-pin FBGA | 0 | 624 | 624 | 312 | |
UF45 | 1,932-pin FBGA | 0 | 480 | 480 | 240 | |
GX 1150 | F34 | 1,152-pin FBGA | 0 | 504 | 504 | 252 |
NF40 | 1,517-pin FBGA | 0 | 600 | 600 | 300 | |
RF40 | 1,517-pin FBGA | 0 | 342 | 342 | 154 | |
NF45 | 1,932-pin FBGA | 0 | 768 | 768 | 384 | |
SF45 | 1,932-pin FBGA | 0 | 624 | 624 | 312 | |
UF45 | 1,932-pin FBGA | 0 | 480 | 480 | 240 |
FPGA I/O Resources in Intel Arria 10 GT Packages
Product Line | Package | GPIO Buffers | LVDS Channels | |||
---|---|---|---|---|---|---|
Code | Type | 3 V I/O | LVDS I/O | Total | ||
GT 900 | SF45 | 1,932-pin FBGA | 0 | 624 | 624 | 312 |
GT 1150 | SF45 | 1,932-pin FBGA | 0 | 624 | 624 | 312 |
FPGA I/O Resources in Intel Arria 10 SX Packages
Product Line | Package | GPIO Buffers | LVDS Channels | |||
---|---|---|---|---|---|---|
Code | Type | 3 V I/O | LVDS I/O | Total | ||
SX 160 | U19 | 484-pin UBGA | 48 | 148 | 196 | 74 |
F27 | 672-pin FBGA | 48 | 192 | 240 | 96 | |
F29 | 780-pin FBGA | 48 | 240 | 288 | 120 | |
SX 220 | U19 | 484-pin UBGA | 48 | 148 | 196 | 74 |
F27 | 672-pin FBGA | 48 | 192 | 240 | 96 | |
F29 | 780-pin FBGA | 48 | 240 | 288 | 120 | |
SX 270 | F27 | 672-pin FBGA | 48 | 192 | 240 | 96 |
F29 | 780-pin FBGA | 48 | 312 | 360 | 156 | |
F34 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
F35 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
SX 320 | F27 | 672-pin FBGA | 48 | 192 | 240 | 96 |
F29 | 780-pin FBGA | 48 | 312 | 360 | 156 | |
F34 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
F35 | 1,152-pin FBGA | 48 | 336 | 384 | 168 | |
SX 480 | F29 | 780-pin FBGA | 48 | 312 | 360 | 156 |
F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 | |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
SX 570 | F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
NF40 | 1,517-pin FBGA | 48 | 540 | 588 | 270 | |
KF40 | 1,517-pin FBGA | 96 | 600 | 696 | 300 | |
SX 660 | F34 | 1,152-pin FBGA | 48 | 444 | 492 | 222 |
F35 | 1,152-pin FBGA | 48 | 348 | 396 | 174 | |
NF40 | 1,517-pin FBGA | 48 | 540 | 588 | 270 | |
KF40 | 1,517-pin FBGA | 96 | 600 | 696 | 300 |
I/O Banks Groups in Intel Arria 10 Devices
The I/O pins in Intel® Arria® 10 devices are arranged in groups called I/O banks:
- The I/O banks have independent supplies that allow each bank to support different I/O standards.
- Each I/O bank can support multiple I/O standards that use the same voltage.
I/O Banks for Intel Arria 10 GX Devices
The following tables list the I/O banks available, the total number of I/O pins in each bank, and the total number of I/O pins for each product line and device package of the Intel® Arria® 10 GX device family variant.
Product Line | GX 160 | GX 220 | |||||
---|---|---|---|---|---|---|---|
Package | U19 | F27 | F29 | U19 | F27 | F29 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 |
2J | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | — | 48 | 48 | — | 48 | 48 | |
3B | 4 | — | 48 | 4 | — | 48 | |
Total | 196 | 240 | 288 | 196 | 240 | 288 |
Product Line | GX 270 | GX 320 | |||||||
---|---|---|---|---|---|---|---|---|---|
Package | F27 | F29 | F34 | F35 | F27 | F29 | F34 | F35 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
2J | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3B | — | 48 | 48 | 48 | — | 48 | 48 | 48 | |
3C | — | 48 | 48 | 48 | — | 48 | 48 | 48 | |
3D | — | 24 | 48 | 48 | — | 24 | 48 | 48 | |
Total | 240 | 360 | 384 | 384 | 240 | 360 | 384 | 384 |
Product Line | GX 480 | |||
---|---|---|---|---|
Package | F29 | F34 | F35 | |
I/O Bank | 2A | 48 | 48 | 48 |
2I | — | 12 | 12 | |
2J | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | |
3B | 48 | 48 | 48 | |
3C | 48 | 48 | 48 | |
3D | 24 | 48 | 48 | |
3E | — | 48 | — | |
3F | — | 48 | — | |
Total | 360 | 492 | 396 |
Product Line | GX 570 | GX 660 | |||||||
---|---|---|---|---|---|---|---|---|---|
Package | F34 | F35 | NF40 | KF40 | F34 | F35 | NF40 | KF40 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
2G | — | — | — | 24 | — | — | — | 24 | |
2H | — | — | — | 48 | — | — | — | 48 | |
2I | 12 | 12 | 12 | 48 | 12 | 12 | 12 | 48 | |
2J | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3B | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3C | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3D | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3E | 48 | — | 48 | 48 | 48 | — | 48 | 48 | |
3F | 48 | — | 48 | 48 | 48 | — | 48 | 48 | |
3G | — | — | 48 | 48 | — | — | 48 | 48 | |
3H | — | — | 48 | 48 | — | — | 48 | 48 | |
Total | 492 | 396 | 588 | 696 | 492 | 396 | 588 | 696 |
Product Line | GX 900 | ||||||
---|---|---|---|---|---|---|---|
Package | F34 | NF40 | RF40 | NF45 | SF45 | UF45 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 |
2F | — | — | 48 | 48 | — | — | |
2G | — | — | — | 48 | — | — | |
2H | — | — | — | 48 | — | — | |
2I | 24 | 24 | — | 48 | 48 | 48 | |
2J | 48 | 48 | — | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 28 | 48 | 48 | 48 | |
3B | 48 | 48 | 27 | 48 | 48 | 48 | |
3C | 48 | 48 | — | 48 | 48 | 48 | |
3D | 48 | 48 | — | 48 | 48 | 48 | |
3E | 48 | 48 | — | 48 | 48 | 48 | |
3F | 48 | 48 | — | 48 | 48 | — | |
3G | — | 48 | 47 | 48 | 48 | — | |
3H | — | 48 | 48 | 48 | 48 | — | |
Total | 504 | 600 | 342 | 768 | 624 | 480 |
Product Line | GX 1150 | ||||||
---|---|---|---|---|---|---|---|
Package | F34 | NF40 | RF40 | NF45 | SF45 | UF45 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 |
2F | — | — | 48 | 48 | — | — | |
2G | — | — | — | 48 | — | — | |
2H | — | — | — | 48 | — | — | |
2I | 24 | 24 | — | 48 | 48 | 48 | |
2J | 48 | 48 | — | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 28 | 48 | 48 | 48 | |
3B | 48 | 48 | 27 | 48 | 48 | 48 | |
3C | 48 | 48 | — | 48 | 48 | 48 | |
3D | 48 | 48 | — | 48 | 48 | 48 | |
3E | 48 | 48 | — | 48 | 48 | 48 | |
3F | 48 | 48 | — | 48 | 48 | — | |
3G | — | 48 | 47 | 48 | 48 | — | |
3H | — | 48 | 48 | 48 | 48 | — | |
Total | 504 | 600 | 342 | 768 | 624 | 480 |
I/O Banks for Intel Arria 10 GT Devices
The following table lists the I/O banks available, the total number of I/O pins in each bank, and the total number of I/O pins for each product line and device package of the Intel® Arria® 10 GT device family variant.
Product Line | GT 900 | GT 1150 | |
---|---|---|---|
Package | SF45 | SF45 | |
I/O Bank | 2A | 48 | 48 |
2I | 48 | 48 | |
2J | 48 | 48 | |
2K | 48 | 48 | |
2L | 48 | 48 | |
3A | 48 | 48 | |
3B | 48 | 48 | |
3C | 48 | 48 | |
3D | 48 | 48 | |
3E | 48 | 48 | |
3F | 48 | 48 | |
3G | 48 | 48 | |
3H | 48 | 48 | |
Total | 624 | 624 |
I/O Banks for Intel Arria 10 SX Devices
The following tables list the I/O banks available, the total number of I/O pins in each bank, and the total number of I/O pins for each product line and device package of the Intel® Arria® 10 SX device family variant.
Product Line | SX 160 | SX 220 | |||||
---|---|---|---|---|---|---|---|
Package | U19 | F27 | F29 | U19 | F27 | F29 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 |
2J | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | — | 48 | 48 | — | 48 | 48 | |
3B | 4 | — | 48 | 4 | — | 48 | |
Total | 196 | 240 | 288 | 196 | 240 | 288 |
Product Line | SX 270 | SX 320 | |||||||
---|---|---|---|---|---|---|---|---|---|
Package | F27 | F29 | F34 | F35 | F27 | F29 | F34 | F35 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
2J | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3B | — | 48 | 48 | 48 | — | 48 | 48 | 48 | |
3C | — | 48 | 48 | 48 | — | 48 | 48 | 48 | |
3D | — | 24 | 48 | 48 | — | 24 | 48 | 48 | |
Total | 240 | 360 | 384 | 384 | 240 | 360 | 384 | 384 |
Product Line | SX 480 | |||
---|---|---|---|---|
Package | F29 | F34 | F35 | |
I/O Bank | 2A | 48 | 48 | 48 |
2I | — | 12 | 12 | |
2J | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | |
3B | 48 | 48 | 48 | |
3C | 48 | 48 | 48 | |
3D | 24 | 48 | 48 | |
3E | — | 48 | — | |
3F | — | 48 | — | |
Total | 360 | 492 | 396 |
Product Line | SX 570 | SX 660 | |||||||
---|---|---|---|---|---|---|---|---|---|
Package | F34 | F35 | NF40 | KF40 | F34 | F35 | NF40 | KF40 | |
I/O Bank | 2A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
2G | — | — | — | 24 | — | — | — | 24 | |
2H | — | — | — | 48 | — | — | — | 48 | |
2I | 12 | 12 | 12 | 48 | 12 | 12 | 12 | 48 | |
2J | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2K | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
2L | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3A | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3B | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3C | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3D | 48 | 48 | 48 | 48 | 48 | 48 | 48 | 48 | |
3E | 48 | — | 48 | 48 | 48 | — | 48 | 48 | |
3F | 48 | — | 48 | 48 | 48 | — | 48 | 48 | |
3G | — | — | 48 | 48 | — | — | 48 | 48 | |
3H | — | — | 48 | 48 | — | — | 48 | 48 | |
Total | 492 | 396 | 588 | 696 | 492 | 396 | 588 | 696 |
I/O Vertical Migration for Intel Arria 10 Devices
- The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Devices with fewer resources in the same path have lighter shades.
- To achieve the full I/O migration across product lines in the same migration path, restrict I/Os and transceivers usage to match the product line with the lowest I/O and transceiver counts.
- An LVDS I/O bank in the source device may be mapped to a 3 V I/O bank in the target device. To use memory interface clock frequency higher than 533 MHz, assign external memory interface pins only to banks that are LVDS I/O in both devices.
- There may be nominal 0.15 mm package height difference between some product lines in the same package type.
- Some migration paths are not shown in the Intel® Quartus® Prime software Pin Migration View.
Verifying Pin Migration Compatibility
You can use the Pin Migration View window in the Intel® Quartus® Prime software Pin Planner to assist you in verifying whether your pin assignments migrate to a different device successfully. You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts.
- Open Assignments > Pin Planner and create pin assignments.
-
If necessary,
perform one of the following options to populate the Pin Planner with the node
names in the design:
- Analysis & Elaboration
- Analysis & Synthesis
- Fully compile the design
- Then, on the menu, click View > Pin Migration View.
-
To select or change
migration devices:
- Click Device to open the Device dialog box.
- Under Migration compatibility click Migration Devices.
-
To show more
information about the pins:
- Right-click anywhere in the Pin Migration View window and select Show Columns.
- Then, click the pin feature you want to display.
- If you want to view only the pins, in at least one migration device, that have a different feature than the corresponding pin in the migration result, turn on Show migration differences.
-
Click Pin Finder to open the Pin Finder dialog box to find and highlight pins
with specific functionality.
If you want to view only the pins highlighted by the most recent query in the Pin Finder dialog box, turn on Show only highlighted pins.
- To export the pin migration information to a Comma-Separated Value file (.csv), click Export.
Architecture and General Features of I/Os in Intel Arria 10 Devices
I/O Element Structure in Intel Arria 10 Devices
The I/O elements (IOEs) in Intel® Arria® 10 devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
The IOEs are located in I/O columns within the core fabric of the Intel® Arria® 10 device.
The Intel® Arria® 10 SX devices also have IOEs for the HPS.
The GPIO IOE register consists of the DDR register, the half rate register, and the transmitter delay chains for input, output, and output enable (OE) paths:
- You can take data from the combinatorial path or the registered path.
- Only the core clock clocks the data.
- The half rate clock routed from the core clocks the half rate register.
- The full rate clock from the core clocks the full rate register.
I/O Bank Architecture in Intel Arria 10 Devices
I/O Buffer and Registers in Intel Arria 10 Devices
I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization. Use the Intel® FPGA GPIO Intel® FPGA IP to utilize these registers to implement DDR circuitry.
The input and output paths contains the following blocks:
- Input registers—support half/full rate data transfer from peripheral to core, and support double or single data rate data capture from I/O buffer.
- Output registers—support half/full rate data transfer from core to peripheral, and support double or single data rate data transfer to I/O buffer.
- OE registers—support half or full rate data transfer from core to peripheral, and support single data rate data transfer to I/O buffer.
The input and output paths also support the following features:
- Clock enable.
- Asynchronous or synchronous reset.
- Bypass mode for input and output paths.
- Delays chains on input and output paths.
Features of I/O Pins in Intel Arria 10 Devices
Open-Drain Output
The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured as an open drain, the logic value of the output is either high-Z or logic low.
Use an external resistor to pull the signal to a logic high.
Bus-Hold Circuitry
Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.
Weak Pull-up Resistor
Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor, typically 25 kΩ, weakly holds the I/O to the VCCIO level.
The Intel® Arria® 10 device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated configuration pins, dedicated clock pins, or JTAG pins .
If you enable this option, you cannot use the bus-hold feature.
Programmable IOE Features in Intel Arria 10 Devices
Feature |
Setting |
Condition |
Intel® Quartus® Prime Assignment Name |
---|---|---|---|
Slew Rate Control | 0 (Slow), 1 (Fast). Default is 1. | Disabled if you use the RS OCT feature. | SLEW_RATE |
I/O Delay | Refer to the device datasheet | — |
INPUT_DELAY_CHAIN OUTPUT_DELAY_CHAIN |
Open-Drain Output | On, Off. Default is Off | — | AUTO_OPEN_DRAIN_PINS |
Bus-Hold | On, Off. Default is Off. | Disabled if you use the weak pull-up resistor feature. | ENABLE_BUS_HOLD_CIRCUITRY |
Weak Pull-up Resistor | On, Off. Default is Off. | Disabled if you use the bus-hold feature. | WEAK_PULL_UP_RESISTOR |
Pre-Emphasis | 0 (disabled), 1 (enabled). Default is 1. | — | PROGRAMMABLE_PREEMPHASIS |
Differential Output Voltage | 0 (low), 1 (medium low), 2 (medium high), 3 (high). Default is 2. | — | PROGRAMMABLE_VOD |
Feature | I/O Buffer Type Support |
I/O Standards Support |
||
---|---|---|---|---|
LVDS I/O | 3 V I/O |
HPS I/O (SoC Devices Only) |
||
Slew Rate Control | Yes | Yes | Yes |
|
I/O Delay | Yes | Yes | — | |
Open-Drain Output | Yes | Yes | Yes |
|
Bus-Hold | Yes | Yes | Yes | |
Weak Pull-up Resistor | Yes | Yes | Yes | |
Pre-Emphasis | Yes | — | — |
|
Differential Output Voltage | Yes | — | — |
|
Programmable Current Strength
To use programmable current strength, you must specify the current strength assignment in the Intel® Quartus® Prime software. Without explicit assignments, the Intel® Quartus® Prime software uses these predefined default values:
- All HSTL and SSTL Class I, and all non-voltage-referenced I/O standards—50 Ω RS OCT without calibration
- All HSTL and SSTL Class II I/O standards—25 Ω RS OCT without calibration
- POD12 I/O standard—34 Ω RS OCT without calibration
I/O Standard |
IOH / IOL Current Strength Setting (mA) (Default setting in bold) 7 |
Supported in HPS (SoC Devices Only) 8 |
---|---|---|
3.0 V LVTTL | 24, 20, 16, 12, 8, 4 | 24, 20, 16, 12, 8, 4 |
3.0 V CMOS | 16, 12, 8, 4 | 16, 12, 8, 4 |
2.5 V LVCMOS | 16, 12, 8, 4 | 16, 12, 8, 4 |
1.8 V LVCMOS | 12, 10, 8, 6, 4, 2 | 12, 10, 8, 6, 4, 2 |
1.5 V LVCMOS | 12, 10, 8, 6, 4, 2 | 12, 10, 8, 6, 4, 2 |
1.2 V LVCMOS | 8, 6, 4, 2 | — |
SSTL-18 Class I | 12, 10, 8, 6, 4 | 12, 10, 8, 6, 4 |
SSTL-18 Class II | 16 | 8, 16 |
SSTL-15 Class I | 12, 10, 8, 6, 4 | 12, 10, 8, 6, 4 |
SSTL-15 Class II | 16 | 8, 16 |
SSTL-135 Class I | 12, 10, 8, 6, 4 | — |
SSTL-135 Class II | 16 | — |
SSTL-125 Class I | 12, 10, 8, 6, 4 | — |
SSTL-125 Class II | 16 | — |
SSTL-12 Class I | 12, 10, 8, 6, 4 | — |
SSTL-12 Class II | 16 | — |
POD12 | 16, 12, 10, 8, 6, 4 | — |
1.8 V HSTL Class I | 12, 10, 8, 6, 4 | 12, 10, 8, 6, 4 |
1.8 V HSTL Class II | 16 | 16 |
1.5 V HSTL Class I | 12, 10, 8, 6, 4 | 12, 10, 8, 6, 4 |
1.5 V HSTL Class II | 16 | 16 |
1.2 V HSTL Class I | 12, 10, 8, 6, 4 | — |
1.2 V HSTL Class II | 16 | — |
Differential SSTL-135 Class I | 12, 10, 8, 6, 4 | — |
Differential SSTL-135 Class II | 16 | — |
Differential SSTL-125 Class I | 12, 10, 8, 6, 4 | — |
Differential SSTL-125 Class II | 16 | — |
Differential SSTL-12 Class I | 12, 10, 8, 6, 4 | — |
Differential SSTL-12 Class II | 16 | — |
Differential POD12 | 16, 12, 10, 8, 6, 4 | — |
Programmable Output Slew Rate Control
The programmable output slew rate control in the output buffer of each regular- and dual-function I/O pin allows you to configure the following:
- Fast slew rate—provides high-speed transitions for high-performance systems.
- Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew rate control.
Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or increase clock-to-output time. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.
Each pin can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the signals within a bus have the same delay going into or out of the device.
- In the output and OE paths, there are the output and OE delays which have 50 ps incremental delays and a maximum delay of 800 ps.
- In the input paths, there are two input delay chains with incremental delays of 50 ps and a maximum delay of 3.2 ns.
For more information about the programmable IOE delay specifications, refer to the device datasheet.
Programmable Open-Drain Output
You can attach several open-drain output to a wire. This connection type is like a logical OR function and is commonly called an active-low wired-OR circuit. If at least one of the outputs is in logic 0 state (active), the circuit sinks the current and brings the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For example, you can use the open-drain output for system-level control signals that can be asserted by any device or as an interrupt.
- Design the tristate buffer using OPNDRN primitive.
- Turn on the Auto Open-Drain Pins option in the Intel® Quartus® Prime software.
Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. The overshoot introduced by the extra current happens only during a change of state switching to increase the output slew rate and does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Pre-emphasis |
Allowed values | 0 (disabled), 1 (enabled). Default is 1. |
Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller VOD swing reduces power consumption. You can statically adjust the VOD of the differential signal by changing the VOD settings in the Intel® Quartus® Prime software Assignment Editor.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Differential Output Voltage (VOD) |
Allowed values | 0 (low), 1 (medium low), 2 (medium high), 3 (high). Default is 2. |
On-Chip I/O Termination in Intel Arria 10 Devices
Serial (RS) and parallel (RT) OCT provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs.
The Intel® Arria® 10 devices support OCT in all FPGA and HPS I/O banks. For the 3 V and HPS I/Os, the I/Os support only OCT without calibration.
Direction | OCT Schemes | I/O Type Support | ||
---|---|---|---|---|
LVDS I/O | 3 V I/O | HPS I/O | ||
Output | RS OCT with calibration | Yes | — | — |
RS OCT without calibration | Yes | Yes | Yes | |
Input | RT OCT with calibration | Yes | — | — |
RD OCT (LVDS I/O standard only) | Yes | — | — | |
Bidirectional | Dynamic RS and RT OCT | Yes | — | — |
RS OCT without Calibration in Intel Arria 10 Devices
The Intel® Arria® 10 devices support RS OCT for single-ended and voltage-referenced I/O standards. RS OCT without calibration is supported on output only.
I/O Standard | Device Variant Support | Uncalibrated OCT (Output) |
---|---|---|
RS (Ω) | ||
3.0 V LVTTL/3.0 V LVCMOS | GX, SX | 25/50 |
2.5 V LVCMOS | GX, SX | 25/50 |
1.8 V LVCMOS | All | 25/50 |
1.5 V LVCMOS | All | 25/50 |
1.2 V LVCMOS | All | 25/50 |
SSTL-18 Class I | All | 50 |
SSTL-18 Class II | All | 25 |
SSTL-15 Class I | All | 50 |
SSTL-15 Class II | All | 25 |
SSTL-15 | All | 34, 40 |
SSTL-135 | All | 34, 40 |
SSTL-125 | All | 34, 40 |
SSTL-12 | All | 40, 60, 120, 240 |
POD12 | All | 34, 40, 48, 60 |
1.8 V HSTL Class I | All | 50 |
1.8 V HSTL Class II | All | 25 |
1.5 V HSTL Class I | All | 50 |
1.5 V HSTL Class II | All | 25 |
1.2 V HSTL Class I | All | 50 |
1.2 V HSTL Class II | All | 25 |
HSUL-12 | All | 34.3, 40, 48, 60, 80 |
Differential SSTL-18 Class I | All | 50 |
Differential SSTL-18 Class II | All | 25 |
Differential SSTL-15 Class I | All | 50 |
Differential SSTL-15 Class II | All | 25 |
Differential SSTL-15 | All | 34, 40 |
Differential SSTL-135 | All | 34, 40 |
Differential SSTL-125 | All | 34, 40 |
Differential SSTL-12 | All | 40, 60, 120, 240 |
Differential POD12 | All | 34, 40, 48, 60 |
Differential 1.8 V HSTL Class I | All | 50 |
Differential 1.8 V HSTL Class II | All | 25 |
Differential 1.5 V HSTL Class I | All | 50 |
Differential 1.5 V HSTL Class II | All | 25 |
Differential 1.2 V HSTL Class I | All | 50 |
Differential 1.2 V HSTL Class II | All | 25 |
Differential HSUL-12 | All | 34.3, 40, 48, 60, 80 |
Driver-impedance matching provides the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce signal reflections on PCB traces.
If you select matching impedance, current strength is no longer selectable.
RS OCT with Calibration in Intel Arria 10 Devices
The Intel® Arria® 10 devices support RS OCT with calibration in all LVDS I/O banks.
I/O Standard | Device Variant Support | Calibrated OCT (Output) | |
---|---|---|---|
RS (Ω) | RZQ (Ω) | ||
1.8 V LVCMOS | All | 25, 50 | 100 |
1.5 V LVCMOS | All | 25, 50 | 100 |
1.2 V LVCMOS | All | 25, 50 | 100 |
SSTL-18 Class I | All | 50 | 100 |
SSTL-18 Class II | All | 25 | 100 |
SSTL-15 Class I | All | 50 | 100 |
SSTL-15 Class II | All | 25 | 100 |
SSTL-15 | All | 25, 50 | 100 |
34, 40 | 240 | ||
SSTL-135 | All | 34, 40 | 240 |
SSTL-125 | All | 34, 40 | 240 |
SSTL-12 | All | 40, 60, 120, 240 | 240 |
POD12 | All | 34, 40, 48, 60 | 240 |
1.8 V HSTL Class I | All | 50 | 100 |
1.8 V HSTL Class II | All | 25 | 100 |
1.5 V HSTL Class I | All | 50 | 100 |
1.5 V HSTL Class II | All | 25 | 100 |
1.2 V HSTL Class I | All | 50 | 100 |
1.2 V HSTL Class II | All | 25 | 100 |
HSUL-12 | All | 34, 40, 48, 60, 80 | 240 |
Differential SSTL-18 Class I | All | 50 | 100 |
Differential SSTL-18 Class II | All | 25 | 100 |
Differential SSTL-15 Class I | All | 50 | 100 |
Differential SSTL-15 Class II | All | 25 | 100 |
Differential SSTL-15 | All | 25, 50 | 100 |
34, 40 | 240 | ||
Differential SSTL-135 | All | 34, 40 | 240 |
Differential SSTL-125 | All | 34, 40 | 240 |
Differential SSTL-12 | All | 40, 60, 120, 240 | 240 |
Differential POD12 | All | 34, 40, 48, 60 | 240 |
Differential 1.8 V HSTL Class I | All | 50 | 100 |
Differential 1.8 V HSTL Class II | All | 25 | 100 |
Differential 1.5 V HSTL Class I | All | 50 | 100 |
Differential 1.5 V HSTL Class II | All | 25 | 100 |
Differential 1.2 V HSTL Class I | All | 50 | 100 |
Differential 1.2 V HSTL Class II | All | 25 | 100 |
Differential HSUL-12 | All | 34, 40, 48, 60, 80 | 240 |
The RS OCT calibration circuit compares the total impedance of the I/O buffer to the external reference resistor connected to the RZQ pin and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. When the calibration circuit finds the correct impedance, the circuit powers down and stops changing the characteristics of the drivers.
RT OCT with Calibration in Intel Arria 10 Devices
The Intel® Arria® 10 devices support RT OCT with calibration in all LVDS I/O banks but not in the 3 V I/O banks. RT OCT with calibration is available only for configuration of input and bidirectional pins. Output pin configurations do not support RT OCT with calibration. If you use RT OCT, the VCCIO of the bank must match the I/O standard of the pin where you enable the RT OCT.
I/O Standard | Device Variant Support | Calibrated OCT (Input) | |
---|---|---|---|
RT (Ω) | RZQ (Ω) | ||
SSTL-18 Class I | All | 50 | 100 |
SSTL-18 Class II | All | 50 | 100 |
SSTL-15 Class I | All | 50 | 100 |
SSTL-15 Class II | All | 50 | 100 |
SSTL-15 | All | 30, 40, 60,120 | 240 |
SSTL-135 | All | 30, 40, 60, 120 | 240 |
SSTL-125 | All | 30, 40, 60, 120 | 240 |
SSTL-12 | All | 60, 120 | 240 |
POD12 | All | 34, 40, 48, 60, 80, 120, 240 | 240 |
1.8 V HSTL Class I | All | 50 | 100 |
1.8 V HSTL Class II | All | 50 | 100 |
1.5 V HSTL Class I | All | 50 | 100 |
1.5 V HSTL Class II | All | 50 | 100 |
1.2 V HSTL Class I | All | 50 | 100 |
1.2 V HSTL Class II | All | 50 | 100 |
Differential SSTL-18 Class I | All | 50 | 100 |
Differential SSTL-18 Class II | All | 50 | 100 |
Differential SSTL-15 Class I | All | 50 | 100 |
Differential SSTL-15 Class II | All | 50 | 100 |
Differential SSTL-15 | All | 30, 40, 60,120 | 240 |
Differential SSTL-135 | All | 30, 40, 60, 120 | 240 |
Differential SSTL-125 | All | 30, 40, 60, 120 | 240 |
Differential SSTL-12 | All | 60, 120 | 240 |
Differential POD12 | All | 34, 40, 48, 60, 80, 120, 240 | 240 |
Differential 1.8 V HSTL Class I | All | 50 | 100 |
Differential 1.8 V HSTL Class II | All | 50 | 100 |
Differential 1.5 V HSTL Class I | All |