Intel MAX 10 High-Speed LVDS I/O User Guide
Intel MAX 10 High-Speed LVDS I/O Overview
The LVDS I/O banks in Intel® MAX® 10 devices feature true and emulated LVDS buffers:
- True LVDS buffers support LVDS using true differential buffers.
- Emulated LVDS buffers use a pair of single-ended pins to emulate differential buffers.
I/O Buffer Type | I/O Bank Support |
---|---|
True LVDS input buffer | All I/O banks |
True LVDS output buffer | Only bottom I/O banks |
Emulated LVDS output buffer | All I/O banks |
The Intel® MAX® 10 D (dual supply) and S (single supply) device variants support different LVDS I/O standards. For a list of LVDS I/O standards supported by the Intel® MAX® 10 D and S variants, refer to the related information.
Altera Soft LVDS Implementation Overview
Intel MAX 10 High-Speed LVDS Architecture and Features
- For LVDS transmitters and receivers, Intel® MAX® 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
- For the LVDS serializer/deserializer (SERDES), Intel® MAX® 10 devices use logic elements (LE) registers.
Intel MAX 10 LVDS Channels Support
Product Line | Package | Device Power Supply | Side | True LVDS Pairs | Emulated LVDS Pairs | |
---|---|---|---|---|---|---|
TX | RX | |||||
10M02 | V36 | Dual | Top | 0 | 1 | 1 |
Right | 0 | 3 | 3 | |||
Left | 0 | 3 | 3 | |||
Bottom | 3 | 3 | 3 | |||
M153 | Single | Top | 0 | 12 | 12 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 12 | 12 | |||
Bottom | 9 | 13 | 13 | |||
U169 | Single | Top | 0 | 12 | 12 | |
Right | 0 | 17 | 17 | |||
Left | 0 | 15 | 15 | |||
Bottom | 9 | 14 | 14 | |||
U324 | Single | Top | 0 | 27 | 27 | |
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
Dual | Top | 0 | 13 | 13 | ||
Right | 0 | 24 | 24 | |||
Left | 0 | 20 | 20 | |||
Bottom | 9 | 16 | 16 | |||
E144 | Single | Top | 0 | 10 | 10 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 7 | 12 | 12 | |||
10M04 | M153 | Single | Top | 0 | 12 | 12 |
Right | 0 | 12 | 12 | |||
Left | 0 | 12 | 12 | |||
Bottom | 9 | 13 | 13 | |||
U169 | Single | Top | 0 | 12 | 12 | |
Right | 0 | 17 | 17 | |||
Left | 0 | 15 | 15 | |||
Bottom | 9 | 14 | 14 | |||
U324 | Single | Top | 0 | 27 | 27 | |
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
Dual | Top | 0 | 27 | 27 | ||
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
F256 | Dual | Top | 0 | 19 | 19 | |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 8 | 8 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
10M08 | V81 | Dual | Top | 0 | 5 | 5 |
Right | 0 | 7 | 7 | |||
Left | 0 | 6 | 6 | |||
Bottom | 7 | 7 | 7 | |||
M153 | Single | Top | 0 | 12 | 12 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 12 | 12 | |||
Bottom | 9 | 13 | 13 | |||
U169 | Single | Top | 0 | 12 | 12 | |
Right | 0 | 17 | 17 | |||
Left | 0 | 15 | 15 | |||
Bottom | 9 | 14 | 14 | |||
U324 | Single | Top | 0 | 27 | 27 | |
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
Dual | Top | 0 | 27 | 27 | ||
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
F256 | Dual | Top | 0 | 19 | 19 | |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 8 | 8 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
F484 | Dual | Top | 0 | 27 | 27 | |
Right | 0 | 33 | 33 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
10M16 | U169 | Single | Top | 0 | 12 | 12 |
Right | 0 | 17 | 17 | |||
Left | 0 | 15 | 15 | |||
Bottom | 9 | 14 | 14 | |||
U324 | Single | Top | 0 | 27 | 27 | |
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
Dual | Top | 0 | 27 | 27 | ||
Right | 0 | 31 | 31 | |||
Left | 0 | 28 | 28 | |||
Bottom | 15 | 28 | 28 | |||
F256 | Dual | Top | 0 | 19 | 19 | |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 8 | 8 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
F484 | Dual | Top | 0 | 39 | 39 | |
Right | 0 | 38 | 38 | |||
Left | 0 | 32 | 32 | |||
Bottom | 22 | 42 | 42 | |||
10M25 | F256 | Dual | Top | 0 | 19 | 19 |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 8 | 8 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
F484 | Dual | Top | 0 | 41 | 41 | |
Right | 0 | 48 | 48 | |||
Left | 0 | 36 | 36 | |||
Bottom | 24 | 46 | 46 | |||
10M40 | F256 | Dual | Top | 0 | 19 | 19 |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 9 | 9 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
F484 | Dual | Top | 0 | 41 | 41 | |
Right | 0 | 48 | 48 | |||
Left | 0 | 36 | 36 | |||
Bottom | 24 | 46 | 46 | |||
F672 | Dual | Top | 0 | 53 | 53 | |
Right | 0 | 70 | 70 | |||
Left | 0 | 60 | 60 | |||
Bottom | 30 | 58 | 58 | |||
10M50 | F256 | Dual | Top | 0 | 19 | 19 |
Right | 0 | 22 | 22 | |||
Left | 0 | 19 | 19 | |||
Bottom | 13 | 20 | 20 | |||
E144 | Single | Top | 0 | 9 | 9 | |
Right | 0 | 12 | 12 | |||
Left | 0 | 11 | 11 | |||
Bottom | 10 | 10 | 10 | |||
F484 | Dual | Top | 0 | 41 | 41 | |
Right | 0 | 48 | 48 | |||
Left | 0 | 36 | 36 | |||
Bottom | 24 | 46 | 46 | |||
F672 | Dual | Top | 0 | 53 | 53 | |
Right | 0 | 70 | 70 | |||
Left | 0 | 60 | 60 | |||
Bottom | 30 | 58 | 58 |
Intel MAX 10 LVDS SERDES I/O Standards Support
I/O Standard | I/O Bank | TX | RX | Intel® MAX® 10 Device Support | Notes | |
---|---|---|---|---|---|---|
Dual Supply Device |
Single Supply Device |
|||||
True LVDS | All | Bottom banks only | Yes | Yes | Yes |
|
Emulated LVDS (three resistors) | All | Yes | — | Yes | Yes |
All I/O banks support emulated LVDS output buffers. |
True RSDS | Bottom | Yes | — | Yes | Yes | — |
Emulated RSDS (single resistor) | All | Yes | — | Yes | — |
All I/O banks support emulated RSDS output buffers. |
Emulated RSDS (three resistors) | All | Yes | — | Yes | Yes |
All I/O banks support emulated RSDS output buffers. |
True Mini-LVDS | Bottom | Yes | — | Yes | — | — |
Emulated Mini-LVDS (three resistors) | All | Yes | — | Yes | — |
All I/O banks support emulated Mini-LVDS output buffers. |
PPDS | Bottom | Yes | — | Yes | — | — |
Emulated PPDS (three resistors) | All | Yes | — | Yes | — | — |
Bus LVDS | All | Yes | Yes | Yes | Yes |
|
LVPECL | All | — | Yes | Yes | Yes |
Supported only on dual function clock input pins. |
TMDS | All | — | Yes | Yes | — |
|
Sub-LVDS | All | Yes | Yes | Yes | — |
|
SLVS | All | Yes | Yes | Yes | — |
|
HiSpi | All | — | Yes | Yes | — |
|
Intel MAX 10 High-Speed LVDS Circuitry
The Intel® MAX® 10 devices do not contain dedicated serialization or deserialization circuitry:
- You can use I/O pins and core fabric to implement a high-speed differential interface in the device.
- The Intel® MAX® 10 solution uses shift registers, internal PLLs, and I/O elements to perform the serial-to-parallel and parallel-to-serial conversions of incoming and outgoing data.
- The Intel® Quartus® Prime software uses the parameter settings of the Altera Soft LVDS IP core to automatically construct the differential SERDES in the core fabric.
Intel MAX 10 High-Speed LVDS I/O Location
Differential I/O Pins in Low Speed Region
- For each user I/O pin (excluding configuration pin) that you place in the low speed region, the Intel® Quartus® Prime software generates an informational warning message.
- Refer to the device pinout to identify the low speed I/O pins.
- Refer to the device datasheet for the performance information of these I/O pins.
Intel MAX 10 LVDS Transmitter Design
High-Speed I/O Transmitter Circuitry
LVDS Transmitter Programmable I/O Features
Programmable Pre-Emphasis
Pre-emphasis increases the amplitude of the high-frequency component of the output signal. This increase compensates for the frequency-dependent attenuation along the transmission line.
The overshoot introduced by the extra current occurs only during change of state switching. This overshoot increases the output slew rate but does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Pre-emphasis |
Allowed values | 0 (disabled), 1 (enabled). Default is 1. |
Programmable Differential Output Voltage
You can statically adjust the VOD of the differential signal by changing the VOD settings in the Intel® Quartus® Prime software Assignment Editor.
Field | Assignment |
---|---|
To | tx_out |
Assignment name | Programmable Differential Output Voltage (VOD) |
Allowed values | 0 (low), 1 (medium), 2 (high). Default is 2. |
LVDS Transmitter I/O Termination Schemes
Emulated LVDS External Termination
Sub-LVDS Transmitter External Termination
SLVS Transmitter External Termination
Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
LVDS Transmitter FPGA Design Implementation
Altera Soft LVDS IP Core in Transmitter Mode
- You can use the Altera Soft LVDS parameter editor to customize your serializer based on your design requirements.
- The high-speed I/O interface created using the Altera Soft LVDS IP core always sends the most significant bit (MSB) of your parallel data first.
Guidelines: LVDS TX Interface Using External PLL
If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core:
- Serial clock input to the tx_inclock port of the Altera Soft LVDS transmitter.
- Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port.
ALTPLL Signal Interface with Altera Soft LVDS Transmitter
If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS transmitter, use the source-synchronous compensation mode.
From the ALTPLL IP Core | To the Altera Soft LVDS Transmitter |
---|---|
Fast clock output (c0) The fast clock output (c0) can only drive tx_inclock on the Altera Soft LVDS transmitter. |
tx_inclock |
Slow clock output (c1) |
tx_syncclock |
Determining External PLL Clock Parameters for Altera Soft LVDS Transmitter
- Instantiate the Altera Soft LVDS IP core transmitter using internal PLL.
- Compile the design up to TimeQuest timing analysis.
- In the Table of Contents section of the Compilation Report window, navigate to TimeQuest Timing Analyzer > Clocks.
-
Note the clock parameters used by the internal PLL for the
Altera Soft LVDS IP core transmitter.
In the list of clocks, clk0 is the fast clock.

Guidelines: LVDS Transmitter Channels Placement
Intel recommends that you create a Intel® Quartus® Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Intel® Quartus® Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device will operate properly.
You can use the Intel® Quartus® Prime Pin Planner Package view to ease differential I/O assignment planning:
- On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
- For differential pins, you only need to assign the signal to a positive pin. The Intel® Quartus® Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.
In Intel® MAX® 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.
Guidelines: LVDS Transmitter Logic Placement
To improve the performance of the Intel® Quartus® Prime Fitter, you can create LogicLock™ regions in the device floorplan to confine the transmitter SERDES logic placement.
- The TCCS parameter is guaranteed per datasheet specification to the entire bank of differential I/Os that are located in the same side. This guarantee applies if the transmitter SERDES logic is placed within the LAB adjacent to the output pins.
- Constrain the transmitter SERDES logic to the LAB adjacent to the data output pins and clock output pins to improve the TCCS performance.
Guidelines: Enable LVDS Pre-Emphasis for E144 Package
LVDS Transmitter Debug and Troubleshooting
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Intel SignalTap® II Logic Analyzer to perform system level verification to correlate the system against your design targets.
Intel MAX 10 LVDS Receiver Design
High-Speed I/O Receiver Circuitry
In the receiver mode, the following blocks are available in the differential receiver datapath:
- Deserializer
- Data realignment block (bit slip)
Soft Deserializer
Signal | Description |
---|---|
rx_in |
LVDS data stream, input to the Altera Soft LVDS channel. |
fclk | Clock used for receiver. |
loaden | Enable signal for deserialization generated by the Altera Soft LVDS IP core. |
rx_out[9:0] | Deserialized data. |
Data Realignment Block (Bit Slip)
To align the data manually, use the data realignment circuit to insert a latency of one RxFCLK cycle . The data realignment circuit slips the data one bit for every RX_DATA_ALIGN pulse. You must wait at least two core clock cycles before checking to see if the data is aligned. This wait is necessary because it takes at least two core clock cycles to purge the corrupted data.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently of the internal logic. The data slips one bit on the rising edge of RX_CHANNEL_DATA_ALIGN.
The RX_CHANNEL_DATA_ALIGN signal has these requirements:
- The minimum pulse width is one period of the parallel clock in the logic array.
- The minimum low time between pulses is one period of the parallel clock.
- The signal is edge-triggered.
- The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN.
LVDS Receiver I/O Termination Schemes
LVDS, Mini-LVDS, and RSDS Receiver External Termination
SLVS Receiver External Termination
Sub-LVDS Receiver External Termination
TMDS Receiver External Termination
HiSpi Receiver External Termination
LVPECL External Termination
- LVDS input buffers support LVPECL input operation.
- LVPECL output operation is not supported.
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the Intel® MAX® 10 LVPECL input buffer specification.
For information about the VICM specification, refer to the device datasheet.
LVDS Receiver FPGA Design Implementation
Altera Soft LVDS IP Core in Receiver Mode
- You can use the Altera Soft LVDS parameter editor to customize your deserializer based on your design requirements.
- The Altera Soft LVDS IP core implements the high-speed deserializer in the core fabric.
PLL Source Selection for Altera Soft LVDS IP Core
Instantiate Altera Soft LVDS IP Core with Internal PLL
- To use this method, turn off the Use external PLL option in the PLL Settings tab.
- The Altera Soft LVDS IP core integrates the PLL into the LVDS block.
- The drawback of this method is that you can use the PLL only for the particular LVDS instance.
Instantiate Altera Soft LVDS IP Core with External PLL
- To use this method, turn on the Use external PLL option in the PLL Settings tab.
- Follow the required clock setting to the input ports as listed in the notification panel.
- You can create your own clocking source using the ALTPLL IP core.
- Use this method to optimize PLL usage with other functions in the core.
Guidelines: LVDS RX Interface Using External PLL
If you turn on the Use External PLL option for the Altera Soft LVDS receiver, you require the following signals from the ALTPLL IP core:
- Serial clock input to the rx_inclock port of the Altera Soft LVDS receiver.
- Parallel clock used to clock the receiver FPGA fabric logic.
- The locked signal for Altera Soft LVDS PLL reset port.
ALTPLL Signal Interface with Altera Soft LVDS Receiver
If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS receiver, use the source-synchronous compensation mode.
From the ALTPLL IP Core | To the Altera Soft LVDS Receiver |
---|---|
Fast clock output (c0) The serial clock output (c0) can only drive rx_inclock on the Altera Soft LVDS receiver. |
rx_inclock |
From the ALTPLL IP Core | To the Altera Soft LVDS Receiver |
---|---|
Fast clock output (c0) The serial clock output (c0) can only drive rx_inclock on the Altera Soft LVDS receiver. |
rx_inclock |
Slow clock output (c1) |
rx_syncclock |
Read clock (c2) output from the PLL |
rx_readclock (clock input port for reading operation from RAM buffer and read counter) |
Determining External PLL Clock Parameters for Altera Soft LVDS Receiver
- Instantiate the Altera Soft LVDS IP core receiver using internal PLL.
- Compile the design up to TimeQuest timing analysis.
- In the Table of Contents section of the Compilation Report window, navigate to TimeQuest Timing Analyzer > Clocks.
-
Note the clock parameters used by the internal PLL for the
Altera Soft LVDS IP core receiver.
In the list of clocks, clk[0] is the fast clock, clk[1] is the slow clock, and clk[2] is the read clock.

Initializing the Altera Soft LVDS IP Core
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the high-speed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Altera Soft LVDS IP core:
- Assert the pll_areset signal for at least 10 ns.
- After at least 10 ns, deassert the pll_areset signal.
-
Wait until the PLL
lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
High-Speed I/O Timing Budget
Intel® MAX® 10 devices implement the SERDES in LEs. You must set proper timing constraints to indicate whether the SERDES captures the data as expected or otherwise. You can set the timing contraints using the Timing Analyzer tool in the Intel® Quartus® Prime software or manually in the Synopsys® Design Constraints (.sdc) file.
Receiver Input Skew Margin
RSKM Equation
Conventions used for the equation:
- RSKM—the timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise.
- Time unit interval (TUI)—time period of the serial data.
- SW—the period of time that the input data must be stable to ensure that the LVDS receiver samples the data successfully. The SW is a device property and varies according to device speed grade.
- TCCS—the timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the tCO variation, clock, and clock skew.
You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS receiver can sample the data:
- A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly.
- A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly.
Example: RSKM Calculation
- TCCS = 100 ps
- SW = 300 ps
- TUI = 1000 ps
- Total RCCS = TCCS + Board channel-to-channel skew = 100 ps + 200 ps = 300 ps
- RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 300 ps) / 2 = 200 ps
If the RSKM is greater than 0 ps after deducting transmitter jitter, the receiver will work correctly.
Guidelines: LVDS Receiver Timing Constraints
For LVDS receiver data paths where the PLL operation is in source-synchronous compensation mode, the Intel® Quartus® Prime compiler automatically ensures that the associated delay chain settings are set correctly.
However, if the input clock and data at the receiver are not edge- or center-aligned, it may be necessary for you to set the timing constraints in the Intel® Quartus® Prime Timing Analyzer. The timing constraints specify the timing requirements necessary to ensure reliable data capture.
Guidelines: Floating LVDS Input Pins
For floating LVDS input pins, apply a 100 Ω differential resistance across the P and N legs of the LVDS receiver. You can use external termination.
If you use floating LVDS input pins, Intel recommends that you use external biasing schemes to reduce noise injection and current consumption.
Guidelines: LVDS Receiver Channels Placement
Intel recommends that you create a Intel® Quartus® Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Intel® Quartus® Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device will operate properly.
You can use the Intel® Quartus® Prime Pin Planner Package view to ease differential I/O assignment planning:
- On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
- For differential pins, you only need to assign the signal to a positive pin. The Intel® Quartus® Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.
In Intel® MAX® 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.
Guidelines: LVDS Channels PLL Placement
I/O Bank Edge | Input refclk | GCLK mux | Usable PLL |
---|---|---|---|
Left | Left | Left | Top left or bottom left |
Bottom | Bottom | Bottom | Bottom left or bottom right |
Right | Right | Right | Top right or bottom right |
Top | Top | Top | Top left or top right |
Guidelines: LVDS Receiver Logic Placement
To improve the performance of the Intel® Quartus® Prime Fitter, you can create LogicLock™ regions in the device floorplan to confine the transmitter SERDES logic placement.
- The TCCS parameter is guaranteed per datasheet specification to the entire bank of differential I/Os that are located in the same side. This guarantee applies if the transmitter SERDES logic is placed within the LAB adjacent to the output pins.
- Constrain the transmitter SERDES logic to the LAB adjacent to the data output pins and clock output pins to improve the TCCS performance.
LVDS Receiver Debug and Troubleshooting
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Intel SignalTap® II Logic Analyzer to perform system level verification to correlate the system against your design targets.
Perform RTL Simulation Before Hardware Debug
For example, you can use the RTL simulation to verify that when you send a training pattern from a remote transmitter, the bitslipping mechanism in your LVDS receiver works.
Geometry-Based and Physics-Based I/O Rules
For more information, refer to the related information.
Intel MAX 10 LVDS Transmitter and Receiver Design
In a mixed transmitter and receiver implementation, the transmitter and receiver can share some FPGA resources.
Transmitter–Receiver Interfacing
LVDS Transmitter and Receiver FPGA Design Implementation
LVDS Transmitter and Receiver PLL Sharing Implementation
- Turn on the Use common PLL(s) for receivers and transmitters option to allow the Intel® Quartus® Prime compiler to share the same PLL.
- To share a PLL, several PLLs must have the same PLL settings, such as PLL feedback mode, clock frequency, and phase settings. The LVDS transmitters and receivers must use the same input clock frequency and reset input.
- If you are sharing a PLL, you can use more counters to enable different deserialization factor and data rates for the transmitters and receivers. However, because you are using more PLL counters, the PLL input clock frequency and the PLL counter resolution cause limitations in clocking the transmitters and receivers.
Initializing the Altera Soft LVDS IP Core
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the high-speed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Altera Soft LVDS IP core:
- Assert the pll_areset signal for at least 10 ns.
- After at least 10 ns, deassert the pll_areset signal.
-
Wait until the PLL
lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
LVDS Transmitter and Receiver Debug and Troubleshooting
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Intel SignalTap® II Logic Analyzer to perform system level verification to correlate the system against your design targets.
Perform RTL Simulation Before Hardware Debug
For example, you can use the RTL simulation to verify that when you send a training pattern from a remote transmitter, the bitslipping mechanism in your LVDS receiver works.
Geometry-Based and Physics-Based I/O Rules
For more information, refer to the related information.
Intel MAX 10 High-Speed LVDS Board Design Considerations
Guidelines: Improve Signal Quality
To improve signal quality, follow these board design guidelines:
- Base your board designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces.
- Maintain equal distance between traces in differential I/O standard pairs as much as possible. Routing the pair of traces close to each other maximizes the common-mode rejection ratio (CMRR).
- Keep the traces as short as possible to limit signal integrity issues. Longer traces have more inductance and capacitance.
- Place termination resistors as close to receiver input pins as possible.
- Use surface mount components.
- Avoid 90° corners on board traces.
- Use high-performance connectors.
- Design backplane and card traces so that trace impedance matches the impedance of the connector and termination.
- Keep an equal number of vias for both signal traces.
- Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the transmitter-channel-to-channel skew (TCCS) value increases.
- Limit vias because they cause discontinuities.
- Keep toggling single-ended I/O signals away from differential signals to avoid possible noise coupling.
- Do not route single-ended I/O clock signals to layers adjacent to differential signals.
- Analyze system-level signals.
Guidelines: Control Channel-to-Channel Skew
At the package level, you must control the LVDS I/O skew for each I/O bank and each side of the device. If you plan to vertically migrate from one device to another using the same board design, you must control the package migration skew for each migratable LVDS I/O pin.
For information about controlling the LVDS I/O and package skew, refer to the related information.
Guidelines: Determine Board Design Constraints
The time margin for the LVDS receiver (indicated by the RSKM value) is the timing budget allocation for board level effects such as:
- Skew—these factors cause board-level skew:
- Board trace lengths
- Connectors usage
- Parasitic circuits variations
- Jitter—jitter effects are derived from factors such as crosstalk.
- Noise—on board resources with imperfect power supplies and reference planes may also cause noise.
To ensure successful operation of the Altera Soft LVDS IP core receiver, do not exceed the timing budget.
Guidelines: Perform Board Level Simulations
The board-level simulation ensures optimum board setup where you can determine if the data window conforms to the input specification (electrical and timing) of the LVDS receiver.
You can use the programmable pre-emphasis feature on the true LVDS output buffers, for example, to compensate for the frequency-dependent attenuation of the transmission line. With this feature, you can maximize the data eye opening at the far end receiver especially on long transmission lines.
Altera Soft LVDS IP Core References
The Intel® Quartus® Prime software generates your customized Altera Soft LVDS IP core according to the parameter options that you set in the parameter editor.
Altera Soft LVDS Parameter Settings
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Power Supply Mode | — |
|
Specifies whether the target device is a single or dual supply device. |
Functional mode | — |
|
Specifies the functional mode for
the Altera Soft LVDS IP core:
|
Number of channels | — | 1–18 |
Specifies the number of LVDS channels. |
SERDES factor | — | 1, 2, 4, 5, 6, 7, 8, 9, 10 |
Specifies the number of bits per channel. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Use external PLL | Not applicable for x1 and x2 modes. |
|
Specifies whether the Altera Soft LVDS IP core generates a PLL or connects to a user-specified PLL. |
Data rate | — | Refer to the device datasheet. |
Specifies the data rate going out of the PLL. The multiplication value for the PLL is OUTPUT_DATA_RATE divided by INCLOCK_ PERIOD. |
Inclock frequency | — | Depends on Data rate. |
Specifies the input clock frequency to the PLL in MHz. |
Enable rx_locked port |
|
|
If turned on, enables the rx_locked port. |
Enable tx_locked port |
|
|
If turned on, enables the tx_locked port. |
Enable pll_areset port | Use external PLL = Off |
|
If turned on, enables the pll_areset port in internal PLL mode. In external PLL mode, the pll_areset port is not available. |
Enable tx_data_reset port |
|
|
If turned on, enables the tx_data_reset port. |
Enable rx_data_reset port |
|
|
If turned on, enables the rx_data_reset port. |
Use common PLL(s) for receivers and transmitters | Use external PLL = Off |
|
You can use common PLLs if you use the same input clock source, deserialization factor, pll_areset source, and data rates. |
Enable self-reset on loss lock in PLL | Use external PLL = Off |
|
If turned on, the PLL is reset when it loses lock. |
Desired transmitter inclock phase shift |
|
Depends on Data rate. |
Specifies the phase shift parameter used by the PLL for the transmitter. |
Desired receiver inclock phase shift |
|
Depends on Data rate. |
Specifies the phase shift parameter used by the PLL for the receiver. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Enable bitslip mode | General, Functional mode = RX |
|
If turned on, enables the rx_data_align port. |
Enable independent bitslip controls for each channel | General, Functional mode = RX |
|
If turned on, enables the rx_channel_data_align port. The rx_channel_data_align is an edge-sensitive bit slip control signal:
|
Enable rx_data_align_reset port |
|
|
If turned on, enables the rx_data_align_reset port. |
Add extra register for rx_data_align port |
|
|
If turned on, registers the rx_data_align port. If you turn this option off, you must pre-register the rx_data_align[] port in the logic that feeds the receiver. |
Bitslip rollover value |
|
1–11 |
Specifies the number of pulses before the circuitry restores the serial data latency to 0. |
Use RAM buffer | — |
|
If turned on, the Altera Soft LVDS IP core implements the output synchronization buffer in the embedded memory blocks. This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment. |
Use a multiplexer and synchronization register | — |
|
If turned on, the Altera Soft LVDS IP core implements a multiplexer instead of a buffer for output synchronization. |
Use logic element based RAM | — |
|
If turned on, the Altera Soft LVDS IP core implements the output synchronization buffer in the logic elements. This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment. |
Register outputs | General, Functional mode = RX |
|
If turned on, registers the rx_out[] port. If you turn this option off, you must pre-register the rx_out[] port in the logic that feeds the receiver. |
Parameter | Condition | Allowed Values | Description |
---|---|---|---|
Enable 'tx_outclock' output port |
|
|
If turned on, enables the tx_outclock port. Every tx_outclock signal goes through the shift register logic, except in the following parameter configurations:
|
Tx_outclock division factor |
|
Depends on SERDES factor. |
Specifies that the frequency of the tx_outclock signal is equal to the the transmitter output data rate divided by the selected division factor. |
Outclock duty cycle |
|
Depends on SERDES factor and Tx_outclock division factor. |
Specifies the external clock timing constraints. |
Desired transmitter outclock phase shift |
|
Depends on Data rate. |
Specifies the phase shift of the output clock relative to the input clock. |
Register 'tx_in' input port | General, Functional mode = TX |
|
If turned on, registers the tx_in[] port. If you turn this option off, you must pre-register the tx_in[] port in the logic that feeds the transmitter. |
Clock resource |
|
|
Specifies which clock resource registers the tx_in input port. |
Enable 'tx_coreclock' output port | General, Functional mode = TX |
|
If turned on, enables the tx_coreclock output port. |
Clock source for 'tx_coreclock' |
|
|
Specifies which clock resource drives the tx_coreclock output port. |
Altera Soft LVDS Interface Signals
Signal Name | Direction | Width (Bit) | Description |
---|---|---|---|
pll_areset | Input | 1 |
Asynchronously resets all counters to the initial values. |
tx_data_reset | Input | <n> |
Asynchronous reset for the shift registers, capture registers, and synchronization registers for all channels.
|
tx_in[] | Input | <m> |
This signal is parallel data that Altera Soft LVDS IP core transmits serially. Input data is synchronous to the tx_coreclock signal. The data bus width per channel is the same as the serialization factor (SF). |
tx_inclock | Input | 1 |
Reference clock input for the transmitter PLL. The parameter editor automatically selects the appropriate PLL multiplication factor based on the data and reference clock frequency. |
tx_coreclock | Output | 1 |
Output clock that feeds non-peripheral logic. FPGA fabric–transmitter interface clock—the parallel transmitter data generated in the FPGA fabric is clocked with this clock. |
tx_locked | Output | 1 |
Provides the LVDS PLL status:
|
tx_out[] | Output | <n> |
Serialized LVDS data output signal of <n> channels. tx_out[(<n>-1)..0] drives parallel data from tx_in[(<J> × <n>)-1 ..0] where <J> is the serialization factor and <n> is the number of channels. tx_out[0] drives data from tx_in[(<J>-1)..0]. tx_out[1] drives data from the next <J> number of bits on tx_in. |
tx_outclock | Output | 1 |
External reference clock. The frequency of this clock is programmable to be the same as the data rate. |
signal Name |
Direction |
Width (Bit) |
Description |
---|---|---|---|
rx_data_reset | Input | <n> |
Asynchronous reset for all channels, excluding the PLL.
|
rx_in[] | Input | <n> |
LVDS serial data input signal of <n> channels. rx_in[(<n>-1)..0] is deserialized and driven on rx_out[(<J> × <n>)-1 ..0] where <J> is the deserialization factor and <n> is the number of channels. rx_in[0] drives data to rx_out[(<J>-1)..0]. rx_in[1] drives data to the next <J> number of bits on rx_out. |
rx_inclock | Input | 1 |
LVDS reference input clock. The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection. |
rx_coreclk | Input | <n> |
LVDS reference input clock.
|
rx_locked | Output | 1 |
Provides the LVDS PLL status:
|
rx_out | Output | <m> |
Receiver parallel data output. The data bus width per channel is the same as the deserialization factor (DF). |
rx_outclock | Output | 1 |
Parallel output clock from the receiver PLL.
|
rx_data_align | Input | 1 |
Controls the byte alignment circuitry. You can register this signal using the rx_outclock signal. |
rx_data_align_reset | Input | 1 |
Resets the byte alignment circuitry. Use the rx_data_align_reset input signal if:
|
rx_channel_data_align | Input | <n> |
Controls byte alignment circuitry. |
rx_cda_reset | Input | <n> |
Asynchronous reset to the data realignment circuitry. This signal resets the data realignment block. The minimum pulse width requirement for this reset is one parallel clock cycle. |
Intel MAX 10 High-Speed LVDS I/O User Guide Archives
IP Core Version | User Guide |
---|---|
16.1 | MAX 10 High-Speed LVDS I/O User Guide |
16.0 | MAX 10 High-Speed LVDS I/O User Guide |
15.1 | MAX 10 High-Speed LVDS I/O User Guide |
15.0 | MAX 10 High-Speed LVDS I/O User Guide |
14.1 | MAX 10 High-Speed LVDS I/O User Guide |
Document Revision History for Intel MAX 10 High-Speed LVDS I/O User Guide
Date | Version | Changes |
---|---|---|
December 2017 | 2017.12.15 |
|
February 2017 | 2017.02.21 | Rebranded as Intel. |
October 2016 | 2016.10.31 |
|
May 2016 | 2016.05.02 |
|
November 2015 | 2015.11.02 |
|
May 2015 | 2015.05.04 |
|
December 2014 | 2014.12.15 |
|
September 2014 | 2014.09.22 | Initial release. |