The DisplayPort Intel® FPGA IP core design example
requires these components.
Table 1. Core System Components
Core System (Platform Designer)
The core system consists of the Nios II processor and its necessary
components, DisplayPort TX core sub-system and the Video and
Image Processing (VIP) FPGA IPs.
This system provides the infrastructure to interconnect the Nios II
processor with the DisplayPort Intel® FPGA IP core (TX instance)
through Avalon Memory Mapped (Avalon-MM) interface within a
single Platform Designer system to
ease the software build flow.
This system consists of:
VIP FPGA IPs
TX Sub-System (Platform Designer)
The TX sub-system consists of:
Clock Source—The clock source to the
DisplayPort TX core. This sub-system has two clock
sources integrated: 100 MHz and 16 MHz.
Reset Bridge—The bridge that connects
the external signal to the sub-system. This bridge
synchronizes to the respective clock source before it is
DisplayPort TX Core—DisplayPort Source
IP core, VESA DisplayPort
Standard version 1.4.
Debug FIFO—This FIFO captures all
DisplayPort TX auxiliary cycles, and prints out in the
Nios II Debug terminal. This component is only used when
parameter is turned on.
PIO—The parallel IO that triggers the
DPTX register update in software (tx_utils.c).
Avalon-MM Pipeline Bridge—This
Avalon-MM bridge interconnects the Avalon-MM interface
between components within the TX sub-system to the Nios
II processor in the Core sub-system.
Table 2. DisplayPort
PHY Top Components
TX PHY Top
The TX PHY top level consists of the components
related to the transmitter PHY layer.
Transceiver Native PHY(TX)—The transceiver block that receives 20-bit or 40-bit
parallel data from the DisplayPort Intel® FPGA IP core and
serializes the data before transmitting it. This block
supports up to 8.1 Gbps (HBR3)
data rate with 4 channels.
Note: You must set the TX channel bonding
mode to PMA and PCS
bonding and the PCS TX Channel bonding
master parameter to 0 (default is
Transceiver PHY Reset Controller—The TX
Reconfiguration Management module triggers the reset
input of this controller to generate the corresponding
analog and digital reset signals to the Transceiver
Native PHY block according to the reset sequencing.
TX Reconfiguration Management—This block reconfigures and
recalibrates the Transceiver Native PHY and TX PLL
blocks to transmit serial data in the required data
rates (RBR, HBR, HBR2, and
TX PLL—The transmitter PLL block
provides a fast serial fast clock to the Transceiver
Native PHY block. For the DisplayPort Intel® FPGA IP core design
Intel® uses transmitter
fractional PLL (FPLL).
Note: 8.1 Gbps is available only in the
Quartus® Prime Pro Edition software.
Table 3. Top-Level Common Blocks
IOPLL generates three common source clocks:
160 MHz—Used as main clock for Clocked Video Output II and Test
Pattern Generator II FPGA IPs.
16 MHz—Used as DisplayPort TX auxiliary clock.
MHz—Used as video clock for DisplayPort Intel® FPGA source and Clocked
Video Output II FPGA IP
1.2. Clocking Scheme
The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP core design example.
Table 4. Clocking Scheme Signals
Signal Name in Design
TX PLL Refclock
135 MHz TX PLL reference clock, that is
divisible by the transceiver for all DisplayPort data rates
(1.62 Gbps, 2.7 Gbps, and 5.4 Gbps).
Note: The reference clock source of the TX PLL
refclock is located at the HSSI refclk pin.
TX Transceiver Clockout
TX clock recovered from the transceiver, and
the frequency varies depending on the data rate and symbols
RBR (1.62 Gbps)
HBR (2.7 Gbps)
HBR2 (5.4 Gbps)
A free running 100 MHz clock for both Avalon-MM
interfaces for reconfiguration and PHY reset controller for
transceiver reset sequence.
100 – 125
Transceiver PHY reset controller
1 – 500
16 MHz Clock
MHz clock used to encode and decode auxiliary
channel in the DisplayPort Intel® FPGA source and sink IP
MHz calibration clock input that must be
synchronous to the Transceiver Reconfiguration module's
clock. This clock is used in the DisplayPort Intel® FPGA IP core's
TX Video Clock
Video clock frequency generated from IOPLL. A correct output clock frequency needs to be generated according to video format.
Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 0.
CVO Video Clock
video clock generated by the video PLL (148.5 MHz) to the
DisplayPort Intel® FPGA
MHz clock generated by the video PLL.
1.3. Top Level Interface Signals
The tables list the signals for the TX-only design
Table 5. Top-Level Signals
On-board Oscillator Signal
100 MHz clock source used as IOPLL reference
clock and Avalon-MM management clock
DisplayPort FMC Daughter Card Pins on FMC Port A
135 MHz dedicated transceiver reference clock
from FMC port A
DisplayPort TX serial data
Note:N = TX maximum
DisplayPort TX HPD
1 = HPD asserted
0 = HPD deasserted
DisplayPort TX Aux In
DisplayPort TX Aux Out
DisplayPort TX Aux OE
FMC card TX CAD
1.4. Quick Start Guide
The reference design features a hardware design that supports compilation and
1.4.1. Hardware and Software Requirements
To test the design, ensure that you have the appropriate hardware and
Arria® 10 GX FPGA Development Kit (10AX115S2F45I1SG)
Bitec FMC daughter card revision 5.0 or later
DisplayPort sink (monitor)
Quartus® Prime Pro Edition 18.1 (for hardware testing)
1.4.2. Compiling and Testing the Design
You can download the DisplayPort TX-only design file (A10_DP_TX_FMC_PRO.par) from the Intel Design Store.
To compile and run a demonstration test on the hardware
example design, follow these steps.
The .par file contains includes
pre-compiled .sof and .elf files that you can run to test the design.
To extract the files in the .par file, refer to the Installation Package instruction in the Intel Design Store design download page.
Extract and unzip the Additional_Files.zip file from the A10_DP_TX_FMC_PRO.par file, and move the Script and Software folder to the main project directory.
Quartus® Prime Pro Edition software and open <project directory>/quartus/top.qpf.
Bitec DisplayPort FMC daughter card revision 10 has schematic changes compared to revisions 8 and earlier. Revision 8 has lane reversal and polarity inversion at TX. To support all revisions, the design example top level RTL file at <project directory>/rtl/top.v file include a local parameter for you to select the FMC revision.
localparam BITEC_DP_CARD_REV = 0;
// 0 = Bitec FMC DP card rev.4 - 8,
// 1 = rev.9 or later
Open Nios II Command Shell and navigate to the Script folder.
Run the build_sw_sh script in the Nios II terminal to build the software.
Quartus® Prime Pro Edition software, click Processing > Start Compilation.
After successful compilation, the
Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
By default, the ELF file is generated
when you generate the dynamic design
some cases, you need to regenerate the ELF file if you modify the software file or
modify and regenerate the dp_core.qsys file.
Regenerating the dp_core.qsys file updates the
.sopcinfo file, which requires you to
regenerate the ELF file.
Go to <project directory>/software and edit the
code if necessary.
Go to <project directory>/script and execute the
following build script:
On Windows, search and open Nios II Command Shell. In
the Nios II Command Shell, go to <project
directory>/script and execute source build_sw.sh.
On Linux, launch the Platform Designer, and open
Tools > Nios II Command Shell. In the Nios II Command Shell, go to <project
directory>/script and execute source build_sw.sh.
Make sure an .elf file is
generated in <project
Download the generated .elf file into the FPGA without recompiling the .sof file by running the following script:
Push the reset button on the FPGA board for the new software to
1.4.3. Running the Hardware
Set up the hardware before you run the design on the
Arria® 10 development kit.
Figure 2. Arria 10 Development Kit Hardware Setup
Install the Bitec FMC daughter card at the FMC port A on the
Arria® 10 development kit.
Connect the DisplayPort TX connector on the Bitec FMC daughter
card to a video analyzer or DisplayPort sink device such as a monitor.
Ensure all MSEL switches on the development board are in default position.
Power up and connect the development board to your PC using a
micro USB cable.
Download the .sof file into the
FPGA device using
Quartus® Prime Programmer.
Push the Reset button on the
Arria® 10 development kit.
The DisplayPort sink device displays the video.
Figure 3. DisplayPort TX-only Design Output Video
Note: The hardware setup below uses ASUS MG28UQ monitor with Bitec FMC daughter
card revision 8 connected to
Arria® 10 FPGA development
kit. The monitor runs 4Kp60 color bar video generated by the Video and Image
Intel® FPGA IPs.
1.4.4. Design Debug Features
This design also
offers debugging features that are useful for debugging link up and no video output
184.108.40.206. Main Stream Attribute (MSA) Information
This debug feature enables you to check the MSA
This feature is a part of the DisplayPort TX-only design example. To display the (MSA of the DisplayPort TX core, type ‘S’ on the keyboard while in the Nios II terminal. The TX stream MSA values will appear on the Nios II terminal.
Figure 4. MSA Values on Nios II Terminal
Other Nios II Commands:
h - help
s - MSA Status
c- Read Sink DPCD CRC
v - Print versions
220.127.116.11. Auxiliary Channel Traffic Monitor
This debug feature enables you to check the auxiliary channel
This feature is also a part of the DisplayPort TX-only design example. To
display the auxiliary channel transaction on the Nios II terminal, set the BITEC_AUX_DEBUG flag in the config.h
file in the project folder to 1.
#define BITEC_AUX_DEBUG 1 // Set to 1 to enable AUX CH traffic monitoring
Rebuild the Nios II software and download the ELF image into the FPGA.
1.5. Creating the TX-only Design with Bitec FMC Daughter Card
You can create the DisplayPort TX-only design by making certain software and hardware modifications to the already provided DisplayPort SST parallel loopback with PCR design example. The steps below align with
Quartus® Prime Pro Edition 18.1 software release. For newer Quartus release, additional steps to create TX-only design may be needed.
1.5.1. Generating the Design
Before you make the modifications, first you need to generate the DisplayPort SST
Parallel Loopback design example in the
Quartus® Prime Pro Edition.
Instantiate the DisplayPort Intel® FPGA IP and specify the parameters.
Table 6. Example of IP Parameters Value to Generate a 4kp60 Output Video
Maximum video output color depth (Source)
This design supports GPU and monitors up to a maximum of 10 bit-per-color depth.
Maximum link rate
The bandwidth requirement for 4Kp60 and 10 bpc video stream through serial link:
Active video resolution = 3840 × 2160 pixels/frame
Total resolution (including reduced blanking) = 4000 × 2222 pixels/frame
Refresh rate = 60 Hz or 60 frames per second
Bits per pixel = 10 bpc × 3 colors = 30 bits per pixel
With 8b/10b encoding scheme, the actual bandwidth required = 15.9984 × 10/8 = 19.998 Gbps. With 4 lanes at 5.4 Gbps, the aggregated bandwidth of 21.6 Gbps is sufficient to support the 4K video stream at 60 Hz refresh rate.
Maximum lane count
Symbol output mode (Source)
Symbol mode affects the transceiver parallel bus width and the DisplayPort IP core clock frequency. The DisplayPort IP core synchronizes with the transceiver parallel clock. The parallel clock frequency is link rate/transceiver parallel bus width.
Frequency for HBR2 (5.4 Gbps) is 5400/20 or 270 MHz for dual (20 bits) and 5400/40 or 135 MHz for quad (40 bits) mode.
Symbol input mode (Sink)
Pixel input mode (Source)
Pixel mode affects the video clock frequency and video port width of the IP core.
For 4Kp60 video stream, the bandwidth requirement is 4000 × 2222 × 60 pixel/s = 533280000 pixels/s. Because of the high bandwidth requirement, the design requires dual or quad pixel mode for timing closure.
Single (1 pixel/clock) 533.28 MHz
Dual (2 pixels/clock) 266.64 MHz
Quad (4 pixels/clock) 133.32 MHz
Pixel output mode (Sink)
Support analog reconfiguration
Enable analog reconfiguration interface. Used to reconfigure vod and pre-emphasis value.
Enable AUX debug stream
Enable AUX source traffic output to Avalon-ST port
DisplayPort SST Parallel Loopback With PCR
Enable Pixel Clock Recovery in the design.
Note: The table above is an example of IP setting. However, Intel recommends you to generate a base example design with required IP setting (BPC, symbol per clock, pixel per clock, number of channels, link rate) and then proceed with the design modification. Changing the IP settings at the later stage can cause design conflict if not done properly.
Click Generate Example Design with
Arria® 10 GX FPGA Development kit as a target board.
1.5.2. Removing Irrelevant Blocks
Modify the generated design example by removing the irrelevant blocks
from the top-level design and from the dp_core.qsys
Remove the RX sub-system, RX PHY top.
Pixel Clock Recovery (PCR), and Transceiver Arbiter components (in gray), as shown in
the diagram below. These blocks are not needed for the TX-only design.
Figure 5. Components Required for the DisplayPort TX-only Design
18.104.22.168. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File
Below are detailed steps to remove the irrelevant blocks in top level file:
Module a10_dp_demo IO port modification:-
Remove Transceiver Data RX inputs - fmca_dp_m2c signals
Remove other RX signals (RX_HPD, RX Cable Detect, RX Power Detect and RX AUX Signals)
Remove Paratech Retimer signals (Bitec FMC Card Rev.8 or below)
DisplayPort Core Qsys system dp_core instantiation modifications;
Remove I2C Avalon Interface to Paratech/Megachip Retimer
Remove the DisplayPort Sink Sub-system
Remove rx_phy_top module instantiation.
Remove bitec_clkrec module instantiation
This module is only available if you generated DisplayPort design example with PCR
22.214.171.124. Removing Irrelevant Block in Platform Designer
Below are detailed steps to remove the irrelevant blocks in Platform Designer
From Quartus Project Navigator, double click to open dp_core system.
Remove dp_rx sub-system.
Remove unused RX components - dp_rx_clk_16 bridge and dp_rx_reset_bridge.
Note: Before generating HDL, save the changes in Platform Designer, Sync System Info and Validate System Integrity to ensure no errors were introduced.
1.5.3. Instantiating Video and Image Processing (VIP) Intel FPGA IPs
After removing irrelevant blocks in the design, instantiate the relevant Video and Image Processing FPGA IPs.
Instantiate the Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II
Intel® FPGA IPs in the Platform Designer and specify the parameters. The table below is an example of parameter value that generates a 4kp60 video.
Note: The Test Pattern Generator (TPG) II
Intel® FPGA IP generates video stream that displays color bars video pattern. The Clocked Video Output II
Intel® FPGA IP converts the Avalon-ST video format received from the TPG II
Intel® FPGA IP to standard clocked video format.
Note: Certain sink devices may not be able to accept below video resolution and settings. Contact sink device manufacturer for more information.
Table 7. Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II Parameter Settings
Clocked Video Output II
Note: The CVO II parameter setting is specific for 4K video resolution. For other video resolution, refer to VESA monitor timing standard specifications.
Image width / Active pixels
Image height / Active lines
Bits per pixel per color plane
Number of color planes
Number of pixels in parallel
Separate syncs only - Frame/ Field 1 Horizontal sync
Separate syncs only - Frame/ Field 1 Horizontal front porch
Separate syncs only - Frame/ Field 1 Horizontal back porch
Separate syncs only - Frame/ Field 1 Vertical sync
Separate syncs only - Frame/ Field 1 Vertical front porch
Separate syncs only - Frame/ Field 1 Vertical back porch
Pixel FIFO size
FIFO level at which to start output
Use control port
Test Pattern Generator II
Bits per color sample
Number of pixels in parallel
Color planes transmitted in parallel
Maximum frame width
Maximum frame height
Number of test patterns
Subsampling & Colorspace
Add Clock Bridge (160MHz clock input to TPG II and CVO II) for VIP and export out the input port.
Add Reset Bridge (active low reset with none synchronous edges) for VIP and export out the input port.
Connect the CVO II and TPG II
Intel® FPGA IP instances in the Platform Designer.
Figure 6. Connecting the CVO II and TPG II in the Platform Designer
Note: The CVO II and TPG II
Intel® FPGA IPs share the reset input from the reset generator output. Ensure the Clocked Video Port of CVO II FPGA IP signals are exported out from Platform Designer.
Save the changes, run Sync System Info & Validate System Integrity. After that, proceed to Generate HDL.
Note: By adding TPG II, CVO II, Clock and Reset Bridge in the system, design top level instantiations of dp_core modules needs to be updated. Refer to the Instantiation Template in Platform Designer and update your top level instantiation accordingly.
Note: Ensure the TPG II, CVO II, Clock and Reset Bridge are listed in the Quartus Project Navigator. If it is not available, manually add the IPs in the Quartus Settings > Files.
At the top level design file, connect the signals in the DisplayPort TX sub-system as shown below.
Figure 7. Video PLL with Tx_vid_clk output
Note: The CVO II and TPG II
Intel® FPGA IPs share the reset input from the reset generator output (reset_n), through VIP Reset Bridge.
1.5.4. Generated Clocks
Apart from the default clocking scheme in the generated design example, you need to generate an additional output clock from the video PLL. To do that, double click on video_pll_a10.ip on Quartus Project Navigator to open IP Parameter Editor.
160 MHz output clock that acts as the main clock for CVO II and TPG II FPGA IP instances through VIP Clock Bridge.
16 MHz output clock for DisplayPort Source 1 Mbps AUX channel interface.
148.5 MHz output clock for DisplayPort TX and CVO II video clocks.
Note: The 148.5 MHz clock frequency supports the native 4K or UHD resolution video output. Other video formats may run at different clock frequency.
After you make the changes, click Save and Generate HDL.
1.5.5. Making a Direct Connection to the TX Transceiver Block
dynamic DisplayPort parallel SST loopback with PCR design example uses the
Transceiver Arbiter to share between an RX and TX transceiver within the same channel.
As the TX-only design only requires the TX transceiver, you
need to remove the Transceiver Arbiter and make a direct connection to the TX
Before you make the connection, in the Platform Designer turn on the Share Reconfiguration Interface parameter in the Transceiver Native PHY block to allow for single Avalon-MM slave interface for dynamic reconfiguration of all channels.
Update the transceiver signal width as shown below in the design top-level and the tx_phy_top.v files.
Table 9. TX Transceiver Signals
Make a direct connection from the Bitec Reconfig block to the TX transceiver block in the tx_phy_top.v file as shown in the diagram below.
Figure 8. Bitec Reconfig and TX Transceiver Block Connection
Remove the following Transceiver Reconfig Group assignments from the
Quartus® Prime Settings File (qsf).
After removing the irrelevant blocks and reconnecting the remaining
blocks with the newly instantiated FPGA IPs, modify the software.
First, modify the software's config.h file. Navigate to the design example folder and change the values of the following parameter settings in the file.
Table 10. Config.h Parameter Settings
Set to 1 to enable AUX channel traffic monitoring.
Set to 1 to enable MSA and link status monitoring.
Set to 1 if the DisplayPort supports RX.
Set to 1 to enable Sink GPU mode.
Set to 1 to enable MST support.
Set to 1 to enable Fast Link Training support.
Set to 1 to enable Link Quality Analysis support.
Set to 1 to use an EDID with maximum resolution 800 x 600
Set to 1 to enable MST support
Set to 1 if DisplayPort supports TX
Set to 1 to enable MST support
Set to 1 to enable TX Video IM interface
Set to 1 to enable EDID passthrough from sink to source.
Set to 0 = Bitec FMC DisplayPort daughter card revision 4 – 8 (without Paradetech Retimer)
Set to 1 = Bitec FMC DisplayPort daughter card revision 9 or later (with Paradetech Retimer)
RX MST number of streams
TX MST number of streams
Note: You must select a correct Bitec FMC DisplayPort daughtercard revision. Make the selection in the Config.h and design top level file.
Since DisplayPort TX-only design does not require a retimer at RX, remove below code in the software/dp_demo/Main.c.
#if (BITEC_DP_CARD_REV == 1)
// Bitec Daughter Card Rev 10
// Init the PS8460 I2C interface
// Set the PS8460 P4 registers
// Set the PS8460 equaliser as required by your design
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x09, 0x02);
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0B, 0xC4); // Enable EQ from I2C register,squelch enabled
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0C, 0x55); // HBR RBR EQ
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0D, 0x85); // HBR2 EQ
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0E, 0x05); // HBR3 EQ
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9A, 0x88); // L1_VOD L1_PRE L0_VOD L0_PRE
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9B, 0x88); // L3_VOD L3_PRE L2_VOD L2_PRE
intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0xA4, 0x08); // Full Jitter cleaning mode
#if (BITEC_DP_CARD_REV == 2)
// Bitec Daughter Card Rev 11
unsigned int data;
// Init the MCDP6000 on the Bitec Sink main link input
// (on the Bitec daughter board)
// Set the MCDP6000 as required by your design
data = 0x0001704E; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0504, (unsigned char *)&data, 4);
data = 0x00000601; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x01D8, (unsigned char *)&data, 4);
data = 0x00005011; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0660, (unsigned char *)&data, 4);
data = 0x00000001; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x067C, (unsigned char *)&data, 4);
data = 0x55801E14; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0A00, (unsigned char *)&data, 4); // MC solution #2
data = 0x0000001F; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0350, (unsigned char *)&data, 4); // MC solution #3
Quartus® Prime Pro Edition software, the bitec_dptx_init() function is only called when DP_SUPPORT_EDID_PASSTHRU is enabled in Config.h. Since DP_SUPPORT_EDID_PASSTHRU is not needed for this design, DP TX will never get initialized. To avoid this, bring out the bitec_dptx_init() function from the #if DP_SUPPORT_EDID_PASSTHRU directive so that the function can run. For example:
Remove the bitec_dp_dump_sink_msa() and bitec_dp_dump_sink_config() from the Main.c.
Next, for debugging purposes, modify the debug.c file located in the software/dp_demo folder. Open the debug.c file and remove the void bitec_dp_dump_sink_msa() and void bitec_dp_dump_sink_config() functions.
Note: Any modifications you make in the debug.c and Main.c, the script will be overwritten each time you rebuild the software. To prevent this, place a copy of the modified Main.c and debug.c file in the main software folder before you rebuild your software.
In a Nios II Command Shell, cd into the script directory and ‘source build_sw.sh’ to update software. The updated dp_demo.elf file is located in the software/dp_demo directory.
After you make any change to the software (ie: config.h or any other software file), you must run build_sw.sh script from a nios2-terminal to ensure the software (dp_demo.elf) file is accurate.
The IP components in the Platform Designer are utilized in the generation of the BSP (Board Support Package). For this reason, it is also imperative to regenerate software if you make any changes or updates within the Platform Designer dp_core system as well.
If design has already been compiled and a10_dp_demo.sof image previously generated, load dp_demo.elf from a nios2 command shell and run ‘nios2-download dp_demo.elf’ in the Nios terminal. Use push button reset on the
Arria® 10 GX development kit for software changes to take effect.
1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
Edited the Description for TX Video Clock in Table: Clocking Scheme Signals.
Added the steps to extract the files in the .par file in Compiling and Testing the Design.
Added the software version 18.1 for
Quartus® Prime Pro Edition in Creating the TX-only Design with Bitec FMC Daughter Card.
Added a note and renamed Table: Example of IP Parameters Value to Generate a 4kp60 Output Video.
Added subtopic Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File and Removing Irrelevant Block in Platform Designer in section Removing Irrelevant Blocks.
Edited the Instantiating Video and Image Processing (VIP) Intel FPGA IPs.
Changed the Value from 8 to 10 for Bits per pixel per color plane in Table: Clocked Video Output (CVO) II and Test Pattern Generator (TPG) IIParameter Settings.
Edited Figure: Connecting CVO II Intel FPGA IP to the DisplayPort TX Sub-system.
Added Figure: Video PLL with tx_vid_clk output.
Added a new column Signal Name in the Table: DisplayPort TX-only Design Generated Clocks.
Changed Figure: Bitec Reconfig and TX Transceiver Block Connection.