1. Signal Integrity (SI) in High-Speed PCB Designs
Many factors impact
for example, insertion
deviation (ILD), return loss, crosstalk, and mode conversion. To mitigate
these factors, you must first determine the loss budget for your targeted protocol. Second,
materials and a stackup design that allow you to stay under your loss budget. Then design
your PCB with these
materials, and run
channel compliance analysis.
final steps are post-layout model extraction and end-to-end system
Use IBIS-AMI models
BER of your targeted protocol.
more details about IBIS-AMI models, contact My Intel support.
Figure 1. Signal Integrity Flow in High-Speed PCB Designs
supported protocols, refer to the
FPGA Device Overview. For device characteristics, refer to the
Device Data Sheet.
For transceiver details, refer to the E-Tile Transceiver PHY User
Guide. For protocol-specific layout requirements, refer to the relevant protocol
1.2. Channel Insertion Loss (IL) Budget Calculation
The following figure is an example of a channel IL budget calculation for an
end-to-end (TP0 to TP5) 200GBASE-CR4 channel, with the IL estimation at the Nyquist
frequency for each channel
the minimum and maximum insertion loss allocations for each
of the channel (from the transmitter to the receiver) to meet the link standard (for
example, IEEE 802.3cd).
Figure 2. 200GBase-CR4 End-to-End Channel IL Estimation ExampleAssign a few dB of margin to the end-to-end channel PCB design to account for PCB and
process, voltage, and temperature (PVT) variations.
1.3. PCB Materials and Stackup Design Guidelines
stackup is the substrate upon which all design components are assembled. A well-designed
PCB stackup can maximize the electrical performance of signal transmissions, power
delivery, manufacturability, and long-term reliability of the finished product.
You need to know the following in order to decide
required number of signal and power layers.
Board thickness requirements
for example, gold finger or edge finger
PCB manufacturing capability limitations
Your critical devices and their placement requirements
High-speed signal data rate and connection requirements
The power tree and power budget for each power rail
1.3.1. Mitigating Insertion Loss with Dielectric Material
like E-tile to the quad small form factor pluggable double-density (QSFP-DD) interface
and P-tile to the gold finger interface in a
) add-in card have very strict IL
requirements. Use the following dielectric constant (Dk) and dissipation factor (Df)
values as a reference only for low-loss and ultra-low-loss dielectric materials. Test
your design with a vector network analyzer (VNA).
Dk =3.5 and Df =0.007 (at 1 GHz) for low-loss material
Dk =3.4 and Df =0.002 (at 1 GHz) for ultra-low-loss material
low-surface-roughness copper materials such as very low profile (VLP)
hyper very low profile (HVLP)
mitigate insertion loss caused by the skin effect. Copper resistance is a function of
frequency, so, as the frequency increases, the resistive loss increases because of the
skin depth (δ). This skin effect reduces the cross-sectional area of the channel,
increasing the copper resistance.
dielectric material (with the corresponding wider traces) for high-speed differential
channel routing layers.
trace widths increase the effective surface area and reduce the skin
1.3.2. Power Layers
For details about designing your power distribution network (PDN), see the
Device Power Distribution Network PCB Design User Guide.
Use 1 or 2 oz.
copper foil where possible to provide a stronger current carrying
capability in the same routing space.
For high current power rails, like the core power rail which may carry a
current of more than 100 A, use multi-layers in parallel.
in multiple planes for a single supply,
enough stitching vias for the power planes to provide a low resistance vertical
Place power layers next to a ground layers to create planar capacitance,
which aids high-frequency decoupling, reduces electromagnetic interference (EMI)
radiation, and enhances electromagnetic compliance (EMC) robustness. Because planar
capacitance is inversely proportional to the dielectric thickness between the power and
ground planes, choose thin dielectrics between the power and ground planes to increase
the planar capacitance while reducing planar spreading inductance.
Make sure all high-speed signals reference
solid planes over the length of their routing (ground reference is
preferred) and do not cross plane splits.
signal layers to provide good isolation and reference.
1.3.4. Layer Assignment
For high-speed differential traces, avoid long via coupling between the
transmit (TX) and receive (RX) transceiver channels.
Make sure the via coupling length is as short as possible to reduce
impedance tolerance of high-speed traces. Generally, ten percent can
be used for stripline impedance, but seven percent is better.
Breakout routing usually has limited routing space which may cause
impedance discontinuity. Optimize breakout routing trace geometries to reduce the
impedance discontinuity for better return loss performance.
1.3.6. Via Drill Size
The aspect ratio (AR) is the ratio of a via length or depth to its drill
hole diameter. An AR of 15 is a common manufacturing capability
by PCB vendors, but
vendors define the exact AR based on the board thickness specified by their
the target differential via impedance, the optimized anti-pad size is usually larger
than the default via anti-pad which may cause a reference issue for breakout routing in
the BGA area.
via impedance with time domain reflectometry (TDR), and use a teardrop or wider trace
segment in the breakout area for a smooth impedance transition to the global
1.3.7. Fiber Weave
composite of fiber and resin make up
of fiber run perpendicular to each other. Depending on the orientation
of the weave relative to the trace, there can be a resin or a fiber bundle beneath the
differing dielectric constants of these two
may introduce a phase skew
signals that comprise a differential pair, manifesting itself as an AC common mode noise
at the receiver, affecting both the voltage and timing margin at the receiver. This is
fiber weave effect. To mitigate the fiber weave effect, specify a dense spread of weave
(1078, 1067, 2116, 2113) rather than a sparse weave (106, 1080) for prepreg1 and core.
2-ply (1078x2, 1078+1067) prepreg and core
mitigate the fiber weave effect.
For more details about the fiber weave effect, refer to AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on
High-Speed Channel Routing.
1 "Prepreg" is an abbreviation of "pre-impregnated material," in this
case, referring to the PCB fiberglass impregnated with resin (an epoxy-based
in multilayer boards.
1.3.8. Reference Stackup
The following figure
example. With 18 layers, it is a total of 62 mils thick. It has two 1 oz
power layers at the center of the stackup, isolated with two ground layers on each side.
The ground-signal-ground layer pattern is used for all signal layers, and a dense weave
(1078, 1035) prepreg and core were used for dielectric prepreg and core.
Figure 3. 18-layer Add-in Card Reference Stackup
1.4. PCB Design Guidelines
1.4.1. General PCB Design Guidelines
in a high-speed channel can impact the overall system performance. From end-to-end, these
are the device packages, PCB traces, PCB vias, connectors,
landing pads of integrated circuit pins, connector pins, and alternating current (AC)
coupling capacitor pins.
188.8.131.52. PCB Traces
better far end crosstalk performance and a tight impedance tolerance, and
than the maximum allowed length limited by the full-channel IL and eye diagram
Follow the general stripline pair-to-pair spacing rule of 5H for
TX-to-TX and RX-to-RX, 9H for TX-to-RX, TX-to-others, and RX-to-others, where 'H' is the
dielectric distance from the signal layer to the closest reference layer.
a solid ground reference for high-speed differential pairs.
Keep at least 5H of spacing
the edge of a trace
the void and
between the edge
of a trace and the edge of the reference
plane in the open
Maintain symmetrical routing between two signals that comprise a
differential pair from end to end, including the trace length, the transition via
location, and the placement of DC blocking capacitors. Failure to maintain layout
or common-to-differential-mode conversion AC
Figure 4. Symmetrical and Non-symmetrical Routing Examples
Breakout routing usually has a
trace width and
pair-to-pair spacing, so keep the breakout routing as short as possible to minimize
insertion loss and reduce crosstalk.
To mitigate near end crosstalk, route the high-speed TX and RX signals
on different layers, or separate the TX and RX signals with large spacing of at least 9H
in the stripline layer.
In the BGA pin field via array, avoid high-speed traces routed between
two vias that comprise a differential via, and
the coupling area between
high-speed trace and via
small as possible. Follow the guidelines in the following figure to minimize crosstalk
in the pin field area. Note that each differential pair has a short bar connecting the P
in the figure to indicate the differential via.
Figure 5. Routing Rule in Hex Pattern Pin Field Via Array
Figure 6. Breakout Routing Example of Hex Pattern BGA
To increase the common mode noise immunity,
differential pair P/N deskew
and compensate for the skew after the skew happens and close to the point where the
Figure 7. Intra-pair Deskew Close to the Skew Happened Location
them transparent to the signal,
discontinuity to the differential
can minimize them by making
shorter than the signal rise time. In general, keep the serpentine routing length
<100 mils with arcs and bends of
loosely coupled differential pair is less affected by serpentine
Figure 8. Deskew Trombone Routing Rule
Do not use
coupled high-speed differential pairs
a given routing density because
increases the impedance fluctuation caused by the deskew trombone and
manufacturing tolerance. The general rule for intra-pair spacing is between one and two
times the trace width.
high-speed differential traces.
high-speed differential traces in the pad and via area.
fiber weave effect with
like zig-zag routing and image
The following figure shows zig-zag routing. If the weave is aligned to the
PCB edges, follow a zig-zag routing of differential traces. Generally, maintain a minimum
angle of 10 degrees between the trace and fiber weave; this
to the PCB edge. For
more details about the fiber weave effect, refer to AN 528: PCB
Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel
Figure 9. Zig-Zag Routing
Another solution is image rotation that maintains an angle between the
trace and the fiber weave pattern. Rotate until the traces are at a 10 degree angle
relative to the fiber weave. Rotate
cutting the PCB board at an angle, as shown in following figure, or by rotating the layout
database relative to the edge of the PCB board.
Figure 10. Cutting the
Relative to the Fiber Weave Pattern
Vias impact high-speed channel loss and the jitter budget, so use as few vias as
possible for the high-speed differential channel.
Keep impedance continuity between
and trace. Vias usually have
impedance than traces.
Optimize via impedance, using a 3D electromagnetic (EM) solver, by
sweeping the anti-pad width, length, and radius for your specific stackup, drill size,
and via stub. Keep in mind that:
The smaller the drill size, the higher the via impedance
The larger the anti-pad size, the higher the via impedance
The shorter the via stub, the higher the via impedance
The smaller the via top, bottom, and functional pads, the higher
Figure 11. Hex Pattern BGA Via Optimization
each high-speed signal via has a ground via for reference, and
make sure that
the two signal vias of a differential pair
as the above figure shows.
you do not do this, mode conversion is introduced.
Remove non-functional pads for high-speed signal vias and
closest TX and RX signal via coupling length
short as possible
an appropriate layer assignment.
Figure 12. Via Coupling Reduction by Routing Layer Assignment
is a resonance
can occur in
range of three times the Nyquist
Control the via
stub length to avoid this.
184.108.40.206. Connector Breakout
For high-speed routing, use the correct breakout orientation to avoid long stubs caused by
the connector pin and PCB pad.
Figure 13. Connector Pin and PCB Pad ConnectionThis is a surface-mount, ground-signal-signal-ground connector pin
interconnection with the PCB. The different layers in the stackup are indicated with
Optimize and tune
reach the target trace impedance and
To test the
interaction between the connector pin and PCB pad, co-simulate the connector-to-PCB
the connector structures included in a 3D EM simulation
220.127.116.11. DC Blocking Capacitor
of DC blocking capacitors can impact high-speed channel
Use a 0402 or 0201 size capacitor for a smaller parasitic and smaller footprint.
Place the DC blocking capacitors at the device end or connector end. Do
not place them in the middle of the
Keep the placement of the DC blocking capacitors on the two lines of a
differential pair symmetrical, make sure
the capacitors is symmetric, and make sure the line lengths on either side of the
Similar to the connector
the cut-out size under the capacitor pad
a 3D EM simulation
your specific stackup and
pad size. Some
basic rules to start with:
Cut the direct, next-layer ground plane of the capacitor
Keep a gap greater than 1H between the edge of the AC capacitor
pad and the adjacent ground planes.
Figure 14. DC Blocking Capacitor Layout
Do not route high-speed differential traces under power connectors, power delivery
inductors, other interface connectors, crystals, oscillators, clock synthesizers,
magnetic devices, or integrated circuits that use or duplicate clocks.
Keep large spacing between high-speed traces, vias, and pads and high-noise power nets,
a spacing of greater than 100 mils is preferred. High-noise power nets are nets like the
switching node (phase node) of a voltage regulator module (VRM), 12 V power net, and
high current transient power net.
If a dog-bone fan-out was used in the BGA pin area, use a ground reference plane cutout
under the high-speed signal pad to reduce the capacitance.
1.4.2. E-Tile and H-Tile PCB Design Guidelines
trace impedance of 90-100 Ω for
The normal package impedance of the
is 90 Ω.
that support 56G PAM4
shallow layers to
reduce via length, with connectors placed on the PCB close to the FPGA
short as possible.
buried via, blind
necessary to shorten the via stubs. Stub lengths
less than 10 mils are recommended.
Only: Use layer assignment to keep
coupling length of the closest
and RX vias
A coupling length including via stubs
less than 56 mils is recommended.
ground reference vias
the package edge
pairs in order
reference via symmetry for the two signal vias that comprise a differential pair.
Figure 15. Adding Reference Ground Vias for Package Edge
Make sure that
on the side that
toward the FPGA rather than the side that faces the board edge to
avoid the long stub caused by the connector pin and PCB pad. For the QSFP-DD connector
and PCB pad connection, refer to the following
Figure 16. QSFP-DD Connector and PCB Connection
Figure 17. QSFP-DD Transition Via Layout
The zQSFP+ connector has
different connection compared to a QSFP-DD connector as shown in the
the periphery of the zQSFP+
Figure 18. zQSFP+ Connector and PCB Connection
Figure 19. zQSFP+ Transition Via Layout
both sides of the connector ground pin and
with short, thick ground trace
order to minimize the inductance of the ground
shown in the figure below.
Figure 20. zQSFP+ Connector Ground Pin Layout
1.4.3. P-Tile PCB Design Guidelines
add-in-card designs, the insertion loss from the top
edge finger to the silicon pad
package insertion loss
the silicon loss)
for both the
receiver and transmitter interconnect must not exceed 8 dB at 8 GHz.
P-tile package plus silicon loss is under 3 dB, you may have an add-in-card PCB loss
under 5 dB.
an insertion loss of 28 dB including the transmitter and receiver
packages as the reference value maximum for end-to-end channel design, but
the final design
completed channel simulation and measurements.
impedance of 85 Ω
P-tile differential channels.
via stubs as short as possible. Use top-drill, back-drill, buried via, blind via, and
micro-via techniques as necessary to shorten the via stubs. Stub lengths of less than 30
mils are recommended.
additional ground reference vias for the package edge differential pairs in order to
keep ground reference via symmetry for the two signal vias that comprise a differential
DC blocking capacitors on TX channels
to the FPGA or connector.
the middle of the trace
slot connector footprint
cutting the ground planes beneath the connector PCB pad, considering the
connector pin and PCB pad, for less return loss.
Make sure that
the periphery of the connector as shown below to avoid
long stub caused by the connector pin and PCB pad.
Slot Connector and PCB Pad
Slot Connector Breakout
Gen4 16.0 GT/s,
make sure that
no inner-layer conductors of any kind, including ground or power
planes, beneath the edge-fingers (for a distance of 15 mils).
You may add
any of the edge fingers if they extend no more than 2 mm into the edge finger region
from the main routing area of the board and are at a depth of
least 15 mils (0.38 mm) beneath the edge finger copper pads on the
surface of the PCB.
Figure 23. Add-in Card Edge-finger Regions with Allowed Inner Layer Plane Volume
For add-in-card ground fingers,
make sure that
the distance between a horizontal line across the top edge ground
fingers and a horizontal line across the bottom edge of the ground via pads
not exceed 15 mils.
the adjacent edge-fingers at the lowered via location
provide additional improvement in the ground resonance.
Figure 24. Add-in-card Ground Finger Layout
1.5. Document Revision History for the Intel Agilex Device Family High-Speed Serial Interface Signal Integrity Design Guidelines