25G Ethernet Intel FPGA IP Release Notes

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RN-1140 | 2020.04.13

1. 25G Ethernet Intel FPGA IP Release Notes

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel^® Quartus^® Prime Design Suite Update Release Notes.

IP versions are the same as the Intel^® Quartus^® Prime Design Suite software versions up to v19.1. From Intel^® Quartus^® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:

X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

1.1. 25G Ethernet Intel FPGA IP v19.4.0

Table 1. v19.4.0 2019.12.16
Intel^® Quartus^® Prime Version	Description	Impact
19.4	`rx_am_lock` behavior change: In previous versions of the 25G Ethernet Intel^® FPGA IP, the `rx_am_lock` signal behaves the same as `rx_block_lock` across all variants. In this version, for RSFEC enabled variants of the IP, `rx_am_lock` now asserts when alignment lock is achieved. For non-RSFEC enabled variants, `rx_am_lock` still behaves the same as `rx_block_lock`.	The interface signal, `rx_am_lock`, behaves differently from the previous versions for the RSFEC-enabled variants.
	Updated the RX MAC Start of Packet: In previous versions, the RX MAC only checks for a START character to determine the start of a packet. In this version, the RX MAC now checks for incoming packets for Start of Frame Delimiter (SFD), in addition to the START character by default. If the preamble pass-through mode is enabled, the MAC checks only for the START character to allow for custom preamble.	—
	Added a new register to enable preamble checking: In the RX MAC registers, the register at offset 0x50A [4] can be written to 1 to enable the preamble checking. This register is a "don't care" when the preamble pass-through is enabled.	—

1.2. 25G Ethernet Intel FPGA IP v19.3.0

Table 2. v19.3.0 2019.09.30
Intel^® Quartus^® Prime Version	Description	Impact
19.3	For a MAC+PCS+PMA variant, the transceiver wrapper module name is now dynamically generated. This prevents unwanted module collision if multiple instances of the IP are being used in a system.	—

1.3. 25G Ethernet Intel FPGA IP v19.2.0

Table 3. v19.2.0 2019.07.01
Intel^® Quartus^® Prime Version	Description	Impact
19.2	Design Example for 25G Ethernet Intel^® FPGA IP: Updated the target development kit option for Intel^® Stratix^® 10 devices from Intel^® Stratix^® 10 L-Tile GX Transceiver Signal Integrity Development Kit to Intel^® Stratix^® 10 10 GX Signal Integrity L-Tile (Production) Development Kit.	—

1.4. 25G Ethernet Intel FPGA IP v19.1

Table 4. v19.1 April 2019
Description	Impact
Added a new feature—Adaptive mode for RX PMA Adaptation: Added a new parameter—Enable auto adaptation triggering for RX PMA CTLE/DFE mode.	These changes are optional. If you do not upgrade your IP core, it does not have this new feature.
Renamed the Enable Altera Debug Master Endpoint (ADME) parameter to Enable Native PHY Debug Master Endpoint (NPDME) as per Intel^® rebranding in the Intel^® Quartus^® Prime Pro Edition software. The Intel^® Quartus^® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint (ADME).	—

1.5. 25G Ethernet Intel FPGA IP v18.1

Table 5. Version 18.1 September 2018
Description	Impact
Added a new feature—Elective PMA: Added a new parameter—Core Variants.	These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added a new signal for 1588 Precision Time Protocol Interface—`latency_sclk`.
Design Example for 25G Ethernet Intel^® FPGA IP: Renamed the target development kit option for Intel^® Stratix^® 10 devices from Stratix^® 10 GX FPGA Development Kit to Stratix^® 10 L-Tile GX Transceiver Signal Integrity Development Kit.	—

1.6. 25G Ethernet Intel FPGA IP v18.0

Table 6. Version 18.0 May 2018
Description	Impact
Added support for the Intel^® Stratix^® 10 device family.	—

1.7. 25G Ethernet IP Core v17.0

Table 7. Version 17.0 May 2017
Description	Impact
Added shadow feature for reading statistics registers. In TX statistics registers, replaced the `CLEAR_TX_STATS` register at offset 0x845 with new `CNTR_TX_CONFIG` register. The new register adds a shadow request and a parity-error clear bit to the bit that clears all TX statistics registers. Added new `CNTR_RX_STATUS` register at offset 0x846, that includes a parity-error bit and a status bit for the shadow request. In RX statistics registers, replaced the `CLEAR_RX_STATS` register at offset 0x945 with new `CNTR_RX_CONFIG` register.The new register adds a shadow request and a parity-error clear bit to the bit that clears all TX statistics registers. Added new `CNTR_TX_STATUS` register at offset 0x946, that includes a parity-error bit and a status bit for the shadow request.	The new feature supports improved reliability in statistics counter reads. To read a statistics counter, first set the shadow request bit for that set of registers (RX or TX), and then read from a snapshot of the register. The read values stop incrementing while the shadow feature is in effect, but the underlying counters continue to increment. After you reset the request, the counters resume their accumulated values. In addition, the new register fields include parity-error status and clear bits.
Modified RS-FEC alignment marker format to comply with the now-finalized Clause 108 of the IEEE 802.3by specification. Previously the RS-FEC feature complied with the 25G/50G Consortium Schedule 3, prior to IEEE specification finalization.	The RX RS-FEC now detects and locks to both the old and new alignment markers, but the TX RS-FEC generates only the new IEEE alignment marker format.

1.8. 25G Ethernet IP Core v16.1

Table 8. Version 16.1 October 2016
Description	Impact
Initial release in the Intel FPGA IP Library.	—

1.9. 25G Ethernet Intel Stratix 10 FPGA IP User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version	User Guide
19.4.0	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide
19.3.0	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide
19.2.0	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide
19.1	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide
18.1	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide
18.0	25G Ethernet Intel^® Stratix^® 10 FPGA IP User Guide

1.10. 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version	User Guide
19.1	25G Ethernet Intel^® Stratix^® 10 FPGA IP Design Example User Guide
18.1	25G Ethernet Intel^® Stratix^® 10 FPGA IP Design Example User Guide
18.0	25G Ethernet Intel^® Stratix^® 10 FPGA IP Design Example User Guide