This section lists and describes the contents of the Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit.

The Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit includes the following hardware:

• Intel^® Arria^® 10 GX transceiver signal integrity development board—A development platform that allows you to develop and prototype hardware designs running on the Intel^® Arria^® 10 GX FPGA device.
• Power supply and cables—The kit includes the following items:
  • Power supply and AC adapters for North America, Japan, Europe and the United Kingdom
  • USB type A to B cable
  • Ethernet cable

The new Intel^® Quartus^® Prime design software includes everything needed to design for Altera FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation. The Intel^® Quartus^® Prime software includes an additional Spectra-Q^® engine that is optimized for future devices. The Spectra-Q^® engine enables new levels of design productivity for next generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure and a unified compiler technology.

Included in the Intel^® Quartus^® Prime Pro Edition are the Intel^® Quartus^® Prime software, Nios^® II EDS and the MegaCore^® IP Library. To install Altera's development tools, download the Intel^® Quartus^® Prime Pro Edition software from this web page in the Download Center of Altera's website.

The license-free Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit package contains Design Examples, Board Test System (BTS), Development Kit schematics, Development Kit Board files, User Guide, Quick Start Guide and Bill of Materials (BoM).

When handling the board, it is important to observe static discharge precautions.

Before using the kit or installing the software, check the development kit contents and inspect the board to verify that you received all of the items listed in “Development Kit Features". If any of the items are missing, contact Altera before you proceed.

Purchasing this kit entitles you to a one-year license for the Development Kit Edition (DKE) of the Intel^® Quartus^® Prime software. After one year, your DKE license will no longer be valid and you will not be permitted to use this version of the Intel^® Quartus^® Prime software. To continue using the Intel^® Quartus^® Prime software, you should download the free Intel^® Quartus^® Prime Lite Edition or purchase a paid license for the Intel^® Quartus^® Prime Pro Edition.

The Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit includes integrated USB-Blaster circuitry for FPGA programming. However, for the host computer and board to communicate, you must install the USB-Blaster driver on the host computer.

Installation instructions for the USB-Blaster driver for your operating system are available on the Altera website. On the Altera Cable and Adapter Drivers Information web page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.

The development board features the Intel^® Arria^® 10 GX115 FPGA (10AX115F1932C).

The Intel^® Arria^® 10 transceiver development kit consists of a MAX^® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX^® V CPLD devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring, FPGA configuration, and analog IC interface. MAX^® V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX^® V CPLDs can help you meet your low power design requirement.

This section describes the FPGA, flash memory, and MAX^® V CPLD System Controller device programming methods supported by the Intel^® Arria^® 10 GX transceiver signal integrity development board.

The embedded USB Blaster core for USB-based configuration of the Intel^® Arria^® 10 GX FPGA device is implemented using a TYPE B USB connector, a CY7C68013A USB2 PHY device, and an Altera MAX II EPM570M100 CPLD. This will allow configuration of the Intel^® Arria^® 10 GX FPGA device using a USB cable directly connected to a PC running Intel^® Quartus^® Prime software without requiring the external USB Blaster dongle. This design will convert USB data to interface with the Intel^® Arria^® 10 GX FPGA’s dedicated JTAG port. An LED (D4) is provided to indicate USB Blaster activity. The embedded USB blaster is automatically disabled when an external USB Blaster dongle is connected to the JTAG chain.

Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its Flash interface signals to avoid contention with the FPGA. A PGMSEL dipswitch (SW3) is provided to select between two POF files (FACTORY or USER) stored on the Flash. The Parallel Flash Loader (PFL) Megafunction will be used to implement FPP x32 configuration in the MAX^® V CPLD. The PFL Megafunction reads data from the flash and converts it to Fast Passive Parallel format. This data is written to the Intel^® Arria^® 10 FPGA device dedicated DCLK and D[31:0] configuration pins at 50 MHz. The actual configuration data rate is limited by the flash read speed.

Implementation will be done using an Altera MAX^® V 5M2210ZF256FBGA CPLD acting as the FPP download controller and two 1G Flash devices. The flash will be a Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX^® V CPLD will share the CFI Flash interface with the Intel^® Arria^® 10 GX FPGA. No arbitration is needed between the MAX^® V CPLD and Intel^® Arria^® 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization.

After a POWER-ON or RESET (re-configuration) event, the MAX^® V device will configure the Arria 10 GX FPGA in FPP x32 mode with either the FACTORY POF or a USER defined POF depending on the FACTORY_LOAD setting. The PGMSEL bit is set via a pushbutton and observing the appropriate LED indicating a Factory or User file to be loaded. After selection of the program file; another pushbutton is press to load the program; that button is the PGM_CONFIG button.

The MSEL [2:0] pins indicate which passive mode is being used and whether the Fast or Slow POR delay is chosen. The data bus width information is contained in the Mode Select Decode Frame that is part of the configuration data. PORSEL is an internal signal decoded from MSEL[2:0] pins. PORSEL = 1 selects a Fast POR delay between 4-12ms. PORSEL = 0 selects a Slow POR delay between 100-300ms.The manufacturing default condition should be [000] for a Fast POR Delay mode without decompression or security enabled.

The 4 modes of Passive Programming are passive serial, passive parallel x8, passive parallel x16, and passive parallel x32.

The JTAG chain allows programming of both the Intel^® Arria^® 10 GX FPGA and MAX V CPLD devices using an external Altera USB blaster dongle or the on-board USB2 blaster via the USB interface connector.

During board bring-up and as a back-up in case the on-board USB2 blaster has a problem, the external Altera USB Blaster dongle can be used to program both Intel^® Arria^® 10 GX FPGA and MAX V CPLD via the external blaster 2 x 5 pin 0.1” programming header (J66).

Another 2 x 5 pin 0.1” vertical non-shrouded header (J18) is provided on the board for programming the MAXII_Blaster CPLD for configuring the on-board USB Blaster circuitry. Once the on-board blaster is configured and operational, the on-board blaster can be used for subsequent programming of the Intel^® Arria^® 10 GX FPGA and MAX V CPLD.

Pin 2 of the Intel^® Arria^® 10 GX FPGA and MAX V JTAG Header will be used to disable the embedded USB Blaster by connecting it to the embedded Blaster’s DEVOEn pin with a pull-up resistor. Since Pin 2 from the mating Blaster dongle is GND, when the dongle is connected into the JTAG header, the embedded Blaster is disabled to avoid contention with the external USB blaster dongle.

JTAG Chain Device Removal Switch: The JTAG chain will connect the Intel^® Arria^® 10 GX FPGA and the MAX V CPLD devices in a chain, with the option to selectively bypass the MAX V CPLD by a dip switch setting. This switch will be one position of a 6-position switch. The other positions will consist of the MSEL bits for configuration modes, Fan Control and VID enable.

Program Select Push Button: After a POWER-ON or RESET (reconfiguration) event, the MAX V will configure the Intel^® Arria^® 10 GX FPGA in FPP mode with either the FACTORY POF or a USER defined POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this button and observing the program LEDs (FACTORY or USER) dictates which program will be selected. Then the PGM_CONFIG pushbutton needs to be pressed to load the program.

MAX V RESET Push Button: This pushbutton is the board Master Reset. This button is connected to the MAX V CPLD (MAX_RESETn pin) that is used for FPP configuration. When this button is pressed, the MAX V CPLD will initiate a reloading of the stored image from flash memory using FPP configuration mode. The image that is reloaded depends on the PGMSEL setting.

CPU RESET Push Button:This pushbutton is the Nios^® II CPU Reset. This button is connected to an Intel^® Arria^® 10 GX FPGA DEV_CLRn and can be used by Nios^® II implementations as a dedicated CPU Reset button. This button is also connected to the MAX^® V CPLD so that the FPGA device can be reset right after its configuration with FPP mode.

The figure below shows the dedicated transceiver clocking that will be implemented for the FPGA. This clocking scheme will allow 4 different protocols to be running simultaneously by the Intel^® Arria^® 10 GX FPGA.

The default frequencies can be overridden and a different frequency can be programmed into the oscillators for support of other protocols.

Each oscillator will support a programmable frequency range of 10 MHz - 1.4 GHz and provide a differential LVDS trigger output to SMA connectors for scope or other lab equipment triggering purposes.

In addition to the four oscillators, each side will have a dedicated differential REFCLK input from a pair of SMA connectors to allow use of lab equipment clock generators as the transceiver clock source.

In addition to the transceiver dedicated clocks, five other clock sources will be provided to the FPGA Global CLK inputs for general FPGA design as shown in the figure below

A 24 MHz oscillator is dedicated for the embedded USB2 Blaster circuitry. The oscillator is used to clock the Cypress CY7C68013A USB2 PHY device.

The development board includes 8 user-defined push buttons and 4 system push buttons that allow you to interact with the Intel^® Arria^® 10 GX FPGA device. When you press and hold down the push button, the device pin is set to logic 0; when you release the push button, the device pin is set to logic 1. There is no board-specific function for these general user push buttons.

Board reference SW2 and SW6 are two 4-pin DIP switches. The switches are user-defined, and are provides additional FPGA input control. When the switch is in the OPEN position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected. There is no board-specific function for these switches.

The development board includes eight user-defined LEDs. Board references D13 through D20 are user LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the Intel^® Arria^® 10 GX FPGA device. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

A 16 character x 2 line LCD display will be connected to the Intel^® Arria^® 10 GX FPGA device to display board information and IP address. The LCD module used is New Haven - NHD-0216K3Z-NSW-BBW-V3. This LCD module will be mounted to the Intel^® Arria^® 10 GX transceiver signal integrity development board using a 1 x 10 vertical male 0.1” header on the left side of the module and 3 plastic standoffs. This mounting scheme will allow low profile (less than 0.5 inches in height) components to be placed underneath the LCD module, preserving board real-estate.

The table below summarizes the LCD pin assignments. The signals name and directions are relative to the Intel^® Arria^® 10 GX FPGA device

The development board supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet Megacore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Intel^® Arria^® 10 GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 connector with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Two Flash devices are implemented to achieve a 32-bit wide data bus at 16 bits each per device. The target device is a Micron PC28F00AP30BF CFI Flash device. Both MAX V CPLD and Intel^® Arria^® 10 GX FPGA can access this Flash device. MAX V CPLD accesses will be for FPP configuration of the FPGA at power-on and board reset events. This will use the Altera PFL Megafunction. Arria 10 GX FPGA access to the FLASH’s user space will be done by Nios^® II for the BUP application. The flash will be wired for WORD mode operation to support FPPx32 download directly.

Each FPGA bit stream can be a maximum of 254.25 Mbits (or less than 32 MBytes) for the Intel^® Arria^® 10 GX FPGA device. The remaining area will be designated as RESERVED flash area for storage of the BUP image and PFL configuration settings, software binaries and other data relevant to the FPGA design.

Power for this board will be provided through an external Laptop style DC power brick connected to a 4-pin power DIN jack (CUI Inc. PD-40S). The input voltage must be in the range of 12V +/- 5%. This DC voltage is then stepped down to the various power rails used by the components on the board.

Some power rails on the board will have the option to be supplied from an external source via banana jack connectors by first removing a jumper for that power rail.

There are ten voltage rails that are monitored by an LTM2987 and LTC2974 Power Monitor devices. The voltage rails monitored are listed in the table below. These power monitor devices are capable of measuring the voltage, measuring the current, trimming the voltage, and sequencing the order at power on and power off. Voltages can be trimmed up to +/-10%. Communication to these devices is through I2C interface. A Linear Technology power monitor application know as LTPowerPlay can be utilized to measure, trim, and observe each voltage rail's condition.

Temperature monitoring will be done by a MAX1619 dual temperature sense device. This device will allow temperature sensing of both the Intel^® Arria^® 10 GX FPGA die and board ambient. The MAX1619 is connected to the Intel^® Arria^® 10 GX FPGA by a 2-wire SMBus interface. Additionally, the OverTemp (OTn) and ALERTn signals from the MAX1619 is brought to the MAX V device to allow it to immediately sense a temperature fault condition and turn on the Intel^® Arria^® 10 GX FPGA's attached FAN.

An over temperature warning LED (amber-colored) is provided for the Intel^® Arria^® 10 GX FPGA device. This LED will indicate the temperature fault condition and that the FAN should be connected and running. The fan will be controlled by the OverTemp signal from the MAX1619 and can be set to turn on when the Arria 10 GX FPGA die temperature exceeds a specified set point. Temperature fault set points can be programmed into the MAX1619. The HDL design code along with .sof/.pof files are provided to the user.

The Board Test System (BTS) will prompt you with a Version Selector window once opened. You can also open the Version Selector window through the Configure tab by clicking Select Silicon Version. Select the silicon version of the Intel^® Arria^® 10 GX FPGA device that is installed on your board.

This section describes each control in the Board Test System application.

Use the Configure menu to select the design you want to use. Each design example tests different functionality that corresponds to one or more application tabs.

Figure 16. The Configure Menu

The System Info tab shows information about the board’s current configuration. The tab displays the contents of the MAX V registers, the JTAG chain, the board’s MAC address, the flash memory map, and other details stored on the board.

Figure 17. The System Info Tab

The following sections describe the controls on the System Info tab.

The Board information control displays static information about your board.

• Board Name—Indicates the official name of the board, given by the Board Test System.
• Board P/N—Indicates the part number of the board.
• Serial number—Indicates the serial number of the board.
• Factory test version—Indicates the version of the Board Test System used to production test the board.
• MAX V ver—Indicates the version of MAX V code currently running on the board.

The MAX V code resides in the <package dir>\examples\max5 directory. Newer revisions of this code might be available on the Arria 10 GX Transceiver Signal Integrity Development Kit web page of the Altera website.

• MAC—Indicates the MAC address of the board.

The MAX V registers control allows you to view and change the current MAX V register values as described in the table below. Changes to the register values with the GUI take effect immediately.

Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running.

The JTAG chain control shows all the devices currently in the JTAG chain. The Intel^® Arria^® 10 GX FPGA device is always the first device in the chain.

The Qsys memory map control shows the memory map of bts_config.sof design running on your board.

The GPIO tab allows you to interact with all the general purpose user I/O components on your board. You can write to the character LCD, read DIP switch settings, turn LEDs on or off, and detect push button presses.

Figure 18. The GPIO Tab

The following sections describe the controls on the GPIO tab.

The Character LCD controls allow you to display text strings on the character LCD on your board. Type text in the text boxes and then click Display. If you exceed the 16 character display limit on either line, a warning message appears.

The read-only User DIP switches control displays the current positions of the switches in the user DIP switch bank (SW2 and SW6). Change the switches on the board to see the graphical display change accordingly.

The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off.

The read-only Push button switches control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly.

The Flash tab allows you to read and write flash memory on your board.

Figure 19. The Flash Tab

The following sections describe the controls on the Flash tab.

The Read control reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. The flash memory sits at a base address of 0x1000.0000. To see flash memory contents type the address above the base and values starting at this address are displayed. Valid entries are 0x0000.0000 through 0x0FFF.FF80.

The Write control writes the flash memory on your board. To update the flash memory contents, change values in the table and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

Starts a random data pattern test to flash memory, which is limited to a scratch page in the upper 512K block.

The CFI Query control updates the memory table, displaying the CFI ROM table contents from the flash device.

Starts an incrementing data pattern test to flash memory, which is limited to scratch page in the upper 512K block.

The Reset control executes the flash device’s reset command and updates the memory table displayed on the Flash tab.

When erasing flash memory contents should read FFFF FFFF, which is limited to a scratch page in the upper 512K block.

Displays the flash memory map for the Intel^® Arria^® 10 GX transceiver signal integrity development kit.

The XCVR #1 tab allows you to run transceivers QSFP, SFP+ and CFP2 loopback tests on your board. You can run the test using either electrical loopback modules or optical fibre modules.

Figure 20. The XCVR #1 Tab

The following sections describe the controls on the XCVR #1 tab.

The Status control displays the following status information during the loopback test:

The Data type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:

Settings HF and LF are for transmit observation only and are not intended for use in the receiver data detection circuitry.

This control displays data errors detected during analysis and allows you to insert errors:

The XCVR #2 tab allows you to run a x4 backplane and x6 SMA (2.4 mm) loopback tests.

Figure 22. The XCVR #2 Tab

The following sections describe the controls on the XCVR #2 tab.

The Status control displays the following status information during the loopback test.

Refer to the Status section of the XCVR #1 Tab for related information.

The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface.

Refer to the PMA setting section of the XCVR #1 Tab for related information.

The Data type control specifies the type of data contained in the transactions.

Refer to the Data Type section of the XCVR #1 Tab for related information.

This control displays data errors detected during analysis and allows you to insert errors.

Refer to the Error Control section of the XCVR #1 Tab for related information.

Refer to the Run Control section of the XCVR #1 Tab for related information.

The XCVR #3 tab allows you to run x10 high density loopback test through BullsEye connector.

Figure 23. The XCVR #3 Tab

The following sections describe the controls on the XCVR #3 tab.

The Status control displays the following status information during the loopback test.

Refer to the Status section of the XCVR #1 Tab for related information.

Use the following control to select the high density interface to apply PMA settings, data type and error control: High Density (BullsEye)

The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface.

Refer to the PMA setting section of the XCVR #1 Tab for related information.

The Data type control specifies the type of data contained in the transactions.

Refer to the Data Type section of the XCVR #1 Tab for related information.

This control displays data errors detected during analysis and allows you to insert errors.

Refer to the Error Control section of the XCVR #1 Tab for related information.

Refer to the Run Control section of the XCVR #1 Tab for related information.

The Power Monitor measures and reports current power information and communicates with the MAX V device on the board through the JTAG bus. A power monitor circuit attached to the MAX V device allows you to measure the power that the FPGA is consuming.

To start the application, click the Power Monitor icon in the Board Test System application. You can also run the Power Monitor as a stand-alone application. The PowerMonitor.exe reside in the <package dir>\examples\board_test_system directory

The Clock Control application sets the Si570 programmable oscillators to any frequency between 10 MHz and 945 MHz and select frequencies to 1400 MHz. The oscillator drives a 2-to-6 buffer that drives a copy of the clock to all transceiver blocks of the FPGA.

The Clock Control application runs as a stand-alone application. ClockControl.exe resides in the <package dir>\examples\board_test_system directory.

The Clock Control communicates with the MAX V device on the board through the JTAG bus. The Si570 programmable oscillator is connected to the MAX V device through a 2-wire serial bus.

Figure 25. The Clock Control

The following sections describe the Clock Control controls.

The Serial port registers control shows the current values from the Si570 registers.

The fXTAL control shows the calculated internal fixed-frequency crystal, based on the serial port register values.

The Target frequency control allows you to specify the frequency of the clock. Legal values are between 10 and 945 MHz and select frequencies to 1400 MHz. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target frequency control works in conjunction with the Set New Frequency control.

The clear control sets the Si570 programmable oscillator to the default frequency as follows:

Y3 = 644.53125 MHz

Y4 = 706.25 MHz

Y5 = 625 MHz

Y6 = 875 MHz

The Set New Frequency control sets the Si570 programmable oscillator frequency to the value in the Target frequency control. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time.

The table below shows the default memory contents of the two 1-Gb CFI flash devices. For the Board Update Portal to run correctly and update designs in the user memory, this memory map must not be altered.

You can obtain designs containing prepared .flash files from the Arria 10 GX Transceiver Signal Integrity Development Kit web page of the Altera website or create .flash files from your own custom design.

The Nios^® II EDS sof2flash command line utility converts your Quartus-compiled .sof into the .flash format necessary for the flash device. Similarly, the Nios^® II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File (.elf) software design to .flash. After your design files are in the .flash format, use the Board Update Portal or the Nios II EDS nios2-flash-programmer utility to write the .flash files to the user software locations of the flash memory.

Once you have the necessary .flash files, you can use the Board Update Portal to reprogram the flash memory. Refer to “Using the Board Update Portal to Update User Designs” for more information.