The Intel FPGA PAC N3000 provides an on-board PCIe switch that connects fronthaul and 5G channel coding functions to a PCIe Gen3x16 edge connector. The Intel FPGA PAC N3000 is a general-purpose acceleration card for networking.

The Intel PAC N3000 supports a user image. A remote system update (RSU) capable page (page 1) in an on-board 1 Gb flash stores the user image. A non-RSU capable page (page 0) of the same 1 Gb flash stores a fail over factory image..

Intel develops and owns all of the following Intel PAC N3000 components (including all updates) except the Intel^® Arria^® 10 flash page 1 user image:

• Intel^® MAX^® 10 Nios flash.
  • Fixed configuration.
  • RSU capable.
  • Intel loads the binary image.
• PCIe software.
  • Intel flashes the binary images.
  • Fixed configuration for PCIe configuration.
  • Not RSU capable.
• Intel C827 retimer.
  • Intel flashes the binary EEPROM.
  • Power-up configuration initialization by Intel^® Arria^® 10 soft Nios processor through Intel^® MAX^® 10.
  • Fixed configuration for transceiver.
  • Encrypted.
• Intel XL710.
  • Intel flashes the binary images.
  • Fixed configuration for transceiver configuration.
  • RSU capable.
• Intel^® Arria^® 10 flash factory image page 0.
  • Intel flashes the binary images.
  • Not RSU capable.
• Intel^® Arria^® 10 flash page 1 user image.
  • RSU capable.
  • Intel provides the top-level reference design under a software license agreement.
  • Contains multiple encrypted IP blocks provided under a software license agreement.
  • You own the production image and design.

The factory image:

• Tests the image that enables PCIe, Ethernet, and memory diagnostics:
  • PCIe near-end loopback testing
  • Memory testing using DMA reads and writes
  • Ethernet loopback test
• Enables the RSU for the user image in flash

If the user image update fails, the Intel PAC N3000 restarts with the factory image, you can then reload the user image.

On-board power monitoring restricts the board temperature to 100°C. In the event of reaching this limit, the board is automatically shut down. The user image power consumption and thermal profile must fit within this envelope.

For different situations with different functions, the power consumptions are different. As a reference point, the raw power consumption of the FPGA for the 5G user image is about 60 W @ 100°C junction temperature. The Intel PAC N3000 card power consumption is about 100 W.

The channel coders queue and process these blocks based on the load balancing decisions.

The downlink FEC accelerator consists of the 5G LDPC-V transmitter and the uplink FEC accelerator consists of the 5G LDPC-V receiver. The input to the downlink FEC accelerator is 32-bit data and the output data is 32-bit wide. For more information on the 5G LDPC-V transmitter and receiver, refer to the 5G LDPC-V Intel FPGA IP User Guide.

For a single encoder, the clock rate, code block size (base graph number, lifting factor), code rate affect the throughput.

For a single decoder, the clock rate, code block size (base graph number, lifting factor), code rate, and literation number affect the throughput.

The tests randomly select 2,000 test patterns from 110,000 test patterns to test the decoding function and randomly selects 2,000 test patterns from 110,000 test patterns to test the encoding function. The tests also test the randomization (and functional coverage) of system scenarios such as HARQ, physical and virtual function (PF and VF) access, queue flushing, and reset. The reference design includes the UVM test plan, 5G_LDPC_Test_Plan.xls.

Figure 11. UVM Tests