AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000
1. About the 5G Wireless Acceleration Reference Design
The Intel FPGA PAC N3000 provides an on-board PCIe switch that connects fronthaul and 5G channel coding functions to a PCIe Gen3x16 edge connector. The Intel FPGA PAC N3000 is a general-purpose acceleration card for networking.
1.1. 5G User Image Features
FEC features:
- Functionality independent of 25G I/O (look-aside model).
- Support for one physical function (PF) and 8 virtual functions (VFs) simultaneously accessing acceleration.
- 64 queues supported equally split between uplink and downlink.
- Multiqueue high-performance DMA
- Hybrid automatic repeat request (HARQ) block
- LDPC transmitter with interleaving and rate matching.
- LDPC receiver with de-interleaving function and reverse rate matching.
- Load balancer distributes the pending requests to transmitter and receiver.
- Early termination CRC24B.
- Software enablement by baseband device (bbdev) API (targeted to upstream to Data Plane Development Kit (DPDK).
- Function-level reset.
Fronthaul IO features:
- 25G MAC and 25G PHY IP connectivity to retimer and a quad small form factor pluggable (QSFP28).
- 40G MAC and 40G PHY IP connectivity to Intel XL710 networking device.
- Gearbox to enable 25G connectivity to QSFP28.
- IEEE 1588 PTP support.
- Software enablement by Open Platform Acceleration Environment (OPAE), DPDK and bbdev.
1.2. About the Intel PAC N3000
The Intel PAC N3000 supports a user image. A remote system update (RSU) capable page (page 1) in an on-board 1 Gb flash stores the user image. A non-RSU capable page (page 0) of the same 1 Gb flash stores a fail over factory image..
Intel develops and owns all of the following Intel PAC N3000 components (including all updates) except the Intel® Arria® 10 flash page 1 user image:
-
Intel®
MAX® 10 Nios flash.
- Fixed configuration.
- RSU capable.
- Intel loads the binary image.
- PCIe software.
- Intel flashes the binary images.
- Fixed configuration for PCIe configuration.
- Not RSU capable.
- Intel C827 retimer.
- Intel flashes the binary EEPROM.
- Power-up configuration initialization by Intel® Arria® 10 soft Nios processor through Intel® MAX® 10.
- Fixed configuration for transceiver.
- Encrypted.
- Intel XL710.
- Intel flashes the binary images.
- Fixed configuration for transceiver configuration.
- RSU capable.
-
Intel®
Arria® 10 flash factory image page 0.
- Intel flashes the binary images.
- Not RSU capable.
-
Intel®
Arria® 10 flash page 1 user image.
- RSU capable.
- Intel provides the top-level reference design under a software license agreement.
- Contains multiple encrypted IP blocks provided under a software license agreement.
- You own the production image and design.
1.2.1. Factory Image for 2x2x25 GbE
The factory image:
- Tests the image that enables PCIe, Ethernet, and memory
diagnostics:
- PCIe near-end loopback testing
- Memory testing using DMA reads and writes
- Ethernet loopback test
- Enables the RSU for the user image in flash
If the user image update fails, the Intel PAC N3000 restarts with the factory image, you can then reload the user image.
2. 5G User Image Description
2.1. User Image Power Management
On-board power monitoring restricts the board temperature to 100°C. In the event of reaching this limit, the board is automatically shut down. The user image power consumption and thermal profile must fit within this envelope.
For different situations with different functions, the power consumptions are different. As a reference point, the raw power consumption of the FPGA for the 5G user image is about 60 W @ 100°C junction temperature. The Intel PAC N3000 card power consumption is about 100 W.
2.2. 5G Channel Coder
The channel coders queue and process these blocks based on the load balancing decisions.
The downlink FEC accelerator consists of the 5G LDPC-V transmitter and the uplink FEC accelerator consists of the 5G LDPC-V receiver. The input to the downlink FEC accelerator is 32-bit data and the output data is 32-bit wide. For more information on the 5G LDPC-V transmitter and receiver, refer to the 5G LDPC-V Intel FPGA IP User Guide.
.
2.2.1. 5G Channel Coder Throughput
For a single encoder, the clock rate, code block size (base graph number, lifting factor), code rate affect the throughput.
For a single decoder, the clock rate, code block size (base graph number, lifting factor), code rate, and literation number affect the throughput.
2.2.2. 5G LDPC-V Transmitter and Receiver Test Cases
test case | BG | Zc | K' | Code Rate | Qm | E | K0 | CRC |
0 | 0 | 10 | 184 | 1/3 | 1 | 300 | 0 | ON |
1 | 0 | 20 | 400 | 1/2 | 4 | 520 | 0 | ON |
2 | 0 | 40 | 800 | 3/4 | 4 | 900 | 600 | ON |
3 | 0 | 10 | 184 | 8/9 | 1 | 260 | 180 | OFF |
4 | 0 | 4 | 88 | 2/3 | 1 | 80 | 0 | OFF |
5 | 0 | 5 | 104 | 2/3 | 4 | 100 | 120 | OFF |
6 | 1 | 240 | 2352 | 1/2 | 1 | 2800 | 0 | ON |
7 | 1 | 256 | 2520 | 1/3 | 2 | 3200 | 2048 | ON |
8 | 1 | 9 | 88 | 1/3 | 8 | 96 | 117 | ON |
9 | 1 | 80 | 720 | 1/3 | 8 | 864 | 1200 | OFF |
test case | BG | Zc | K' | Code Rate | Qm | E | K0 | CRC |
0 | 0 | 10 | 216 | 1/3 | 2 | 280 | 330 | ON |
1 | 0 | 20 | 440 | 1/2 | 6 | 504 | 440 | ON |
2 | 0 | 40 | 880 | 3/4 | 6 | 882 | 0 | ON |
3 | 0 | 10 | 216 | 8/9 | 2 | 240 | 0 | OFF |
4 | 0 | 4 | 80 | 2/3 | 2 | 80 | 32 | OFF |
5 | 0 | 5 | 96 | 2/3 | 6 | 102 | 0 | OFF |
6 | 1 | 240 | 2400 | 1/2 | 6 | 2802 | 0 | ON |
7 | 1 | 256 | 2560 | 1/3 | 4 | 3200 | 256 | ON |
8 | 1 | 9 | 80 | 1/3 | 8 | 96 | 54 | ON |
9 | 1 | 80 | 800 | 1/3 | 8 | 840 | 1600 | OFF |
2.2.3. 5G VRAN Universal Verification Methodology
The tests randomly select 2,000 test patterns from 110,000 test patterns to test the decoding function and randomly selects 2,000 test patterns from 110,000 test patterns to test the encoding function. The tests also test the randomization (and functional coverage) of system scenarios such as HARQ, physical and virtual function (PF and VF) access, queue flushing, and reset. The reference design includes the UVM test plan, 5G_LDPC_Test_Plan.xls.

2.3. Fronthaul IO
You can add customized IP based on the packet process between 40GbE and 25GbE, e.g. compression and decompression IPs for O-RAN.
2.4. User Image Software
3. Document Revision History for AN 907: Enabling 5G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000
Document Version | Changes |
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2020.09.10 |
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2020.01.30 | Initial release. |