Stratix® 10 Low Latency (LL) 40G Ethernet
IP core provides a simulatable testbench and a hardware design example that supports
compilation and hardware testing. When you generate the design example, the parameter editor
automatically creates the files necessary to simulate, compile, and test the design in
hardware. You can download the compiled hardware design to the
Stratix® 10 GX Transceiver Signal Integrity Development Kit. The testbench and
demonstration design example are available for a wide range of parameters. However, they do
not cover all possible parameterizations of the Intel Stratix 10 LL 40GbE IP Core.
In addition, for most IP core variations,
Intel® provides a compilation-only example project that you can use to
quickly estimate IP core area and timing.
Figure 1. Development Steps for the Design Example
Figure 2. Directory Structure for the Generated Design Example
The hardware configuration and test files (the hardware design
example) are located in <design_example_dir>/hardware_test_design. The simulation
files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The
compilation-only example design is located in <design_example_dir>/compilation_test_design.
The simulation design example top-level test file is
basic_avl_tb_top.sv. This file instantiates and connects an ATX PLL. It
includes a task to send and receive 10 packets. The simulation design example
for 40GBASE-KR4 variations also exercises auto-negotiation and link training, if
Top-level testbench file. The testbench
instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. The testbench also implements auto-negotiation and
link training if enabled in a 40GBASE-KR4/CR4 DUT.
The ModelSim script to run the testbench.
The Synopsys VCS script to run the testbench.
Hardware Design Example Components
Figure 4. Intel Stratix 10 LL 40GbE Hardware Design Example
High Level Block Diagram
The Intel Stratix 10 LL 40GbE hardware design example
includes the following components:
Intel Stratix 10 LL 40GbE IP core.
Client logic that coordinates the programming of the IP core,
and packet generation and checking.
ATX PLL to drive the device transceiver channel clocks.
IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware
JTAG controller that communicates with the
Intel® System Console. You communicate
with the client logic through the System Console.
Table 2. Intel Stratix 10 LL 40GbE IP Core
Hardware Design Example File Descriptions
Quartus® Prime project file.
Quartus project settings file.
Synopsys Design Constraints file. You can copy
and modify this file for your own Intel Stratix 10 LL 40GbE
Top-level Verilog HDL design example file.
Hardware design example support files.
Main file for accessing System Console.
Generating the Design Example
Figure 5. Procedure
Figure 6. Example Design Tab in the Intel Stratix 10 LL 40GbE Parameter Editor
Follow these steps to generate the hardware design example and testbench:
Quartus® Prime Pro Edition, click File > New Project Wizard to create a new
Quartus® Prime project, or
File > Open Project to open an existing
Quartus® Prime project. The
wizard prompts you to specify a device family and device.
Note: The design
example overwrites the selection with the device on the target board. You specify the
target board from the menu of design example options in the Example Design tab (Step 8).
At the time of publication (2017.05.08), only a single target board is available, the
design example DUT if you select an H-tile device is 1SG280HU3F50E3VGS1, and the design
example DUT if you select an L-tile device is 1SG280LU3F50E3VGS1.
In the IP Catalog, locate and select Low
G Ethernet. The New IP Variation window appears.
Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP
variation settings in a file named <your_ip>.ip.
Click OK. The parameter editor
On the IP tab, specify the
parameters for your IP core variation.
Note: The Intel Stratix 10 LL 40GbE design
example does not simulate correctly and does not function correctly in hardware for the
Use external TX MAC PLL
Enable preamble pass-through turned on
Ready latency set to the value of 3
Enable TX CRC insertion turned off
On the Example Design tab, under
Example Design Files, select the Simulation option to generate the testbench, and select the
Synthesis option to generate the compilation-only
and hardware design examples.
On the Example Design tab, under
Generated HDL Format, only Verilog HDL is
available. This IP core does not support VHDL.
Under Target Development Kit
select the Stratix 10 GX Transceiver Signal Integrity
You must ensure your project targets the specific Stratix 10 device on the
Click the Generate Example Design
button. The Select Example Design Directory window
If you wish to modify the design example directory path or name from the
defaults displayed (alt_e40_0_example_design
), browse to the new path and type the new
design example directory name (<design_example_dir>).
Simulating the Intel Stratix 10 LL 40GbE Design Example Testbench
Figure 7. Procedure
Follow these steps to simulate the testbench:
Change to the testbench simulation directory <design_example_dir>/example_testbench.
Run the simulation script for the supported simulator of your choice. The
script compiles and runs the testbench in the simulator. Refer to the table "Steps to
Simulate the Testbench".
Analyze the results. The successful testbench sends ten packets, receives
ten packets, and displays "Testbench complete."
successful 40GBASE-KR4/CR4 testbench performs auto-negotiation (if enabled) and link
training (if enabled) before performing these packet send and receive actions.
Table 3. Steps to Simulate the Testbench
In the command line, type vsim -do
If you prefer to simulate without
bringing up the ModelSim GUI, type vsim -c -do
ModelSim* - Intel® FPGA Edition
simulator does not have the capacity to simulate this IP core. You must use
another supported ModelSim simulator such as ModelSim SE.
In the command line, type sh
The successful test run displays output confirming the following
Waiting for RX clock to settle
Printing PHY status
Sending 10 packets
Receiving 10 packets
Displaying "Testbench complete."
The following sample output illustrates a successful simulation test run. For a 40GBASE-KR4/CR4 IP core variation, additional
auto-negotiation and link training messages display if these features are enabled.
Testing the Intel Stratix 10 LL 40GbE Hardware Design Example
After you compile the Intel Stratix 10 LL 40GbE
IP core design example and configure it on your Stratix® 10 device,
you can use the
Intel® System Console to program the IP core
and its embedded Native PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these
After the hardware design example is configured on the Stratix 10
device, in the
Quartus® Prime Pro Edition software, on
the Tools menu, click System Debugging Tools > System Console.
In the Tcl Console pane, type cd
hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
Type source main.tcl to open a
connection to the JTAG master.
You can program the IP core with the following design example commands:
chkphy_status: Displays the clock frequencies and PHY lock
chkmac_stats: Displays the values in the MAC statistics
clear_all_stats: Clears the IP core statistics counters.
start_pkt_gen: Starts the
stop_pkt_gen: Stops the packet
loop_on: Turns on internal
loop_off: Turns off internal
reg_read <addr>: Returns the IP core register
value at <addr>.
<data>: Writes <data> to the IP
core register at address <addr>.
The design example demonstrates the functions of the Intel Stratix 10 LL 40GbE core with
transceiver interface compliant with the IEEE 802.3ba standard CAUI-4
specification.You can generate
the design from the Example Design tab in the Intel Stratix 10 LL 40GbE parameter editor.
To generate the design example, you must first set the parameter values for
the IP core variation you intend to generate in your end product. Generating the design
example creates a copy of the IP core; the testbench and hardware design example use this
variation as the DUT. If you do not set the parameter values for the DUT to match the
parameter values in your end product, the design example you generate does not exercise the IP
core variation you intend.
Note: The testbench demonstrates a basic test of
the IP core. It is not intended to be a substitute for a full verification environment. You
must perform more extensive verification of your own Intel Stratix 10 LL 40GbE design in
simulation and in hardware.
The testbench sends traffic through the IP core, exercising the
transmit side and receive side of the IP core. In the hardware design example, you
can program the IP core in internal serial loopback mode and generate traffic on the
transmit side that loops back through the receive side.
Design Example Interface Signals
The Intel Stratix 10 LL 40GbE testbench is self-contained and
does not require you to drive any input signals.
Intel Stratix 10 LL 40GbE Design Example Registers
Table 5. Intel Stratix 10 LL 40GbE Hardware
Design Example Register MapLists the memory mapped register ranges for the hardware
design example. You access these registers with the reg_read and reg_write
functions in the
Stratix® 10 LL
TX MAC registers
RX MAC registers
Statistics Counter registers - TX
Statistics Counter registers - RX
Packet Client registers
Table 6. Packet Client Registers You can customize the Intel Stratix 10 LL 40GbE hardware design example by programming the packet
HW Reset Value
Scratch register available for
Four characters of IP block
identification string "CLNT"
Specify the transmit packet size
in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
Bit [29:16]: Specify the upper limit of
the packet size in bytes. This is only applicable to
For fixed mode, these bits specify
the transmit packet size in bytes.
For incremental mode, these bits
specify the incremental bytes for a packet.
Specify the number of packets to
transmit from the packet generator.
Bit : Reserved.
Bit : Packet generator disable bit. Set
this bit to the value of 1 to turn off the packet generator,
and reset it to the value of 0 to turn on the packet
Bit : Reserved.
Bit : Has the value of 1 if the IP core
is in MAC loopback mode; has the value of 0 if the packet
client uses the packet generator.
00: Random mode
01: Fixed mode
10: Incremental mode
Bit : Set this bit to 1 to use 0x1009 register to turn off
packet generator based on a fixed number of packets to
transmit. Otherwise, bit  of PKT_GEN_TX_CTRL register is used to turn off
the packet generator.
1: For transmission without gap in
0: For transmission with random
gap in between packets.
Destination address lower 32 bits
Destination address (lower 32
Destination address upper 16 bits
Destination address (upper 16
address lower 32bits
Source address (lower 32
Source address lower
Source address (upper 16
MAC loopback reset. Set to the
value of 1 to reset the design example MAC loopback.