Avalon Verification IP Suite: User Guide
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.4 |
1. Introduction to Avalon Verification IP Suite
- Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
- Avalon Streaming (Avalon-ST) source and sink interfaces
- Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces
- Clock source and reset source
- Interrupt source and sink
- Custom instruction master and slave
- External memory
This suite also provides the following monitors to verify the respective Avalon protocols:
- Avalon-MM monitor
- Avalon-ST monitor
1.1. Advantages of Using BFMs and Monitors
- It accelerates the verification process by providing key components of the verification testbench.
- It provides Avalon BFM components that implement the standard Avalon-MM and Avalon-ST protocols, serving as a reference for those protocols.
- For SystemVerilog users, the verification suite provides a platform that you can use to implement constraint-driven randomized tests. For example, you can implement the following modules for random testing:
- Traffic scenario drivers
- Scoreboard and coverage facilities
- Assertion checkers
1.2. BFM Implementation
The Quartus II software version 13.0 and higher extends VHDL BFM support in Qsys. The VHDL BFMs wrap the SystemVerilog implementation and include additional logic to support VDHL.
BFM | Verilog HDL Support | VHDL Support |
---|---|---|
Clock Source and Reset Source | Yes | Yes |
Avalon Interrupt Source and Sink | Yes | Version 13.0 and higher |
Avalon-MM Master, Slave, and Monitor | Yes | Version 13.0 and higher |
Avalon-ST Source, Sink, and Monitor | Yes | Version 13.0 and higher |
Conduit and Tri-State Conduit | Yes | Version 14.0 and higher |
External Memory | Yes | Version 13.0 and higher |
Nios II Custom Instruction Master and Slave | Yes | Version 13.0 and higher |
The VHDL BFM has four parts as shown in the figure below.
- SystemVerilog BFM—Contains the BFM implementation and behavioral model, and the SystemVerilog API. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
- VHDL package—Provides the VHDL API used to control the BFM and interface with your test program. The package contains VHDL procedures and events.
- API handler logic—SystemVerilog logic block that translates your test program’s VHDL API calls to SystemVerilog API calls. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
- API communication interface—Bridges
the VHDL API to the API handler logic.
Figure 1. VHDL Component BFM
The monitor components use the SystemVerilog Assertion (SVA) language and are supported only by simulators that support SVA, including:
- ModelSim® - Intel FPGA Edition
- Synopsys VCS
- Mentor Graphics® Questa.
1.3. Application Programming Interface
1.4. Application Example of BFMs
- An Avalon-MM device under test (DUT) that includes both Avalon-MM master and slave interfaces
- An Avalon-ST DUT that includes both source and sink interfaces, although typical components might include a single Avalon interface.
This figure illustrates it is possible to write a testbench using a traditional VerilogHDL implementation or using SystemVerilog with VMM.
To verify a component with Avalon-MM interfaces, insert a monitor between the master BFM and the slave interface. To verify a component with Avalon-ST interfaces, insert a monitor between the source BFM and sink interface. You can insert a second monitor between the slave or sink BFM and the master or source interface of the DUT. You can inserted monitors anywhere in the system to provide protocol assertion checking and functional coverage reporting.
The test program drives the stimulus to the DUTs. The test program also determines whether the DUT behavior is correct, by analyzing the responses. The BFMs translate the test program stimuli. The BFMs create the signaling for the Avalon-MM and Avalon-ST protocols. The monitors verify Avalon protocol compliance and provide test coverage reports.
2. Clock Source BFM
2.1. Parameters
Option | Default Value | Legal Values | Description |
---|---|---|---|
Clock rate | 10 | N/A | Specifies the clock rate in MHz. |
2.2. Clock Source API
clock_start()
Prototype: | clock_start() |
Arguments: | Verilog HDL: None
VHDL: N.A. |
Returns: | void |
Description: | Turns on the clock. |
Language Support: | Verilog HDL |
2.2.1. Clock_stop()
Prototype: |
clock_stop() |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Turns off the clock. |
Language support: | Verilog HDL |
2.2.2. get_run_state()
Prototype: |
get_run_state() |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
bit |
Description: |
Returns the state of the clock source; 1=running, 0=stop. |
Language support: | Verilog HDL |
2.2.3. get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
string |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 10.1 sp1 is encoded as "10.1.1". |
Language support: | Verilog HDL |
3. Reset Source BFM
3.1. Parameters
Option | Default Value | Legal Values | Description |
---|---|---|---|
Assert reset high | On | On/Off | Specifies the polarity of the reset signal. Turn on this option to set the reset signal active high. |
Cycles of initial reset | 0 | N/A | Specifies the number of cycles that the reset signal is asserted at the initial stage of the simulation. |
3.2. Reset Source API
reset_assert
Prototype: |
reset_assert |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void. |
Description: |
Asserts the reset signal. |
Language support: | Verilog HDL |
3.2.1. reset_deassert
Prototype: |
reset_deassert |
Arguments: |
Verilog HDL: None VHDL: None |
Returns: |
void. |
Description: |
Deasserts the reset signal. |
Language support: |
Verilog HDL, VHDL |
3.2.2. get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
String. |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 10.1 sp1 is encoded as "10.1.1". |
Language support: | Verilog HDL |
4. Avalon Interrupt Source and Interrupt Sink BFMs
4.1. Parameters
Option | Default Value | Legal Values | Description |
---|---|---|---|
Interrupt Source | |||
Assert IRQ high | On | On/Off | Specifies the polarity of the interrupt source signal. Turn on this option to change the name of the interrupt source signal port from irq to irq_n. |
IRQ width | 1 | 1–32 | Specifies the width of the interrupt source signal. |
Asynchronous IRQ | Off | On/Off | Specifies whether the interrupt signal is asserted or deasserted immediately after an API call or one clock cycle after an API call. Turn on this option to allow changes to the interrupt signal immediately after an API call. Turn off this option to allow changes to the interrupt signal on the next clock edge. |
VHDL BFM ID | 0 | 1–1023 | For VHDL BFMs only. Use this option to assign a unique number to each BFM in the testbench design. |
Interrupt Sink | |||
Assert IRQ high | On | On/Off | Specifies the polarity of the interrupt sink signal. Turn on this option to change the name of the interrupt source signal port from irq to irq_n. |
IRQ width | 1 | 1–32 | Specifies the width of the interrupt source signal. |
4.2. Interrupt Source and Sink API
clear_irq()
Prototype: | int clear_irq() |
Arguments: | Verilog HDL:
interrupt_bit
VHDL: interrupt_bit, bfm_id, req_if(bfm_id) |
Returns: | void |
Description: | Asserts the interrupt signal and sets the interrupt signal to 0, regardless of the value you set for Assert IRQ high in the parameter editor. |
Language Support: | Verilog HDL, VHDL |
4.2.1. get_irq()
get_irq()
Prototype: | get_irq() |
Arguments: | Verilog HDL: None
VHDL: irq, bfm_id, req_if(bfm_id) |
Returns: | logic[AV_IRQ_W-1:0]void |
Description: |
Returns the current value of the register holding the latched interrupt signal. |
Language Support: | Verilog HDL, VHDL |
4.2.2. get_version()
get_version()
Prototype: | string get_version() |
Arguments: | Verilog HDL: None
VHDL: N.A. |
Returns: | String |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 13.1 sp1 is encoded as "13.1.1". |
Language Support: | Verilog HDL |
4.2.3. set_irq()
set_irq()
Prototype: | set_irq() |
Arguments: | Verilog HDL:
int interrupt_bit
VHDL: int interrupt_bit, bfm_id, req_if(bfm_id) |
Returns: | void |
Description: |
Asserts the interrupt signal and sets the interrupt signal to 1, regardless of the value you set for Assert IRQ high in the parameter editor. |
Language Support: | Verilog HDL, VHDL |
5. Avalon-MM Master BFM
- The Avalon-MM Master BFM
- A test program
- The DUT that includes an Avalon-MM slave interface
Using the Avalon-MM BFM has the following advantage. It highlights any misinterpretation of the Avalon-MM protocol that might be missed in a testbench designed by a single engineer.
5.1. Timing
Symbol | Description |
---|---|
Tinit | The initial command latency, which is two cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency. |
Twt_1 | The response wait time, which is three cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command. |
Twr | waitrequest is always sampled #1 after the falling edge of clk. |
Tidle | The idle time after each transaction. This time is set by the command set_command_idle. |
Trl_1 | The response latency
for the first read, which is 3 cycles. This is the time between the read
command acceptance and the read response provided by the slave. The program
gets this time using the
get_response_latency
command.
If an Avalon-MM slave component defines the readLatency interface property, the readdatavalid signal is not used. The readdatavalid signal is not necessary because the slave component has a fixed read latency. For more information refer to the Avalon Interface Specifications. |
Trl_2 | The response latency for the second read, which is 3 cycles. The program gets this time using the get_response_latency command. |
Twrl_1 | The write response latency for the first write, which is 3 cycles. This is the time between when the write command acceptance and the write response is provided by the slave. The program gets this time using the get_response_latency command. |
Sci_1–Sci_4 | Signals when write or read commands are presented on the interface. The event name is signal_command_issued. |
Src_1,Src_3 | Signals write responses. The event name is signal_response_complete. |
Src_2,Src_4 | Signals read responses. The event name is signal_response_complete. |
Satc | Signals the end of the test. The event name is signal_all_transactions_complete |
TID_1–TID_4 | Reference number to identify each read or write transaction. |
ID_1, ID_3 | Reference number to identify each write transaction. |
ID_2, ID_4 | Reference number to identify each read transaction. |
Symbol | Description |
---|---|
Tinit | The initial command latency, which is 2 cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency. |
Twt_1 | The response wait time, which is 3 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command. |
Twt_2 | The response wait time for the first read, which is 2 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command. |
Twr | waitrequest is always sampled #1 after the falling edge of clk. |
Tidle | The idle time after a transaction. This time is set by the command set_command_idle. |
Sci_1–Sci_2 | Signals when write and read commands are presented on the interface. The event name is signal_command_issued. |
Src_1 | Signals the first read response. The event name is signal_response_complete. |
Satc | Signals the end of the test. The event name is signal_all_transactions_complete. |
5.2. Block Diagram
- Avalon-MM Master API—Provides methods to create Avalon-MM transactions and query the state of all queues.
- Command Descriptor—Accumulates the fields of an Avalon-MM command transaction using the set_command API call. Inserts completed commands onto the pending command queue.
- Avalon-MM Interface Driver—Issues transfers to the system interconnect fabric and holds each transfer until waitrequest is deasserted. For burst transfers, there is a separate transfer for each word of the burst. The system interconnect fabric can assert waitrequest for each word of the burst, as necessary.
- Timestamp Counter—Records a timestamp with commands for use in timing calculations. The driver and monitor both use the timestamp counter for timing calculations.
- Avalon-MM Interface Monitor—Monitors the system interconnect fabric and records responses for read transfers in the response queue.
- Response Descriptor—Collects information about completed transactions using the get_response_<rolename> API calls. The testbench uses this information for further analysis.
- Public Events—Provides status response
that arrives together with the data. The public event signals indicate the
status of the Master’s request, such as successful completion, timeout, or
error.
Figure 6. Block Diagram of the Avalon-MM Master BFM
5.3. Parameters
Parameter | Default Value | Legal Values | Description |
---|---|---|---|
Port Widths | |||
Address width | 32 | N/A | Address width in bits. |
Symbol width | 8 | N/A | Data symbol width in bits. The symbol width should be 8 for byte-oriented interfaces. |
Read Response width | 8 | N/A | Read response signal width in bits. |
Write Response width | 8 | N/A | Write response signal width in bits. |
Parameters | |||
Number of symbols | 4 | N/A | Number of symbols per word. |
Burstcount width | 3 | N/A | The width of the burst count in bits. |
Port Enables | |||
Use the read signal | On | On/Off | When On, the interface includes a read pin. |
Use the write signal | On | On/Off | When On, the interface includes a write pin. |
Use the address signal | On | On/Off | When On, the interface includes address pins. |
Use the byteenable signal | On | On/Off | When On, the interface includes byteenable pins. |
Use the burstcount signal | On | On/Off | When On, the interface includes burstcount pins. |
Use the readdata signal | On | On/Off | When On, the interface includes a readdata pin. |
Use the readdatavalid signal | On | On/Off | When On, the interface includes a readdatavalid pin. |
Use the writedata signal | On | On/Off | When On, the interface includes a writedata pin. |
Use the begintransfer signal | Off | On/Off | When On, the interface includes writedata pins |
Use the beginbursttransfer signal | Off | On/Off | When On, the interface includes a beginbursttransfer pins. |
Use the arbiterlock signal | Off | On/Off | When On, the interface includes an arbiterlock pin. |
Use the lock signal | Off | On/Off | When On, the interface includes a lock pin. |
Use the debugaccess signal | Off | On/Off | When On, the interface includes a debugaccess pin. |
Use the waitrequest signal | On | On/Off | When On, the interface includes a waitrequest pin. |
Use the transactionid signal | Off | On/Off | When On, the interface includes a transactionid pin. |
Use the write response signals | Off | On/Off | When On, the interface includes a writeresponse pin. |
Use the read response signals | Off | On/Off | When On, the interface includes a readresponse pin. |
Use the clken signals | Off | On/Off | When On, the interface includes a clken pin. |
Port Polarity | |||
Assert reset high | On | On/Off | When On, reset is asserted high. |
Assert waitrequest high | On | On/Off | When On, waitrequest is asserted high. |
Assert read high | On | On/Off | When On, read is asserted high. |
Assert write high | On | On/Off | When On, write is asserted high. |
Assert byteenable high | On | On/Off | When On, byteenable is asserted high. |
Assert readdatavalid high | On | On/Off | When On, readdatavalid is asserted high. |
Assert arbiterlock high | On | On/Off | When On, arbiterlock is asserted high. |
Assert lock high | On | On/Off | When On, lock is asserted high. |
Burst Attributes | |||
Linewrap burst | On | On/Off | When On, the address for bursts wraps instead of incrementing. With a wrapping burst, when the address reaches a burst boundary, it wraps back to the previous burst boundary. Consequently, only the low order bits are used for addressing. |
Burst on burst boundaries only | On | On/Off | When On, memory bursts are aligned to the address size. |
Miscellaneous | |||
Maximum pending reads | 1 | N/A | The maximum number of pending reads that can be queued by the slave. |
Fixed read latency (cycles) | 1 | N/A | Sets the read latency for fixed-latency slaves. Not used on interfaces that include the readdatavalid signal. |
VHDL BFM ID | 0 | 0–1023 | For VHDL BFMs only. Use this option to assign a unique number to each BFM in the testbench design. |
Timing | |||
Fixed read wait time (cycles) | 1 | N/A | For master interfaces that do not use the waitrequest signal. The read wait time indicates the number of cycles before the master responds to a read. The timing is as if the master asserted waitrequest for this number of cycles. |
Fixed write wait time (cycles) | 0 | N/A | For master interfaces that do not use the waitrequest signal. The write wait time indicates the number of cycles before the master accepts a write. |
Registered waitrequest | Off | On/Off | Specifies whether to turn on the register stage. |
Registered Incoming Signals | Off | On/Off | Specifies whether to register incoming signals. |
Interface Address Type | |||
Set master interface address type to symbols or words | WORDS | WORDS/SYMBOLS | Sets slave interface address type to symbols or words. |
5.4. Avalon-MM Master BFM API
all_transactions_complete()
Prototype: |
bit all_() |
Arguments: |
Verilog HDL: None
VHDL:transactions_complete_status, bfm_id, req_if(bfm_id) |
Returns: |
bit. |
Description: |
Queries the BFM component to determine whether all issued commands have been completed. A return value of 1 means that there are no more transactions in the transaction queue or in progress. |
Language support: | Verilog HDL, VHDL |
5.4.1. event_all_transactions_complete()
Prototype: |
event_all_transactions_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that all commands have completed. |
Language support: | VHDL |
5.4.2. event_command_issued()
Prototype: |
event_command_issued() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench a command was driven to the bus. |
Language support: | VHDL |
5.4.3. event_max_command_queue_size()
Prototype: |
event_max_command_queue_size() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the command queue size reached its maximum limit. |
Language support: | VHDL |
5.4.4. event_min_command_queue_size()
Prototype: |
event_min_command_queue_size() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the command queue size reached its minimum limit. |
Language support: | VHDL |
5.4.5. event_read_response_complete()
Prototype: |
event_read_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a read response was received. |
Language support: | VHDL |
5.4.6. event_response_complete()
Prototype: |
event_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a read/write response was received. |
Language support: | VHDL |
5.4.7. event_write_response_complete()
Prototype: |
event_write_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a write response was received. |
Language support: | VHDL |
5.4.8. get_command_issued_queue_size()
Prototype: |
int get_command_issued_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: command_issued_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the issued command queue to determine the number of commands that have been driven to the system interconnect fabric, but not completed. |
Language support: | Verilog HDL, VHDL |
5.4.9. get_command_pending_queue_size()
Prototype: |
int get_command_pending_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: command_pending_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the command queue to determine number of pending commands waiting to be driven out as Avalon requests. |
Language support: | Verilog HDL, VHDL |
5.4.10. get_read_response_queue_size()
Prototype: |
int get_read_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: read_response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the read response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately remove from the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
5.4.11. get_response_address()
Prototype: |
bit [AV_ADDRESS_W-1:0] get_response_address() |
Arguments: |
Verilog HDL: None
VHDL: response_address, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Returns the transaction address in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.12. get_response_byte_enable()
Prototype: |
bit [AV_NUMSYMBOLS-1:0] get_response_byte_enable(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_byte_enable, index, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Returns the value of the byte enables in the response descriptor that has been removed from the response queue. Each cycle of a burst response is addressed individually by the specified index. |
Language support: | Verilog HDL, VHDL |
5.4.13. get_response_burst_size()
Prototype: |
bit [AV_BURSTCOUNT_W-1:0]get_response_burst_size() |
Arguments: |
Verilog HDL: None
VHDL: response_burst_size, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Returns the size of the response transaction burst count in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.14. get_response_data()
Prototype: |
bit [AV_DATA_W-1:0] get_response_data(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_data, index, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Returns the transaction read data in the response descriptor that has been removed from the response queue. Each cycle in a burst response is addressed individually by the specified index. In the case of read responses, the data is the data captured on the avm_readdata interface pin. In the case of write responses, the data on the driven avm_writedata pin is captured and reflected here. |
Language support: | Verilog HDL, VHDL |
5.4.15. get_response_latency()
Prototype: |
int get_response_latency(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_data, index, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Returns the transaction read latency in the response descriptor that has been removed from the response queue. Each cycle in a burst read has its own latency entry. |
Language support: | Verilog HDL, VHDL |
5.4.16. get_response_queue_size()
Prototype: |
int get_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately remove from the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
5.4.17. get_response_read_id()
Prototype: |
[AV_TRANSACTIONID_W-1:0] get_response_read_id() |
Arguments: |
Verilog HDL: None
VHDL: response_read_id, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Returns the read id of the transaction in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.18. get_response_read_response()
Prototype: |
bit[2**(AV_BURSTCOUNT_W-1) - 1:0] [AV_READRESPONSE_W-1:0] get_response_read_response(int index) |
Arguments: |
Verilog HDL:
int index
VHDL: response_read_response, int index, bfm_id, req_if(bfm_id) |
Returns: |
AvalonReadResponse_t |
Description: |
Returns the transaction read status in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.19. get_response_request()
Prototype: |
enum int[REQ_READ = 0, REQ_WRITE = 1, RED_IDLE = 2] get_response_request() |
Arguments: |
Verilog HDL: None
VHDL: response_request, bfm_id, req_if(bfm_id) |
Returns: |
Request_t |
Description: |
Returns the transaction command type in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.20. get_response_wait_time()
Prototype: |
int get_response_wait_time(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_wait_time, index, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Returns the wait latency for transaction in the response descriptor that has been removed from the response queue. Each cycle in a burst has its own wait latency entry. |
Language support: | Verilog HDL, VHDL |
5.4.21. get_response_write_id()
Prototype: |
bit [AV_TRANSACTIONID_W-1:0] get_response_write_id() |
Arguments: |
Verilog HDL: None
VHDL: response_write_id, index, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Returns the write id of the transaction in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
5.4.22. get_write_response_status()
Prototype: |
get_write_response_status() |
Arguments: |
Verilog HDL: None VHDL: write_response_status, bfm_id, req_if(bfm_id) |
Returns: |
AvalonResponseStatus_t |
Description: |
Returns the transaction response status in the write response descriptor that has been popped from the response queue. If the API is called when write response is not enabled, or when it is enabled but not requested, the API returns the default value, i.e. OKAY. |
Language support: | Verilog HDL, VHDL |
5.4.23. get_write_response_queue_size()
Prototype: |
int get_write_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: write_response_queue_size, index, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the write response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately pop off the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
5.4.24. get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
String |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 14.1 sp1 is encoded as "14.1.1". |
Language support: | Verilog HDL |
5.4.25. init()
Prototype: |
init |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Initializes the Avalon-MM master interface. |
Language support: | Verilog HDL, VHDL |
5.4.26. pop_response()
Prototype: |
void pop_response() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Removes the oldest response descriptor from the response queue, such that transaction information is available using the get_response_<rolename> commands. |
Language support: | Verilog HDL, VHDL |
5.4.27. push_command()
Prototype: |
void push_command() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Inserts the fully populated transaction descriptor onto the pending transaction command queue. |
Language support: | Verilog HDL, VHDL |
5.4.28. set_clken()
Prototype: |
void set_clken(bit state) |
Arguments: |
Verilog HDL:
bit state
VHDL: bit state, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the assertion and deassertion of the clock enable signal. |
Language support: | Verilog HDL, VHDL |
5.4.29. set_command_address()
Prototype: |
void set_command_address(bit[AV_ADDRESS_W-1:0]addr) |
Arguments: |
Verilog HDL:
addr
VHDL: addr, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction address in the command descriptor. |
Language support: | Verilog HDL, VHDL |
5.4.30. set_command_arbiterlock()
Prototype: |
void set_command_arbiterlock (bit state) |
Arguments: |
Verilog HDL:
bit state
VHDL: bit state, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Controls the assertion or deassertion of the arbiterlock interface signal. The arbiterlock control is on the transaction boundaries and is not used when the Avalon-MM Master BFM is operating in burst mode. |
Language support: | Verilog HDL, VHDL |
5.4.31. set_command_byte_enable()
Prototype: |
void set_command_byte_enable(bit[AV_NUMSYMBOLS-1:0] byte_enable, int index) |
Arguments: |
Verilog HDL:
byte_enable,
index
VHDL: byte_enable, index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction byte enable field for the cycle of the burst command descriptor indicated by index. This field applies to both read and write operations. |
Language support: | Verilog HDL, VHDL |
5.4.32. set_command_burst_count()
Prototype: |
void set_command_burst_count(bit[AV_BURSTCOUNT_W-1:0] burst_count) |
Arguments: |
Verilog HDL:
burst_count
VHDL: burst_count, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the value driven on the Avalon interface burstcount pin. Generates a warning message if the specified burst_count is out of range. Not available if the USE_BURSTCOUNT parameter is false. |
Language support: | Verilog HDL, VHDL |
5.4.33. set_command_burst_size()
Prototype: |
void set_command_burst_size (bit[AV_BURSTCOUNT_W-1:0] burst_size) |
Arguments: |
Verilog HDL:
burst_size
VHDL: burst_size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction burst count in the command descriptor to determine the number of words driven on the write burst command. The value might be different from the value specified in set_command_burst_count to generate illegal traffic for testing. Generates a warning if the value is different. |
Language support: | Verilog HDL, VHDL |
5.4.34. set_command_data()
Prototype: |
void set_command_data(bit[AV_DATA_W-1:0] data, int index) |
Arguments: |
Verilog HDL:
data,
index
VHDL: data, index,bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction write data in the command descriptor. For burst transactions, the command descriptor holds an array of data, with each element individually set by this method. |
Language support: | Verilog HDL, VHDL |
5.4.35. set_command_debugaccess()
Prototype: |
void set_command_debugaccess |
Arguments: |
Verilog HDL: bit
state
VHDL: bit state, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Controls the assertion or deassertion of the debugaccess interface signal. The debugaccess control is on transaction boundaries. |
Language support: | Verilog HDL, VHDL |
5.4.36. set_command_idle()
Prototype: |
void set_command_idle(int idle, int index) |
Arguments: |
Verilog HDL: int
idle, int index
VHDL: int idle, int index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets idle cycles at the end of each transaction cycle. For read commands, idle cycles are inserted at the end of the command cycle. For burst write commands, idle cycles are inserted at the end of each write data cycle within the burst. |
Language support: | Verilog HDL, VHDL |
5.4.37. set_command_init_latency()
Prototype: |
void set_command_init_latency(int cycles) |
Arguments: |
Verilog HDL:
cycles
VHDL: cycles, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the number of cycles to postpone the start of a command. |
Language support: | Verilog HDL, VHDL |
5.4.38. set_command_lock()
Prototype: |
void set_command_lock (bit state) |
Arguments: |
Verilog HDL: bit
state
VHDL: bit state, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Controls the assertion or deassertion of the lock interface signal. Lock control is on the transaction boundaries. It is not used when the Avalon-MM Master BFM is operating in burst mode. |
Language support: | Verilog HDL, VHDL |
5.4.39. set_command_request()
Prototype: |
void set_command_request(Request_t request) |
Arguments: |
Verilog HDL:
Request_t request
VHDL: Request_t request, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction type to read or write in the command descriptor. The enumeration type defines REQ_READ = 0 and REQ_WRITE = 1. |
Language support: | Verilog HDL, VHDL |
5.4.40. set_command_timeout()
Prototype: |
void set_command_timeout(int cycles) |
Arguments: |
Verilog HDL: int
cycles
VHDL: int cycles, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the number of elapsed cycles between waiting for a waitrequest and when time out is asserted. Disables time-out by setting the value to 0. |
Language support: | Verilog HDL, VHDL |
5.4.41. set_command_transaction_id()
Prototype: |
void set_command_transaction_id(bit[AV_TRANSACTIONID_W-1:0] id) |
Arguments: |
AvalonTransactionId_t id.
Verilog HDL: tid VHDL: tid , bfm_id,req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction id number in the command descriptor. |
Language support: | Verilog HDL, VHDL |
5.4.42. set_command_write_response_request()
Prototype: |
void set_command_write_response_request (logic request) |
Arguments: |
Verilog HDL:
request
VHDL: request, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the flag that enables or disables the write response requests in the command descriptor. |
Language support: | Verilog HDL, VHDL |
5.4.43. set_max_command_queue_size()
Prototype: |
void set_max_command_queue_size(int size) |
Arguments: |
Verilog HDL: int size
VHDL: int size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the pending command queue size maximum threshold. |
Language support: | Verilog HDL, VHDL |
5.4.44. set_min_command_queue_size()
Prototype: |
void set_min_command_queue_size(int size) |
Arguments: |
Verilog HDL: int size
VHDL: int size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the pending command queue size minimum threshold. |
Language support: | Verilog HDL, VHDL |
5.4.45. set_response_timeout()
Prototype: |
void set_response_timeout(int cycles) |
Arguments: |
Verilog HDL: int
cycles
VHDL: int cycles, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the number of cycles that may elapse before response time out. Disable time-out by setting the value to 0. |
Language support: | Verilog HDL, VHDL |
5.4.46. signal_all_transactions_complete
Prototype: |
signal_all_transactions_complete |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that all queued transactions have completed. |
Language support: | Verilog HDL |
5.4.47. signal_command_issued
Prototype: |
signal_command_issued |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the currently pending command has been driven to the interface. |
Language support: | Verilog HDL |
5.4.48. signal_fatal_error
Prototype: |
signal_fatal_error |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a fatal error has occurred in this module. |
Language support: | Verilog HDL |
5.4.49. signal_max_command_queue_size
Prototype: |
signal_max_command_queue_size |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the maximum pending transaction queue size threshold has been exceeded. |
Language support: | Verilog HDL |
5.4.50. signal_min_command_queue_size
Prototype: |
signal_min_command_queue_size |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the pending transaction queue size is below the minimum threshold. |
Language support: | Verilog HDL |
5.4.51. signal_read_response_complete
Prototype: |
signal_read_response_complete |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the read response has been received and inserted into the response queue. |
Language support: | Verilog HDL |
5.4.52. signal_response_complete
Prototype: |
signal_response_complete |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Triggers when either signal_read_response_complete or signal_write_response_complete is triggered. |
Language support: | Verilog HDL |
5.4.53. signal_write_response_complete
Prototype: |
signal_write_response_complete |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the write response has been received and inserted into the response queue. |
Language support: | Verilog HDL |
6. Avalon-MM Slave BFM
- Reads and writes typical of simple peripherals
- Reads, writes, burst reads, and burst writes for typical memory devices
This BFM also includes a procedural interface to implement the following functions:
- Monitoring of incoming commands
- Passing incoming commands to the test program
- Accepting response transactions from the test program
- Driving responses
The following figure shows the top-level modules for a testbench. This testbench uses the Avalon-MM Slave BFM to verify an Avalon-MM Master device. In addition to the The example testbench includes the following components:
- Avalon-MM Slave BFM
- A test program
- The DUT
The test program is written in HDL. It implements the following functions:
- Programs the Avalon-MM master to issue Avalon-MM transactions
- Programs the Avalon-MM Slave BFM to respond
- Analyzes the results
6.1. Timing
Symbol | Description |
---|---|
Twt_1 | The response wait time, which is three cycles. The slave sets this value using the set_interface_wait_time command. |
Twr | waitrequest is sampled #1 after the falling edge of clk. |
Twt_2 | The response wait time for the first read, which is 2 cycles. The slave sets this value using the set_interface_wait_time command. |
Scr_1–Scr_2 | Signals when read commands were received. The event name is signal_command_received. |
Trl_1,Trl_2 | The response latency for the reads, which is 3 cycles. The slave sets this time using the set_response_latency command. |
Twrl_1 | The write response latency for the first write, which is 3 cycles. This is the time between when the write command is accepted, and the write response is provided by the slave. T |
Src_1,Src_3 | Signals write responses. The event name is signal_response_issued. |
Src_2,Src_4 | Signals read responses. The event name is signal_response_issued. |
TID_1–TID_4 | Reference number to identify each read or write transaction. |
ID_1, ID_3 | Reference number to identify write transactions. |
ID_2, ID_4 | Reference number to identify read transactions. |
Symbol | Description |
---|---|
Ti | The initial command latency which is two cycles for transactions 1 and 2. |
Twt_1 | The response wait time which is 3 cycles. The master gets this value using the get_response_wait_time command. |
Twt_2 | The response wait time for the first read, which is 2 cycles. The slave sets this value using the set_interface_wait_time command. |
Twr | waitrequest is sampled #1 after the falling edge of clk. |
Trl_1 | The response latency for the first read, which is 0 cycles. The master gets this time using the get_response_latency command. |
Scr_1, Scr_2 | Signals write and read commands. The event name is signal_command_issued. |
Src_1 | Signals the first read response. The event name is signal_response_complete. |
Satc | Signals the end of the test. The event name is signal_all_transactions_complete |
6.2. Block Diagram
- Avalon-MM Slave API—Provides methods to get commands and create responses to commands from the Avalon-MM master (DUT).
- Command Descriptor—Accumulates the fields of a command sent by the Avalon-MM master. Sends completed commands to the Avalon-MM Slave BFM when requested.
- Avalon-MM Interface Monitor—Monitors activity coming from the Avalon-MM Master (DUT). Stores commands in the Client Command Queue.
- Response Generator and Data Cache— In memory_mode the Slave BFM models a single port RAM. A write operation stores the data in an associative array and generates no response. A read operation fetches data from the array and drives it on the response side of the Avalon interface. This mode simplifies loopback testing.
- Avalon-MM Slave Interface Driver—Drives responses to the system interconnect fabric. For burst transfers, there is a separate transfer for each word of the burst. The client testbench can instruct the Slave BFM to assert waitrequest for each word of the burst to test the functionality of the Avalon-MM master.
- Public Events—Provides status response
that arrives together with the data. The public event signals indicate the
status of the Master’s request such as successful completion, timeout, or
error.
Figure 10. Avalon-MM Slave BFM Block Diagram
6.3. Parameters
Parameter | Default Value | Legal Values | Description |
---|---|---|---|
Port Widths | |||
Address width | 32 | N/A | Address width in bits. |
Symbol width | 8 | N/A | Data symbol width in bits. Set AV_SYMBOL_W to 8 for byte-oriented interfaces. |
Read Response width | 8 | N/A | Read status response width in bits. |
Write Response width | 8 | N/A | Write status response width in bits. |
Parameters | |||
Number of symbols | 4 | N/A | Number of symbols per word. |
Burstcount width | 3 | N/A | The width of the burst count in bits. |
Port Enables | |||
Use the read signal | On | On/Off | When On, the interface includes a read pin. |
Use the write signal | On | On/Off | When On, the interface includes a write pin. |
Use the address signal | On | On/Off | When On, the interface includes address pins. |
Use the byte enable signal | On | On/Off | When On, the interface includes byte_enable pins. |
Use the burstcount signal | On | On/Off | When On, the interface includes burstcount pins. |
Use the readdata signal | On | On/Off | When On, the interface includes a readdata pin. |
Use the readdatavalid signal | On | On/Off | When On, the interface includes a readdatavalid pin. |
Use the writedata signal | On | On/Off | When On, the interface includes a writedata pin. |
Use the begintransfer signal | Off | On/Off | When On, the interface includes writedata pins. |
Use the beginbursttransfer signal | Off | On/Off | When On, the interface includes a beginbursttransfer pin. |
Use the arbiterlock signal | Off | On/Off | When On, the interface includes an arbiterlock pin. |
Use the lock signal | Off | On/Off | When On, the interface includes a lock pin. |
Use the debugaccess signal | Off | On/Off | When On, the interface includes a debugaccess pin. |
Use the waitrequest signal | On | On/Off | When On, the interface includes a waitrequest pin. |
Use the transactionid signal | Off | On/Off | When On, the interface includes a transactionid pin. |
Use the write response signals | Off | On/Off | When On, the interface includes a writeresponse pin. |
Use the read response signals | Off | On/Off | When On, the interface includes a readresponse pin. |
Use the clken signals | Off | On/Off | When On, the interface includes a clken pin. |
Port Polarity | |||
Assert reset high | On | On/Off | When On, reset is asserted high. |
Assert waitrequest high | On | On/Off | When On, waitrequest is asserted high. |
Assert read high | On | On/Off | When On, read is asserted high. |
Assert write high | On | On/Off | When On, write is asserted high. |
Assert byteenable high | On | On/Off | When On, byteenable is asserted high. |
Assert readdatavalid high | On | On/Off | When On, readdatavalid is asserted high. |
Assert arbiterlock high | On | On/Off | When On, arbiterlock is asserted high. |
Assert lock high | On | On/Off | When On, lock is asserted high. |
Burst Attributes | |||
Linewrap burst | On | On/Off | When On, the address for bursts wraps instead of an incrementing. With a wrapping burst, when the address reaches a burst boundary, it wraps back to the previous burst boundary. Consequently, only the low order bits need to be used for addressing. |
Burst on burst boundaries only | On | On/Off | When On, memory bursts are aligned to the address size. |
Miscellaneous | |||
Maximum pending reads | 1 | N/A | The maximum number of pending reads which can be queued up by the slave. |
VHDL BFM ID | 0 | 0–1023 | For VHDL BFMs only. Use this option to assign a unique number to each BFM in the testbench design. |
Timing | |||
Fixed read latency (cycles) | 0 | N/A | Sets the read latency for fixed-latency slaves. Not used on interfaces that include the readdatavalid signal. |
Fixed read wait time (cycles) | 1 | N/A | For slave interfaces that do not use the waitrequest signal. The read wait time indicates the number of cycles before the slave responds to a read. The timing is as if the slave asserted waitrequest for this number of cycles. |
Fixed write wait time (cycles) | 0 | N/A | For slave interfaces that do not use the waitrequest signal. The write wait time indicates the number of cycles before the slave accepts a write. |
Registered waitrequest | On | On/Off | Specifies whether to turn on the register stage. |
Registered Incoming Signals | On | On/Off | Specifies whether to register incoming signals. |
Interface Address Type | |||
Set slave interface address type to symbols or words | WORDS | WORDS/ SYMBOLS | Sets slave interface address type to symbols or words. |
6.4. Avalon-MM Slave BFM API
event_error_exceed_max_pending_reads()
Prototype: |
event_error_exceed_max_pending_reads () |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id, req_if |
Returns: |
void |
Description: |
Notifies the testbench that the BFM has more than the maximum pending reads in the pipelined read commands queue waiting to be processed. |
Language support: | VHDL |
6.4.1. event_command_received()
Prototype: |
event_command_received () |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a command was received. |
Language support: | VHDL |
6.4.2. event_response_issued()
Prototype: |
event_response_issued () |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a response was driven to the interface. |
Language support: | VHDL |
6.4.3. event_max_response_queue_size()
Prototype: |
event_max_response_queue_size () |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the response queue size has reached the threshold limit. |
Language support: | VHDL |
6.4.4. event_min_response_queue_size()
Prototype: |
event_min_response_queue_size () |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the response queue size is below the minimum limit. |
Language support: | VHDL |
6.4.5. get_clken()
Prototype: |
logic get_clken() |
Arguments: |
Verilog HDL: None
VHDL: clken, bfm_id, req_if(bfm_id) |
Returns: |
logic |
Description: |
Returns the clock enable signal status. |
Language support: | Verilog HDL, VHDL |
6.4.6. get_command_address()
Prototype: |
bit [AV_ADDRESS_W-1:0] get_command_address() |
Arguments: |
Verilog HDL: None
VHDL: command_address, bfm_id, req_if(bfm_id) |
Returns: |
bit [AV_ADDRESS_W-1:0] |
Description: |
Queries the received command descriptor for the transaction address. |
Language support: | Verilog HDL, VHDL |
6.4.7. get_command_arbiterlock()
Prototype: |
bit get_command_arbiterlock() |
Arguments: |
Verilog HDL: None
VHDL: command_arbiterlock, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction arbiterlock. |
Language support: | Verilog HDL, VHDL |
6.4.8. get_command_burst_count()
Prototype: |
[AV_BURSTCOUNT_W-1:0] get_command_burst_count() |
Arguments: |
Verilog HDL: None
VHDL: command_burst_count, bfm_id, req_if(bfm_id) |
Returns: |
[AV_BURSTCOUNT_W-1:0] |
Description: |
Queries the received command descriptor for the transaction burst count. |
Language support: | Verilog HDL, VHDL |
6.4.9. get_command_burst_cycle()
Prototype: |
int get_command_burst_cycle() |
Arguments: |
Verilog HDL: None
VHDL: command_burst_cycle, bfm_id, req_if(bfm_id) |
Returns: |
Int |
Description: |
The slave BFM receives and processes write burst commands as a sequence of discrete commands. The number of commands corresponds to the burst count. A separate command descriptor is constructed for each write burst cycle. Each command corresponds to a partially completed burst. This method returns a burst cycle field telling the testbench which burst cycle was active when this descriptor was constructed. This facility enables the testbench to query partially completed write burst operations.The testbench can query the write data word on each burst cycle as it arrives. Consequently, the testbench can begin to process it immediately rather than waiting until the entire burst has been received. This facility means you can implement pipelined write burst processing in the testbench. |
Language support: | Verilog HDL, VHDL |
6.4.10. get_command_byte_enable()
Prototype: |
bit [AV_NUMSYMBOLS-1:0] get_command_byte_enable (int index) |
Arguments: |
Verilog HDL:
index
VHDL: command_byte_enable, index, bfm_id, req_if(bfm_id) |
Returns: |
bit [AV_NUMSYMBOLS-1:0] |
Description: |
Queries the received command descriptor for the transaction byte enable. For burst commands with burst count greater than 1, the index selects the data cycle. |
Language support: | Verilog HDL, VHDL |
6.4.11. get_command_data()
Prototype: |
bit [AV_DATA_W-1:0] get_command_data(int index) |
Arguments: |
Verilog HDL:
index
VHDL: command_data, index, bfm_id, req_if(bfm_id) |
Returns: |
bit [AV_DATA_W-1:0] |
Description: |
Queries the received command descriptor for the transaction write data. For burst commands with burst count greater than 1, the index selects the write data cycle. |
Language support: | Verilog HDL, VHDL |
6.4.12. get_command_debugaccess()
Prototype: |
bit get_command_debugaccess() |
Arguments: |
Verilog HDL: None
VHDL:command_debugaccess, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction debug access. |
Language support: | Verilog HDL, VHDL |
6.4.13. get_command_queue_size()
Prototype: |
int get_command_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: command_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the command queue to determine number of pending commands. |
Language support: | Verilog HDL, VHDL |
6.4.14. get_command_lock()
Prototype: |
bit get_command_lock() |
Arguments: |
Verilog HDL: None
VHDL: command_lock, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction lock. |
Language support: | Verilog HDL, VHDL |
6.4.15. get_command_request()
Prototype: |
Request_t get_command_request() |
Arguments: |
Verilog HDL: None
VHDL: command_request, bfm_id, req_if(bfm_id) |
Returns: |
Request_t (enumerated type) |
Description: |
Gets the received command descriptor to determine command request type. A command type may be REQ_READ or REQ_WRITE. These type values are defined in the enumerated type called Request_t, which is imported with the package named altera_avalon_mm_pkg. |
Language support: | Verilog HDL, VHDL |
6.4.16. get_command_transaction_id()
Prototype: |
AvalonTransactionId_t get_command_transaction_id() |
Arguments: |
Verilog HDL: None
VHDL: command_transaction, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Queries the received command descriptor for the transaction ID. |
Language support: | Verilog HDL, VHDL |
6.4.17. get_command_write_response_request()
Prototype: |
AvalonTransactionId_t get_command_write_response_request() |
Arguments: |
Verilog HDL: None
VHDL: command_write_response_request, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Queries the received command descriptor for the write_response_request field value. A value of 1 indicates that the master has requested for a write response. |
Language support: | Verilog HDL, VHDL |
6.4.18. get_pending_read_latency_cycle()
Prototype: |
int get_pending_read_latency_cycle() |
Arguments: |
Verilog HDL: None
VHDL: pending_read_latency_cycle, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the read command queue to determine the cycles needed for the Slave BFM to complete the current read response. This method notifies the master when the Slave BFM is ready to receive a command. |
Language support: | Verilog HDL, VHDL |
6.4.19. get_pending_write_latency_cycle()
Prototype: |
int get__cycle() |
Arguments: |
Verilog HDL: None
VHDL: pending_write_latency, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the write command queue to determine the cycles needed for the Slave BFM to complete the current write response. |
Language support: | Verilog HDL, VHDL |
6.4.20. get_response_queue_size()
Prototype: |
int get_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the response queue to determine number of response descriptors pending. |
Language support: | Verilog HDL, VHDL |
6.4.21. vget_slave_bfm_status
Prototype: |
bit get_slave_bfm_status |
Arguments: |
Verilog HDL: None
VHDL: slave_bfm_status, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the Slave BFM component to determine when the read transaction in the Slave BFM has reached the maximum read transactions. A return value of 1 means that the Slave BFM can no longer accept a new read command. |
Language support: | Verilog HDL, VHDL |
6.4.22. get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
String |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 10.1 sp1 is encoded as "10.1.1". |
Language support: | Verilog HDL |
6.4.23. init()
Prototype: |
init() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Initializes the Avalon-MM slave interface. |
Language support: | Verilog HDL, VHDL |
6.4.24. pop_command()
Prototype: |
void pop_command() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Removes the command descriptor from the queue so that the testbench can query it using the get_command methods. |
Language support: | Verilog HDL, VHDL |
6.4.25. push_response()
Prototype: |
void push_response() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Inserts the fully populated response transaction descriptor onto the response queue. The BFM removes response descriptors from the queue as soon as they are available. The BFM reads them and drives the Avalon-MM interface response plane. |
Language support: | Verilog HDL, VHDL |
6.4.26. set_command_transaction_mode()
Prototype: |
void set_command_transaction_mode (int mode); |
Arguments: |
Verilog HDL:
mode
VHDL: mode, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
By default, write burst commands are consolidated into a single command transaction. The single command transaction contains the write data for all burst cycles in that command. This mode is set when the mode argument equals 0. When the mode argument is set to 1, the write burst commands yield one command transaction per burst cycle. |
Language support: | Verilog HDL, VHDL |
6.4.27. set_interface_wait_time()
Prototype: |
void set_interface_wait_time(int wait_cycles, int index) |
Arguments: |
Verilog HDL:
wait_cycles,
index
VHDL: wait_cycles, index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Specifies zero or more wait states to assert in each Avalon burst cycle by driving waitrequest active. With write burst commands, each write data cycle must wait the number of cycles corresponding to the cycle index. With read burst commands, there is only one command cycle corresponding to index 0 which can be forced to wait. |
Language support: | Verilog HDL, VHDL |
6.4.28. vset_max_response_queue_size()
Prototype: |
void set_max_response_queue_size(int size) |
Arguments: |
Verilog HDL:
int size
VHDL: int size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the maximum pending response queue size threshold. |
Language support: | Verilog HDL, VHDL |
6.4.29. set_min_response_queue_size()
Prototype: |
void set_min_response_queue_size(int size) |
Arguments: |
Verilog HDL:
int size
VHDL: int size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the minimum pending response queue size threshold. |
Language support: | Verilog HDL, VHDL |
6.4.30. set_read_response_id()
Prototype: |
void set_read_respose_id(AvalonTransactionId_t id) |
Arguments: |
Verilog HDL:
AvalonTransactionId_t
id
VHDL: AvalonTransactionId_t id, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction ID on the avs_readid pin. |
Language support: | Verilog HDL, VHDL |
6.4.31. set_read_response_status()
Prototype: |
void set_read_respose_status(AvalonReadResponse_t status, int index) |
Arguments: |
Verilog HDL:
AvalonReadResponse_t
status,
int index
VHDL: AvalonReadResponse_t status, int index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the read response status code. |
Language support: | Verilog HDL, VHDL |
6.4.32. set_response_burst_size()
Prototype: |
void set_response_burst_size(bit [AV_BURSTCOUNT_W-1:0] burst_size). |
Arguments: |
Verilog HDL:
burst_size
VHDL: burst_size, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction burst count in the response descriptor. |
Language support: | Verilog HDL, VHDL |
6.4.33. set_response_data()
Prototype: |
void set_response_data(bit [AV_DATA_W-1:0] data, int index). |
Arguments: |
Verilog HDL:
data,
index
VHDL: data, index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction read data in the response descriptor. For burst transactions, the command descriptor holds an array of data, with each element individually set by this method. |
Language support: | Verilog HDL, VHDL |
6.4.34. set_response_latency()
Prototype: |
void set_response_latency(bit [31:0]latency, int index) |
Arguments: |
Verilog HDL:
latency,
index
VHDL: latency, index, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the response latency for read
commands. The response is driven latency number of
cycles after receiving the read command. Designs that set USE_READDATAVALID to 1, cannot set the response latency to 0. For read burst commands the following algorithm determines the read latency:
|
Language support: | Verilog HDL, VHDL |
6.4.35. set_response_request()
Prototype: |
void set_response_request(Request_t request) |
Arguments: |
Verilog HDL:
Request_t request
VHDL: Request_t request, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction type to read or write in the response descriptor. The enumeration type defines REQ_READ = 0 and REQ_WRITE = 1. |
Language support: | Verilog HDL, VHDL |
6.4.36. set_response_timeout()
Prototype: |
void set_response_timeout(int cycles) |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the number of cycles that may elapse before timing out. |
Language support: | Verilog HDL, VHDL |
6.4.37. set_write_response_id()
Prototype: |
void set_write_respose_id(AvalonTransactionId_t id) |
Arguments: |
Verilog HDL:
AvalonTransactionId_t
id
VHDL: AvalonTransactionId_t id, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the transaction ID on the avs_writeid pin. |
Language support: | Verilog HDL, VHDL |
6.4.38. set_write_response_status()
Prototype: |
void set_write_respose_status(AvalonResponseStatus_t status) |
Arguments: |
Verilog HDL: AvalonResponseStatus_t
status
VHDL: AvalonResponseStatus_t status, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Sets the write response status code. |
Language support: | Verilog HDL, VHDL |
6.4.39. signal_command_received()
Prototype: |
signal_command_received |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a command has been detected on an Avalon-MM port. The testbench can respond with a set_command_wait_time call on receiving this event to dynamically back pressure the driving Avalon-MM master. Alternatively, the previously set wait_time might be used continuously for a set of transactions. |
Language support: | Verilog HDL |
6.4.40. signal_error_exceed_max_pending_reads
Prototype: |
signal_error_exceed_max_pending_reads |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench of the error condition, in which the slave has more than max_pending_reads pipelined read commands queued and waiting to be processed. |
Language support: | Verilog HDL |
6.4.41. signal_max_response_queue_size
Prototype: |
signal_max_response_queue_size |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the maximum pending transaction queue size threshold has been exceeded. |
Language support: | Verilog HDL |
6.4.42. signal_min_command_queue_size
Prototype: |
signal_min_response_queue_size |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Signals that the pending transaction queue size is below the minimum threshold. |
Language support: | Verilog HDL |
6.4.43. signal_fatal_error
Prototype: |
signal_fatal_error |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a fatal error has occurred in this module. |
Language support: | Verilog HDL |
6.4.44. signal_response_issued
Prototype: |
signal_response_issued |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a response has been driven out on the Avalon bus. |
Language support: | Verilog HDL |
7. Avalon-MM Monitor
The Avalon-MM Monitor is implemented in SystemVerilog and uses the SystemVerilog Assertion (SVA) language. The SVA language is supported by the Synopsys VCS, and Mentor Graphics Questa simulators. If you are using ModelSim, the monitor component still compiles and simulates. However, the assertion checking is disabled.
The following figure shows a testbench that uses an Avalon-MM Monitor to test components with Avalon-MM interfaces. The monitor’s Avalon-MM Master interface is connected to a component’s Avalon-MM slave interface. An Avalon-MM Slave interface is connected to a component’s Avalon-MM master interface. The test program communicates with the monitor. The test program can use the monitor’s assertion checking and coverage groups to ensure that all legal parameter values for the DUT’s Avalon-MM interface are tested. The Avalon-MM Monitor also includes a transaction collector feature to collect and monitor transaction status.
7.1. Parameters
Parameter | Default Value | Legal Values | Description |
---|---|---|---|
Port Widths | |||
Address width | 32 | N/A | Address width in bits. |
Symbol width | 8 | N/A | Data symbol width in bits. The symbol width should be 8 for byte-oriented interfaces. |
Number of symbols | 4 | N/A | Numbers of symbols per word. |
Burstcount width | 3 | N/A | The width of the burst count in bits. |
Readresponse width | 8 | N/A | Read response signal width in bits. |
Writeresponse width | 8 | N/A | Write response signal width in bits. |
Port Enables | |||
Use the read signal | On | On/Off | When On, the interface includes a read pin. |
Use the write signal | On | On/Off | When On, the interface includes a write pin. |
Use the address signal | On | On/Off | When On, the interface includes address pins. |
Use the byte enable signal | On | On/Off | When On, the interface includes byte_enable pins. |
Use the burstcount signal | On | On/Off | When On, the interface includes burstcount pins. |
Use the readdata signal | On | On/Off | When On, the interface includes a readdata pin. |
Use the readdatavalid signal | On | On/Off | When On, the interface includes a readdatavalid pin. |
Use the writedata signal | On | On/Off | When On, the interface includes a writedata pin. |
Use the begintransfer signal | Off | On/Off | When On, the interface includes writedata pins. |
Use the beginbursttransfer signal | Off | On/Off | When On, the interface includes a beginbursttransfer pins. |
Use the waitrequest signal | On | On/Off | When On, the interface includes a waitrequest pin. |
Use the arbiterlock signal | Off | On/Off | When On, the interface includes an arbiterlock pin. |
Use the lock signal | Off | On/Off | When On, the interface includes a lock pin. |
Use the debugaccess signal | Off | On/Off | When On, the interface includes a debugaccess pin. |
Use the transactionid signal | Off | On/Off | When On, the interface includes a transactionid pin. |
Use the writeresponse signal | Off | On/Off | When On, the interface includes a writeresponse pin. |
Use the readresponse signal | Off | On/Off | When On, the interface includes a readresponse pin. |
Use the clken signals | Off | On/Off | When On, the interface includes a clken pin. |
Burst Attributes | |||
Linewrap burst | On | On/Off | When On, the address for bursts wraps instead of an incrementing. With a wrapping burst, when the address reaches a burst boundary, it wraps back to the previous burst boundary. Consequently, only the low order bits are used for addressing. |
Burst on burst boundaries only | On | On/Off | When On, memory bursts are aligned to the address size. |
Miscellaneous | |||
Read response timeout (cycles) | 100 | N/A | Specifies when a timeout occurs if readdatavalid is not asserted. |
Avalon write timeout (cycles) | 100 | N/A | Specifies when a timeout occurs if a burst write transfer has not completed. |
Waitrequest timeout (cycles) | 1024 | N/A | Timeout period for the continuous assertion of waitrequest. |
Maximum pending reads | 1 | N/A | Specifies the maximum number of pipelined reads that can be pending. |
Fixed read latency (cycles) | 0 | N/A | Sets the read latency for fixed-latency slaves. Not used on interfaces that include the readdatavalid signal. |
Maximum read latency (cycles) | 100 | N/A | Specifies the maximum read latency in cycle for test coverage function |
Maximum waitrequest read cycles (for coverage) | 100 | N/A | Specifies the maximum wait time allowed for read cycle for coverage. |
Maximum waitrequest write cycles (for coverage) | 100 | N/A | Maximum wait time allowed for write cycle for coverage. |
Maximum continuous read (cycles) | 5 | N/A | Maximum continuous read time allowed for coverage. |
Maximum continuous write (cycles) | 5 | N/A | Maximum continuous write time allowed for coverage. |
Maximum continuous waitrequest (cycles) | 5 | N/A | Maximum continuous wait request time allowed for coverage. |
Maximum continuous readdatavalid (cycles) | 5 | N/A | Maximum continuous readdatavalid time allowed for coverage. |
VHDL BFM ID | 0 | 0–1023 | For VHDL BFMs only. Use this option to assign a unique number to each BFM in the testbench design. |
Timing | |||
Fixed read wait time (cycles) | 1 | N/A | For master interfaces that do not use the waitrequest signal. The read wait time indicates the number of cycles before the master responds to a read. The timing is as if the master asserted waitrequest for this number of cycles. |
Fixed write wait time (cycles) | 0 | N/A | For master interfaces that do not use the waitrequest signal. The write wait time indicates the number of cycles before the master accepts a write. |
Registered waitrequest | Off | On/Off | Specifies whether to turn on the register stage. |
Registered Incoming Signals | Off | On/Off | Specifies whether to register incoming signals. |
7.2. Avalon-MM Monitor Assertion Checking API
By default all assertions are enabled. However, depending on the parameterization of the Avalon-MM interface, some assertions are automatically disabled. For example, you might have to turn off some assertion checking to avoid the monitors generating error messages when injecting protocol errors. Protocol errors are typically injected to test the Avalon-MM component’s error handling capability.
The names of all methods that enable assertions begin with set_enable_a. By default, if your testbench includes the Avalon-MM monitor, the checking function is enabled. You can disable checking with the DISABLE_ALTERA_AVALON_SIM_SVA macro.
7.2.1. set_enable_a_address_align_with_data_width()
Prototype: |
set_enable_a_address_align_with_data_width() |
Arguments: |
Verilog HDL:
Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures the byte address that the master uses is aligned with the data width. |
Language support: | Verilog HDL |
7.2.2. set_enable_a_beginbursttransfer_exist()
Prototype: |
set_enable_a_beginbursttransfer_exist() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures beginbursttransfer is asserted during a transfer. It is disabled when beginbursttransfer is not used. |
Language support: | Verilog HDL |
7.2.3. set_enable_a_beginbursttransfer_legal()
Prototype: |
set_enable_a_beginbursttransfer_legal() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures beginbursttransfer is asserted with a read or write signal. It is disabled when beginbursttransfer is not used. |
Language support: | Verilog HDL |
7.2.4. set_enable_a_beginbursttransfer_single_cycle()
Prototype: |
set_enable_a_beginbursttransfer_single_cycle() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures beginbursttransfer is asserted for a single cycle regardless of the behavior of the waitrequest signal. It is disabled when beginbursttransfer is not used. |
Language support: | Verilog HDL |
7.2.5. set_enable_a_begintransfer_exist()
Prototype: |
set_enable_a_begintransfer_exist() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures begintransfer is asserted during any single transfer. Disabled when either begintransfer is not supported. |
Language support: | Verilog HDL |
7.2.6. set_enable_a_begintransfer_legal()
Prototype: |
set_enable_a_begintransfer_legal() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures begintransfer is asserted together with either read or write. Disabled when either begintransfer is not supported. |
Language support: | Verilog HDL |
7.2.7. set_enable_a_begintransfer_single_cycle()
Prototype: |
set_enable_a_begintransfer_single_cycle() |
Arguments: |
Verilog HDL:
Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures begintransfer is asserted for only 1 cycle and not reasserted for any single transfer, regardless of the status of the waitrequest signal. |
Language support: | Verilog HDL |
7.2.8. set_enable_a_burst_legal()
Prototype: |
set_enable_a_burst_legal() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that the total number of assertions for the write and readdatavalid is the same as the burstcount for any burst transfer. Disabled when burst transfers are not supported. |
Language support: | Verilog HDL |
7.2.9. set_enable_a_byteenable_legal()
Prototype: |
set_enable_a_byteenable_legal() |
Arguments: |
Verilog HDL:
Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion
that ensures the
byteenable value is
legal value. Disabled when
byteenable is not
supported.
For more information about legal byte enables, refer to the Avalon Interface Specifications. |
Language support: | Verilog HDL |
7.2.10. set_enable_a_constant_during_burst()
Prototype: |
set_enable_a_constant_during_burst() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion ensuring address, burstcount, and byteenable are held constant in a write burst transfer. Disabled when waitrequest is not supported. Disabled when burst transfers are not supported. |
Language support: | Verilog HDL |
7.2.11. set_enable_a_constant_during_clk_disabled()
Prototype: |
set_enable_a_constant_during_clk_disabled() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that all signals are held constant if clken is deasserted. |
Language support: | Verilog HDL |
7.2.12. set_enable_a_constant_during_waitrequest()
Prototype: |
set_enable_a_constant_during_waitrequest() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion ensuring read, write, writedata, address, burstcount, and byteenable are held constant if waitrequest is asserted. Disabled when waitrequest is not supported. |
Language support: | Verilog HDL |
7.2.13. set_enable_a_exclusive_read_write()
Prototype: |
set_enable_a_exclusive_read_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures read and write are not asserted simultaneously. Disabled when either read or write is not supported. |
Language support: | Verilog HDL |
7.2.14. set_enable_a_half_cycle_reset_legal()
Prototype: |
set_enable_a_half_cycle_reset_legal() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures reset is asserted correctly. |
Language support: | Verilog HDL |
7.2.15. set_enable_a_less_than_burstcount_max_size()
Prototype: |
set_enable_a_less_than_burstcount_max_size() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures burstcount size is less than or equal to the maximum burst size, 2**(AV_BURSTCOUNT_W-1).Disabled when either burst transfers are not supported or the bust size is less than 1. |
Language support: | Verilog HDL |
7.2.16. set_enable_a_less_than_maximumpendingreadtransactions()
Prototype: |
set_enable_a_less_than_maximumpendingreadtransactions() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that the number of pending read transfers is less than maximumPendingReadTransactions. Disabled when either read is not supported or maximumPendingReadTransactions is less than 1. |
Language support: | Verilog HDL |
7.2.17. set_enable_a_no_readdatavalid_during_reset()
Prototype: |
set_enable_a_no_readdatavalid_during_reset() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that readdatavalid is deasserted if reset is asserted. Disabled when readdatavalid is not supported. |
Language support: | Verilog HDL |
7.2.18. set_enable_a_no_read_during_reset()
Prototype: |
set_enable_a_no_read_during_reset() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures read is deasserted if reset is asserted. Disabled when read is not supported. |
Language support: | Verilog HDL |
7.2.19. set_enable_a_no_write_during_reset()
Prototype: |
set_enable_a_no_write_during_reset() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures write is deasserted if reset is asserted. Disabled when write is not supported. |
Language support: | Verilog HDL |
7.2.20. set_enable_a_readid_sequence()
Prototype: |
set_enable_a_readid_sequence() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that verifies if the readid sequence follows the sequence of the transactionid. |
Language support: | Verilog HDL |
7.2.21. set_enable_a_read_response_sequence()
Prototype: |
set_enable_a_read_response_sequence() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures readdatavalid is asserted while read is asserted for the same read transfer. |
Language support: | Verilog HDL |
7.2.22. set_enable_a_read_response_timeout()
Prototype: |
set_enable_a_read_response_timeout() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures readdatavalid is asserted within maximum allowed timeout period. Disabled when either readdatavalid is not supported or the maximum allowed timeout period is less than 1. |
Language support: | Verilog HDL |
7.2.23. set_enable_a_register_incoming_signals()
Prototype: |
set_enable_a_register_incoming_signals() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures waitrequest is asserted at all times and deasserts a single clock cycle after a read or write transaction. |
Language support: | Verilog HDL |
7.2.24. set_enable_a_waitrequest_during_reset()
Prototype: |
set_enable_a_waitrequest_during_resetl() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that waitrequest is asserted if reset is asserted. Disabled when waitrequest is not supported. |
Language support: | Verilog HDL |
7.2.25. set_enable_a_waitrequest_timeout()
Prototype: |
set_enable_a_waitrequest_timeout() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures waitrequest is not asserted continuously for more than maximum allowed timeout period. Disabled when either waitrequest is not supported or the maximum timeout period is less than 1. |
Language support: | Verilog HDL |
7.2.26. set_enable_a_write_burst_timeout()
Prototype: |
set_enable_a_write_burst_timeout() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that ensures that the write burst transfer is completed within maximum allowed timeout period. Disabled when write burst transfers are not supported or the write burst timeout period is less than 1 cycle. |
Language support: | Verilog HDL |
7.2.27. set_enable_a_writeid_sequence()
Prototype: |
set_enable_a_writeid_sequence() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables an assertion that verifies if the writeid sequence follows the sequence of the transactionid. |
Language support: | Verilog HDL |
7.2.28. Coverage Group
To generate the coverage report when using the Synopsys VCS simulator, use the following command:
urg –dir simv.vdb
To generate the coverage report when using the ModelSim-Altera software, use the following command:
run –all coverage report –details –file report.rpt
7.2.28.1. set_enable_c_b2b_read_read()
Prototype: |
set_enable_c_b2b_read_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test back-to-back read transfers. This method is disabled when reads are not supported. |
Language support: | Verilog HDL |
7.2.28.2. set_enable_c_b2b_read_write()
Prototype: |
set_enable_c_b2b_read_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test a read transfer immediately followed by a write transfer. This method is disabled when reads or writes are not supported. |
Language support: | Verilog HDL |
7.2.28.3. set_enable_c_b2b_write_read()
Prototype: |
set_enable_c_b2b_write_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test a write transfer immediately followed by a read. This method is disabled if either reads or writes are not supported. |
Language support: | Verilog HDL |
7.2.28.4. set_enable_c_b2b_write_write()
Prototype: |
set_enable_c_b2b_write_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test back-to-back write transfers. This method is disabled if writes are not supported. |
Language support: | Verilog HDL |
7.2.28.5. set_enable_c_continuous_read()
Prototype: |
set_enable_c_continuous_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test continuous read transfers from 2 cycles until AV_MAX_CONTINUOUS_READ. Continuous read cycles of more than AV_MAX_CONTINUOUS_READ goes to another bin. |
Language support: | Verilog HDL |
7.2.28.6. set_enable_c_continuous_readdatavalid()
Prototype: |
set_enable_c_continuous_readdatavalid() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test continuous readdatavalid transfers from 2 cycles until AV_MAX_CONTINUOUS_READDATAVALID. Continuous read cycles of more than AV_MAX_CONTINUOUS_READDATAVALID goes to another bin. |
Language support: | Verilog HDL |
7.2.28.7. set_enable_c_continuous_waitrequest()
Prototype: |
set_enable_c_continuous_waitrequest() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test continuous waitrequest transfers from 2 cycles until AV_MAX_CONTINUOUS_WAITREQUEST. Continuous read cycles of more than AV_MAX_CONTINUOUS_WAITREQUEST goes to another bin. |
Language support: | Verilog HDL |
7.2.28.8. set_enable_c_continuous_waitrequest_from_idle_to_read()
Prototype: |
set_enable_c_continuous_waitrequest_from_idle_to_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test waitrequest transfers from their idle state until a waitrequest read. |
Language support: | Verilog HDL |
7.2.28.9. set_enable_c_continuous_waitrequest_from_idle_to_write()
Prototype: |
set_enable_c_continuous_waitrequest_from_idle_to_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test waitrequest transfers from their idle state until a waitrequest write. |
Language support: | Verilog HDL |
7.2.28.10. set_enable_c_continuous_write()
Prototype: |
set_enable_c_continuous_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test continuous write transfers from 2 cycles until AV_MAX_CONTINUOUS_WRITE. Continuous write cycles of more than AV_MAX_CONTINUOUS_WRITE goes to another bin. |
Language support: | Verilog HDL |
7.2.28.11. set_enable_c_idle_before_transaction()
Prototype: |
set_enable_c_idle_before_transaction() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to count idle cycles before read or write transactions. |
Language support: | Verilog HDL |
7.2.28.12. set_enable_c_idle_in_read_response()
Prototype: |
set_enable_c_idle_in_read_response() |
Arguments: |
Verilog HDL:
Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to count idle cycles during a read burst response. This method is disabled if reads or readdatavalids are not supported. |
Language support: |
Verilog HDL |
7.2.28.13. set_enable_c_idle_in_write_burst()
Prototype: |
set_enable_c_idle_in_write_burst() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to count idle cycles during a write burst transaction. This method is disabled if writes are not supported. |
Language support: | Verilog HDL |
7.2.28.14. set_enable_c_pending_read()
Prototype: |
set_enable_c_pending_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test pending read support. It covers all values for up to the maximum number of pending reads. This method is disabled when either reads or pipelined reads are not supported. |
Language support: | Verilog HDL |
7.2.28.15. set_enable_c_read()
Prototype: |
set_enable_c_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test read transfers. This method is disabled when reads are not supported. |
Language support: | Verilog HDL |
7.2.28.16. set_enable_c_read_after_reset()
Prototype: |
set_enable_c_read_after_reset() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test read transfers after reset. |
Language support: | Verilog HDL |
7.2.28.17. set_enable_c_read_burstcount()
Prototype: |
set_enable_c_read_burstcount() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group tests different sizes of burstcount during read burst transfers. Tests all possible values of burstcount. Disabled when either burst transfers or reads are not supported, or the maximum burst is less than 1. |
Language support: | Verilog HDL |
7.2.28.18. set_enable_c_read_byteenable()
Prototype: |
set_enable_c_read_byteenable() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group ensures all legal values of the byteenable signal are asserted during read transfers. It is disabled when either byteenable or read is not supported. |
Language support: | Verilog HDL |
7.2.28.19. set_enable_c_read_latency()
Prototype: |
set_enable_c_read_latency() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test all values of the read latency parameter. This method is disabled if read or readdatavalids are not supported, or if the maximum read latency is less than 1. |
Language support: | Verilog HDL |
7.2.28.20. set_enable_c_read_response()
Prototype: |
set_enable_c_read_response() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test each bit of the valid readresponse that represent different status. |
Language support: | Verilog HDL |
7.2.28.21. set_enable_c_waitrequest_in_write_burst()
Prototype: |
set_enable_c_waitrequest_in_write_burst() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test the values of the waitrequest parameter during write burst transfers. |
Language support: | Verilog HDL |
7.2.28.22. set_enable_c_waitrequested_read()
Prototype: |
set_enable_c_waitrequested_read() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test all values of the wait request timeout parameter during read transfers. This method is disabled if read or waitrequest are not supported or the waitrequestt timeout period is less than 1. |
Language support: | Verilog HDL |
7.2.28.23. set_enable_c_waitrequest_without_command()
Prototype: |
set_enable_c_waitrequest_without_command() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to verify that no command is asserted between the time when waitrequest is asserted until waitrequest is deasserted. |
Language support: | Verilog HDL |
7.2.28.24. set_enable_c_waitrequested_write()
Prototype: |
set_enable_c_waitrequested_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test all values of the waitrequest timeout parameter. Disabled if write or waitrequest are not supported or if the waitrequest timeout period is less than 1. |
Language support: | Verilog HDL |
7.2.28.25. set_enable_c_write()
Prototype: |
set_enable_c_write() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test write transfers. This method is disabled when writes are not supported. |
Language support: | Verilog HDL |
7.2.28.26. set_enable_c_write_with_and_without_writeresponserequest()
Prototype: |
set_enable_c_write_with_and_without_writeresponserequest() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test write transactions with or without writeresponserequest. |
Language support: | Verilog HDL |
7.2.28.27. set_enable_c_write_after_reset()
Prototype: |
set_enable_c_write_after_reset() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test write transfers after reset. |
Language support: | Verilog HDL |
7.2.28.28. set_enable_c_write_burstcount()
Prototype: |
set_enable_c_write_burstcount() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test different sizes of burstcount during write burst transfers. It tests all possible values of burstcount. Disabled when either burst transfers or writes are not supported, or the maximum burst is less than 1. |
Language support: | Verilog HDL |
7.2.28.29. set_enable_c_write_byteenable()
Prototype: |
set_enable_c_write_byteenable() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group ensuring all legal values of the byteenable signal are asserted during write transfers. It is disabled when either byteenable or write is not supported. |
Language support: | Verilog HDL |
7.2.28.30. set_enable_c_write_response()
Prototype: |
set_enable_c_write_response() |
Arguments: |
Verilog HDL: Boolean
VHDL: N.A. |
Returns: |
void |
Description: |
Enables a coverage group to test each bit of the valid writeresponse that represent different status. |
Language support: | Verilog HDL |
7.2.29. Transaction Monitoring
- Collects the transactions
- Encapsulates transactions into descriptors
- Inserts the transactions into a queue.
The API provides functions to query the transactions in the queue and disposes them as they are processed. By default the transaction collector module is disabled. You must define the ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING Verilog macro to enable this feature. This macro is required to ensure backward compatibility and to avoid breaking existing test cases.
7.2.29.1. event_transaction_fifo_threshold()
Prototype: |
event_transaction_fifo_threshold() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the transaction FIFO threshold level was exceeded. |
Language support: | VHDL |
7.2.29.2. event_transaction_fifo_overflow()
Prototype: |
event_transaction_fifo_overflow() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that the transaction FIFO is full and further transactions will be dropped. |
Language support: | VHDL |
7.2.29.3. event_command_received()
Prototype: |
event_command_received() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a command was received. |
Language support: | VHDL |
7.2.29.4. event_read_response_complete()
Prototype: |
event_read_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a read response was received. |
Language support: | VHDL |
7.2.29.5. event_write_response_complete()
Prototype: |
event_write_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a write response was received. |
Language support: | VHDL |
7.2.29.6. event_response_complete()
Prototype: |
event_response_complete() |
Arguments: |
Verilog HDL: N.A.
VHDL: bfm_id |
Returns: |
void |
Description: |
Notifies the testbench that a read/write response was received. |
Language support: | VHDL |
7.2.29.7. get_clken()
Prototype: |
logic get_clken() |
Arguments: |
Verilog HDL: None
VHDL: clken, bfm_id, req_if(bfm_id) |
Returns: |
logic |
Description: |
Returns the clock enable signal status. |
Language support: | Verilog HDL, VHDL |
7.2.29.8. get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
String |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, version 10.1 sp1 is encoded as "10.1.1". |
Language support: | Verilog HDL |
7.2.29.9. get_command_address()
Prototype: |
bit [AV_ADDRESS_W-1:0] get_command_address() |
Arguments: |
Verilog HDL: None
VHDL: command_address, bfm_id, req_if(bfm_id) |
Returns: |
bit [AV_ADDRESS_W-1:0] |
Description: |
Queries the received command descriptor for the transaction address. |
Language support: | Verilog HDL, VHDL |
7.2.29.10. get_command_arbiterlock()
Prototype: |
bit get_command_arbiterlock() |
Arguments: |
Verilog HDL: None
VHDL: command_arbiterlock, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction arbiterlock. |
Language support: | Verilog HDL, VHDL |
7.2.29.11. get_command_burst_count()
Prototype: |
[AV_BURSTCOUNT_W-1:0] get_command_burst_count() |
Arguments: |
Verilog HDL: None
VHDL: command_burst_count, bfm_id, req_if(bfm_id) |
Returns: |
[AV_BURSTCOUNT_W-1:0] |
Description: |
Queries the received command descriptor for the transaction burst count. |
Language support: | Verilog HDL, VHDL |
7.2.29.12. get_command_burst_cycle()
Prototype: |
int get_command_burst_cycle() |
Arguments: |
Verilog HDL: None
VHDL: command_burst_cycle, bfm_id, req_if(bfm_id) |
Returns: |
Int |
Description: |
The slave BFM
receives and processes write burst commands as a discrete sequence. The number
of commands corresponds to the burst count. A separate command descriptor is
constructed for each write burst cycle, corresponding to a partially completed
burst.
This method returns a burst cycle field specifying the burst cycle that was active when this descriptor was constructed. This facility enables the testbench to query partially completed write burst operations. The testbench can query the write data word on each burst cycle as it arrives. The testbench can begin to process it immediately. The testbench does not have to wait until the entire burst has been received. Consequently, it is possible to perform pipelined write burst processing in the testbench. |
Language support: | Verilog HDL, VHDL |
7.2.29.13. get_command_byte_enable()
Prototype: |
bit [AV_NUMSYMBOLS-1:0] get_command_byte_enable (int index) |
Arguments: |
Verilog HDL:
index
VHDL: command_byte_enable, index, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_NUMSYMBOLS-1:0] |
Description: |
Queries the received command descriptor for the transaction byte enable. For burst commands with burst count greater than 1, the index selects the data cycle. |
Language support: | Verilog HDL, VHDL |
7.2.29.14. get_command_data()
Prototype: |
bit [AV_DATA_W-1:0] get_command_data(int index) |
Arguments: |
Verilog HDL:
index
VHDL: command_data, index, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_DATA_W-1:0] |
Description: |
Queries the received command descriptor for the transaction write data. For burst commands with burst count greater than 1, the index selects the write data cycle. |
Language support: | Verilog HDL, VHDL |
7.2.29.15. get_command_debugaccess()
Prototype: |
bit get_command_debugaccess() |
Arguments: |
Verilog HDL: None
VHDL: command_debugaccess, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction debug access. |
Language support: | Verilog HDL, VHDL |
7.2.29.16. get_command_issued_queue_size()
Prototype: |
int get_command_issued_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: command_issued_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the command issued queue to determine number of pending commands. |
Language support: | Verilog HDL, VHDL |
7.2.29.17. get_command_queue_size()
Prototype: |
int get_command_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: command_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the command queue to determine number of pending commands. |
Language support: | Verilog HDL, VHDL |
7.2.29.18. get_command_lock()
Prototype: |
bit get_command_lock() |
Arguments: |
Verilog HDL: None
VHDL: command_lock, bfm_id, req_if(bfm_id) |
Returns: |
bit |
Description: |
Queries the received command descriptor for the transaction lock. |
Language support: | Verilog HDL, VHDL |
7.2.29.19. get_command_request()
Prototype: |
Request_t get_command_request() |
Arguments: |
Verilog HDL: None
VHDL: command_request, bfm_id, req_if(bfm_id) |
Returns: |
Request_t (enumerated type) |
Description: |
Gets the received command descriptor to determine command request type. A command type may be REQ_READ or REQ_WRITE. These type values are defined in the enumerated type called Request_t, which is imported with the package named altera_avalon_mm_pkg. |
Language support: | Verilog HDL, VHDL |
7.2.29.20. get_command_transaction_id()
Prototype: |
AvalonTransactionId_t get_command_transaction_id() |
Arguments: |
Verilog HDL: None
VHDL: command_transaction_id, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Queries the received command descriptor for the transaction ID. |
Language support: | Verilog HDL, VHDL |
7.2.29.21. get_command_write_response_request()
Prototype: |
AvalonTransactionId_t get_command_write_response_request() |
Arguments: |
Verilog HDL: None
VHDL: command_write_response_request, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Queries the received command descriptor for the write_response_request field value. A value of 1 indicates that the master has requested for a write response. |
Language support: | Verilog HDL, VHDL |
7.2.29.22. get_read_response_queue_size()
Prototype: |
int get_read_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: read_response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the read response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately remove from the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
7.2.29.23. get_response_address()
Prototype: |
bit [AV_ADDRESS_W-1:0] get_response_address() |
Arguments: |
Verilog HDL: None
VHDL: response_address, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_ADDRESS_W-1:0] |
Description: |
Returns the transaction address in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.24. get_response_byte_enable()
Prototype: |
bit [AV_NUMSYMBOLS-1:0] get_response_byte_enable(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_byte_enable, index, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_NUMSYMBOLS-1:0] |
Description: |
Returns the value of the byte enables in the response descriptor that has been removed from the response queue. Each cycle of a burst response is addressed individually by the specified index. |
Language support: | Verilog HDL, VHDL |
7.2.29.25. get_response_burst_size()
Prototype: |
bit [AV_BURSTCOUNT_W-1:0]get_response_burst_size() |
Arguments: |
Verilog HDL: None
VHDL: response_burst_size, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_BURSTCOUNT_W-1:0] |
Description: |
Returns the size of the response transaction burst count in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.26. get_response_data()
Prototype: |
bit [AV_DATA_W-1:0] get_response_data(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_data, index, bfm_id, req_if(bfm_id) |
Returns: |
bit[AV_DATA_W-1:0] |
Description: |
Returns the transaction read data in the response descriptor that was removed from the response queue. Each cycle in a burst response is addressed individually by the specified index. In the case of read responses, the data is the data captured on the avm_readdata interface pin. In the case of write responses, the data on the driven avm_writedata pin is captured and reflected here. |
Language support: | Verilog HDL, VHDL |
7.2.29.27. get_response_latency()
Prototype: |
int get_response_latency(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_latency, index, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Returns the transaction read latency in the response descriptor that has been removed from the response queue. Each cycle in a burst read has its own latency entry. |
Language support: | Verilog HDL, VHDL |
7.2.29.28. get_response_queue_size()
Prototype: |
int get_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
automatic int |
Description: |
Queries the response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately remove from the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
7.2.29.29. get_response_read_id()
Prototype: |
AvalonTransactionId_t get_response_read_id() |
Arguments: |
Verilog HDL: None
VHDL: response_read_id, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Returns the read id of the transaction in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.30. get_response_read_response()
Prototype: |
AvalonReadResponse_t get_response_read_response(int index) |
Arguments: |
Verilog HDL:
int index
VHDL: response_read_response, int index, bfm_id, req_if(bfm_id) |
Returns: |
AvalonReadResponse_t |
Description: |
Returns the transaction read status in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.31. get_response_request()
Prototype: |
Request_t get_response_request() |
Arguments: |
Verilog HDL: None
VHDL: response_request,bfm_id, req_if(bfm_id) |
Returns: |
Request_t |
Description: |
Returns the transaction command type in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.32. get_response_wait_time()
Prototype: |
int get_response_wait_time(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_wait_time, index, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Returns the wait latency for transaction in the response descriptor that has been removed from the response queue. Each cycle in a burst has its own wait latency entry. |
Language support: | Verilog HDL, VHDL |
7.2.29.33. get_response_write_id()
Prototype: |
AvalonTransactionId_t get_response_write_id() |
Arguments: |
Verilog HDL: None
VHDL: response_write_id, bfm_id, req_if(bfm_id) |
Returns: |
AvalonTransactionId_t |
Description: |
Returns the write id of the transaction in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.34. get_response_write_response()
Prototype: |
AvalonWriteResponse_t get_response_write_response(int index) |
Arguments: |
Verilog HDL:
index
VHDL: response_write_response, index, bfm_id, req_if(bfm_id) |
Returns: |
AvalonWriteResponse_t |
Description: |
Returns the transaction write status in the response descriptor that has been removed from the response queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.35. get_transaction_fifo_max()
Prototype: |
int get_transaction_fifo_max() |
Arguments: |
Verilog HDL: None
VHDL: transaction_fifo_max, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Gets the maximum transaction FIFO depth. |
Language support: | Verilog HDL, VHDL |
7.2.29.36. get_transaction_fifo_threshold()
Prototype: |
int get_transaction_fifo_threshold() |
Arguments: |
Verilog HDL: None
VHDL: transaction_fifo_threshold, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Gets the transaction FIFO threshold level. |
Language support: | Verilog HDL, VHDL |
7.2.29.37. get_write_response_queue_size()
Prototype: |
int get_write_response_queue_size() |
Arguments: |
Verilog HDL: None
VHDL: write_response_queue_size, bfm_id, req_if(bfm_id) |
Returns: |
int |
Description: |
Queries the write response queue to determine number of response descriptors currently stored in the BFM. This is the number of responses the test program can immediately remove from the response queue for further processing. |
Language support: | Verilog HDL, VHDL |
7.2.29.38. init()
Prototype: |
init() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Initializes the counters and clears the queue. |
Language support: | Verilog HDL, VHDL |
7.2.29.39. pop_command()
Prototype: |
pop_command() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
Void |
Description: |
Removes the command descriptor from the queue so that the testbench can query it with the get_command methods. |
Language support: | Verilog HDL, VHDL |
7.2.29.40. pop_response()
Prototype: |
void pop_response() |
Arguments: |
Verilog HDL: None
VHDL: bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
Removes the transaction descriptor from the queue so that the testbench can query it with the get_command methods. Sequence counter is initialized to 1. |
Language support: | Verilog HDL, VHDL |
7.2.29.41. set_command_transaction_mode()
Prototype: |
set_command_transaction_mode() |
Arguments: |
Verilog HDL:
int mode
VHDL: int mode, bfm_id, req_if(bfm_id) |
Returns: |
void |
Description: |
By default, write burst commands are consolidated into a single command transaction containing the write data for all burst cycles in that command. This mode is set when the mode argument equals 0. When the mode argument is set to 1, the default is overridden. Write burst commands yield one command transaction per burst cycle. |
Language support: | Verilog HDL, VHDL |
7.2.29.42. set_transaction_fifo_max()
Prototype: |
set_transaction_fifo_max() |
Arguments: |
Verilog HDL:
int level
VHDL: int level, bfm_id, req_if(bfm_id) |
Returns: |
void. |
Description: |
Sets the maximum transaction level of the FIFO. The event signal_transaction_fifo_max is triggered when this level is exceeded. |
Language support: | Verilog HDL, VHDL |
7.2.29.43. set_transaction_fifo_threshold()
Prototype: |
set_transaction_fifo_threshold() |
Arguments: |
Verilog HDL:
int level
VHDL: int level, bfm_id, req_if(bfm_id) |
Returns: |
void. |
Description: |
Sets the threshold alert level of the FIFO. The event signal_transaction_fifo_threshold is triggered when this level is exceeded. |
Language support: | Verilog HDL, VHDL |
7.2.29.44. signal_command_received
Prototype: |
signal_command_received |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a command was detected on the Avalon port. When this event is received, the testbench responds with a set_interface_wait_time call. This call dynamically backpressures the driving Avalon master. |
Language support: | Verilog HDL |
7.2.29.45. signal_fatal_error
Prototype: |
signal_fatal_error |
Arguments: |
Verilog HDL: None
VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that a fatal error has occurred in this module. |
Language support: | Verilog HDL |
7.2.29.46. signal_read_response_complete
Prototype: |
signal_read_response_complete |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that the read response has been received and inserted into the response queue. |
Language support: | Verilog HDL |
7.2.29.47. signal_response_complete
Prototype: |
signal_response_complete |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Triggers when either signal_read_response_complete or signal_write_response_complete is triggered. Indicates that either a read or a write response was received and inserted into the response queue. |
Language support: | Verilog HDL |
7.2.29.48. signal_transaction_fifo_overflow
Prototype: |
signal_transaction_fifo_overflow |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that the FIFO is full and further transactions are dropped. |
Language support: | Verilog HDL |
7.2.29.49. signal_transaction_fifo_threshold
Prototype: |
signal_transaction_fifo_threshold |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that the transaction FIFO threshold level has exceeded. |
Language support: | Verilog HDL |
7.2.29.50. signal_write_response_complete
Prototype: |
signal_write_response_complete |
Arguments: |
Verilog HDL: None VHDL: N.A. |
Returns: |
void |
Description: |
Notifies the testbench that the write response has been received and inserted into the response queue. |
Language support: | Verilog HDL |
8. Avalon-ST Source BFM
The following figure shows the top-level modules for a testbench. This testbench uses an Avalon-ST Source BFM to verify an Avalon-ST sink component. In addition to the Avalon-ST Source BFM component, the testbench typically includes a test program and the DUT.
8.1. Timing
Symbol | Description |
---|---|
Tidle | The idle time before a transactions. This time is set by the command set_transaction_idles. |
Trl_1 | The response latency for the first source to sink transaction, which is 3 cycles. The source gets this time using the get_response_latency command. |
Ssrc_dr | Signals that the source is driving valid data. The event name is signal_src_driving_transaction. |
Ssrc_rdy | Signals the source has received the assertion of ready from the sink. The event name is signal_src_ready. |
Stc | Signals the first transaction is complete. The event name is signal_src_transaction_complete. |
Ssrc_~rdy | Signals the source has received the deassertion of ready from the sink. The event name is signal_src_not_ready. |
8.2. Block Diagram
- Avalon-ST Source API—Provides methods to create Avalon-ST transactions and query the state of all queues.
- Transaction Descriptor—Accumulates the fields of an Avalon-ST command and inserts completed commands onto the pending command queue.
- Avalon-ST Physical Driver—Issues transfers and holds each transfer until ready is asserted.
- Physical Bus Monitor—Monitors the physical layer and reports on the status of the ready signal to the Physical Bus Driver and the Public Events module.
- Public Events—Signals the events described in the API.
- Response Descriptor—Collects
information about completed transactions.
Figure 14. Block Diagram of the Avalon-ST Source BFM
8.3. Parameters
Parameter | Default Value | Legal Values | Description |
---|---|---|---|
Port Enables | |||
Include the signals to support packets | Off | On/Off | When On, the interface includes the startofpacket, endofpacket, and empty signals. |
Use the channel port | Off | On/Off | When On, the interface includes channel pin or pins. |
Use the error port | Off | On/Off | When On, the interface includes error pin or pins. |
Use the ready port | On | On/Off | When On, the interface includes a ready pin. |
Use the valid port | On | On/Off | When |