Advanced Link Analyzer comes with the following executable files:

• adv_link_analyzer.exe—Advanced Link Analyzer’s main user interface
• adv_link_analyzer_sim_eng.exe—Advanced Link Analyzer simulation engine
• adv_link_analyzer_sim_eng_console.exe—Advanced Link Analyzer simulation engine (console version)
• adv_link_analyzer_data_viewer.exe—The Advanced Link Analyzer Data Viewer displays simulation results
• adv_link_analyzer_channel_viewer.exe—The Advanced Link Analyzer Channel Viewer displays channel characteristics
• adv_link_analyzer_batch_sim.exe—The Advanced Link Analyzer Batch Simulation Controller runs simulations in batch mode
• adv_link_analyzer_channel_designer.exe—Advanced Link Analyzer’s channel designer that generate S-parameter channel models for link simulations

Advanced Link Analyzer uses the following file extensions:

• .jne—Advanced Link Analyzer simulation configuration
• .jneschm—Advanced Link Analyzer simulation schematic configuration
• .jnetxdata, .jnerxdata, .jnedevdata, .jneledata, and others—Advanced Link Analyzer internal data

When you want to share a Advanced Link Analyzer link configuration, both .jne and .jneschm files are needed for other users to reload the link configuration in their Advanced Link Analyzer session. Make sure all other associated files, such as channel model files and device model files, are included so that simulations can run correctly. Advanced Link Analyzer provides limited backward compatibility with link configuration files saved in previous versions.

The following figure shows the jitter decomposition diagram and the breakdown of jitter components.

Figure 17. Transmitter Jitter Decomposition

Click Jitter/Noise Options to further configure each jitter and noise type. There are two jitter/noise modes for Advanced Link Analyzer’s transmitters: Jitter/Noise Component mode and DJ/RJ-DN/RJ mode. Only one jitter/noise mode is active at a time and you must determine which mode to use in your simulations.

• Jitter/Noise Component mode—Advanced Link Analyzer uses a flat jitter/noise structure that assumes no overlapping among all the jitter and noise components. Avoid double counting when inputting or importing jitter/noise figures. In the following figure, there are six specific jitter components: DCD, ISI, SJ, BUJ, RJ, and jitter PDF. The noise components DN, BUN, RN, and noise PDF must also be specified separately.
  Figure 18. Specifying Transmitter Jitter and Noise in Jitter/Noise Mode

  
  Figure 19. Transmitter Jitter/Noise Configuration in Jitter/Noise Component Mode

  

• DJ/RJ-DN/RJ mode—All deterministic jitter/noise components are included in DJ and DN.
  Figure 20. Specifying Transmitter Jitter and Noise in DJ/RJ-DN/RJ Mode

  
  Figure 21. Transmitter Jitter/Noise Configuration in DJ/RJ-DN/RJ Method

  

Termination tab

This section specifies the transmitter impedance.

Figure 22. Transmitter Advanced Options Window: Transmitter Termination

For selected Intel devices, use the TX Impedance pull-down menu to select a termination configuration. You can also customize the termination configuration by selecting the Custom option. When the Custom TX Impedance method is chosen, the termination can be configured as follows:

• Ideal TX termination—The transmitter is ideal with a 50 ohms (single-ended) termination.
• Non-ideal TX termination—Select one of the following options:
  • R—Transmitter impedance is modeled as a resistance R ohms (single-ended).
  • R//C1—Transmitter impedance is modeled as an RC network with a parallel resistor (in ohms) and a capacitance (in pF).
  • File Input (Frequency Real Imaginary)—Transmitter impedance is modeled by a frequency-dependent complex impedance table described in the input file.

For an Intel transmitter, the default termination configurations are automatically selected and specified.

Pulse Shaping tab

Advanced Link Analyzer supports three pulse shaping methods for Custom transmitters:

• Edge Rate—A pulse-shaping filter is generated by using a Gaussian low-pass filter that matches the specified edge rate.
• Rise/Fall Time —A pulse shaping filter is generated by using a Gaussian low-pass filter that matches the specified 20%-80% rise/fall time.
• S-parameter—A pulse-shaping filter is specified by your S-parameter file. Only the differential insertion loss (for example, S_dd21), is applied in the pulse shaping.
• For standards-based transmitters, for example, PCI Express^® 8GT/16GT, pulse shaping types and configurations are set by the transmitter model and, hence, cannot be changed. You can override the default standards-based transmitter model setting by checking the Override generic/standard device setting checkbox.

Figure 23. Transmitter Options: Pulse Shaping Configuration

PAM-n Options

• PAM-n Codec Method— Select PAM-n coder/decoder method. The selections are Default, Gray, and Linear. The default setting is Gray coding.
• PAM-n Gray Coding Option— Select Gray coding options. Selections are Default, MSB first, and LSB first. The default setting is MSB first.
• PAM-n TX Linearity— Set the linearity of PAM-n output waveform. PAM-n linearity means mismatch between amplitude levels. The default value is 1.0. The PAM-n TX linearity is defined in the same way as specified in IEEE 802.3 PAM-4 transmitter linearity (RLM).

FIR / Pre-emphasis tab

Specify the length of the TX FIR and the location of the main cursor tap. This setting is only valid for the Custom transmitter type.

Figure 24. Transmitter Options: Transmitter FIR, Pre-emphasis, and De-emphasis Configuration

TX Analysis

Figure 25. Transmitter Analysis Configuration

PLL tab

Use this panel to set the custom PLL divider ratio. This panel provides an alternative to Advanced Link Analyzer’s automatic divider ratio configuration. For example, Intel transmitters provide three programmable dividers: L, M, and N. You can set the divider ratio manually. Refer to Intel transceiver documentation for PLL setting recommendations.

Figure 26. Transmitter Options: PLL Configuration

Options tab and Die Model tab

Reserved. These tabs are blank.

Use the following guidelines for characterization data access:

• When Stratix^® V GX, Stratix^® V GT, Arria^® V GZ and Intel^® Arria^® 10 GX/SX/GT, or Intel^® Stratix^® 10 L-Tile/H-Tile/E-Tile is selected, the Characterization Data Access button appears and you can include the transmitter jitter parameters in the simulation.
• Characterization Data Access covers PVT variations. You can select appropriate process, voltage, and temperature conditions that best match the desired operation conditions.
• After clicking the button, Characterization Data Access configures Advanced Link Analyzer to use the characterization data by:
  • Selecting Jitter/Noise Component Mode for characterization data entries
  • Setting the Jitter/Noise Data Lock check box
  • Importing device characterization data based on the jitter unit selection
    • RJ—Unit selection can be UI (RMS) or ps (RMS)
    • Other Jitter—Unit selection can be UI (pk-pk), UI (pk), ps (pk-pk), or ps (pk)

These actions inform the Advanced Link Analyzer simulation engine to use the characterization data from the database.

Figure 27. Characterization Data Access: PVT Conditions and Jitter/Noise Lock Check Box

Figure 28. Characterization Data Access Usage and Message

Click the Transmitter Pulse Fitting button to perform transmitter FIR fitting and analysis. The fitting and analysis are implemented according to IEEE 802.3bj and OIF CEI 56G standards. The transmitter fitting results provide an indication of effective emphasis level that was observed at transmitter output.

Transmitter Pulse Fitting can be customized to suite specific transmitter configurations. Please see "TX Analysis" section of "Transmitter Options" for details.

Click the Transmitter SNDR button to perform transmitter SNDR (Signal to Distortion and Noise Ratio) analysis. The calculation and analysis are implemented according to IEEE 802.3bj and OIF CEI 56G standards. The result provides an indication of transmitter output quality.

Advanced Link Analyzer provides extensive jitter and noise modeling and configuration capabilities. The receiver intrinsic jitter and noise types are categorized in the following table. You can configure each jitter and noise type by clicking Receiver Jitter Options, which leads to the Receiver Jitter/Noise Configuration window.

Advanced Link Analyzer uses a flat jitter/noise structure that assumes no overlapping among the jitter and noise components. Avoid double counting when inputting or importing jitter/noise figures. In the following figure, DJ contains DCD, ISI, PJ, and BUJ. This implies that when you specify DCD and BUJ, the DJ should not be used or the DJ figure should not contain any DCD and BUJ components.

Figure 35.  Advanced Link Analyzer Receiver Jitter/Noise Configuration Window

Use the following guidelines for characterization data access:

• When Stratix^® V GX, Stratix^® V GT, Arria^® V GZ or Intel^® Arria^® 10 GX/SX/GT is selected, the Characterization Data Access button appears and you can include the receiver jitter parameters in the simulation.
• Characterization Data Access covers PVT variations. You can select the appropriate process, voltage, and temperature conditions that best match the desired operation conditions.
• After clicking Characterization Data Access, Advanced Link Analyzer is configured to use the characterization data by:
  • Setting Jitter/Noise Component Mode for characterization data entries
  • Setting the Jitter/Noise Data Lock check box
  • Importing device characterization data based on the jitter unit selection
    • RJ—Unit selection can be UI (RMS) or ps (RMS)
    • Other Jitter—Unit selection can be UI (pk-pk), UI (pk), ps (pk-pk), or ps (pk)

The Advanced Link Analyzer simulation engine uses this characterization data from the database.

Figure 36. Characterization Data Access: PVT Conditions and Jitter/Noise Lock Check Box

Figure 37. Characterization Data Access Usage and Message

A message box appears when the Characterization Data Access button is clicked.

Figure 38.  Intel Receiver Jitter Data Usage Message Window

Receiver options provide further configuration and setting options for receivers.

• Termination tab—This section specifies receiver impedance.
  Figure 39. Receiver Termination Configuration

  

  For selected Intel devices, use the RX Impedance pull-down menu to select a termination configuration. You can also customize the termination configuration by selecting the Custom option. When the Custom RX Impedance method is chosen, the termination can be configured as follows:

  • Ideal RX termination—The receiver is ideal with a 50 ohms (single-ended) termination.
  • Non-ideal RX termination—Select one of the following options:
    • R—Receiver impedance is modeled as a resistance R ohms (single-ended).
    • R//C1—Receiver impedance is modeled as an RC network with a parallel resistor (in ohms) and a capacitance (in pF).
    • File Input (Frequency Real Imaginary)—Receiver impedance is modeled by a frequency-dependent complex impedance table described in the input file.

  For an Intel receiver, the default termination configurations are automatically selected and specified.

• Equalization tab—For Intel^® Arria^® 10 GX/SX/GT, Stratix^® V GX, and Arria^® V GZ devices, the DFE model is embedded in the Advanced Link Analyzer with limited configurability. For Custom and PCI Express^® 8GT/16GT receivers, the DFE configuration options are provided.
  Figure 40.  Advanced Link Analyzer Receiver Options: Equalization Configuration

  

  EQ Options tab:

  • DFE Tap Length—For supported Intel devices, you can manually reduce the DFE tap length. If the selected DFE tap length is larger than the device's original DFE tap length, the change is not applied in the simulation. For Intel^® Arria^® 10 devices, manually setting the DFE tap length disables floating DFE tap capability in the simulation.

  Custom RX FFE/DFE tab:

  • Algorithm—The DFE is adapted using the LMS algorithm and its variations.
  • DFE Tap Length—Number of DFE taps. This option is only available for Custom and PCI Express^® 8GT receivers.
  • FFE Tap Length— Number of FFE (Feed Forward Equalizer) taps. This option is only available for Custom and PCI Express 8GT/16GT receivers.
  • Step Size—Step size of the LMS algorithm. This parameter controls the speed of the LMS adaptation. The default value is 0.01.
  • Summation Node Model—Advanced Link Analyzer supports two generic/custom summation node modeling methods:
    • 3dB Bandwidth (RC filter)—Use a first-order RC filter to perform low-pass filtering of the DFE adjustment.
    • S-parameter—Use your S-parameter file to specify a pulse-shaping filter. Only the differential insertion loss (S_dd21) is applied in the pulse shaping.
  • Reference Tap— The location of main cursor tap in the FFE.
  • Override generic/standard device setting: For standard devices, for example, PCI-Express 8GT and 16GT, the DFE tap length, coefficient range, and summation node bandwidth are pre-configured within the device model. Select or check this option if you want to simulate these devices with custom settings.

• Custom RX CTLE tab:
  • CTLE Configuration & Gain Control tab:
    • VGA Configuration
      • Target Level: The target voltage level of VGA output
      • Max VGA Gain (linear scale): The maximum VGA gain in linear scale
      • Gain Granularity: When VGA is in auto mode, the step size of VGA gain
  Note: Custom RX's VGA has flat gain across frequencies.
• CTLE Kernel Options:

  • CTLE Kernel Type: Choices are Default and COM. Default method uses PCI-Express 8GT reference CTLE model which scales with data rate relative to 8 Gbps, i.e. PCI-Express 8GT's data rate. COM method uses IEEE 802.3cd COM reference CTLE model. Advanced Link Analyzer allow users to modify the frequency divider of pole and zero locations and frequency scaling.

Figure 41.  Advanced Link Analyzer Receiver Options: CTLE Configuration & Gain Control, Kernel Options

• Misc tab—Reserved. This tab is blank.

IBIS-AMI Receiver—Advanced Link Analyzer supports IBIS-AMI receiver modeling. When you select the IBIS-AMI receiver, the IBIS-AMI Receiver page appears. The IBIS-AMI page includes three tabs for additional settings of the IBIS-AMI model.

Figure 42. Receiver IBIS-AMI Model IBIS Configuration Page

• Package—Package models are required in all IBIS models. Advanced Link Analyzer includes the IBIS package model in the simulation by default. You can choose other package models by changing the Package selection to Custom and specifying the external package model (Channel type Package) as a channel component.
  Note: Make sure there is only one package model for the IBIS-AMI receiver. Use either package type IBIS-AMI or package type Custom with external package model in the schematic. Simulation errors may occur if you have more than one receiver package model in the link.
• IBIS Files—Click the file open button next to the IBIS File text box to select an IBIS model file. Advanced Link Analyzer scans through the IBIS file and allocates all available receiver components and models. If Advanced Link Analyzer encounters any of the following issues in opening or interpreting the IBIS-AMI model, a warning message is shown.
  • No receiver component or model can be located.
  • The DLL for the computer platform cannot be located. Note that the IBIS-AMI model is platform dependent. For example, a 32-bit DLL is required to simulate in a 32-bit link simulator. A 64-bit DLL is required to simulate in a 64-bit simulator. A 32-bit DLL cannot simulate with a 64-bit DLL in the same simulation.
  • The DLL occupies so much memory that Advanced Link Analyzer was not able to load it. However, Advanced Link Analyzer might be able to run the simulation with such a DLL because of memory allocation differences in the Advanced Link Analyzer GUI and the simulation engine.
• Component—Select an IBIS component from the IBIS model.

IBIS tab

• Model—Select a device model within a component of an IBIS model.
• Model Selector—Select a model from the model selector list.
• Corner—Select the corner type of a device model. The choices are Typ, Min, and Max.
• AMI File—Shows the AMI file specified in the IBIS model.
  Note: Advanced Link Analyzer currently only supports device models with AMI modeling components.
• DLL File—Shows the DLL file specified in the IBIS model.
• Check [R series] during model load time— Check this option if you want Advanced Link Analyzer to scan [R series] settings when the IBIS model is loaded which can take extra loading time especially when the IBIS model is large. When you experience long loading time when reading an IBIS-AMI model, you can optionally disable this feature. Use of R series is not common in most IBIS-AMI models. Please check the IBIS-AMI model description or consult model vendor for usage of R series.
• Use External Termination—A checked box indicates that an external termination is used in the simulation. The external termination (single-ended) is specified in the text box on the right. The default setting is not using external termination and the default external termination (if applicable) is 50 ohms (single-ended).
  Note: Advanced Link Analyzer automatically enables the external termination option when it detects that the IBIS-AMI model is using [series pin mapping] with [R series] configuration.
• Automatic Jitter/Noise Update—A checked box allows automatic jitter/noise updates from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later). Automatic Jitter/Noise Update is disabled by default.
  Note: If you experience unexpected long delay when loading an IBIS-AMI model, you can disable the Automatic Jitter/Noise Update by unchecking it. It was seen that certain IBIS-AMI models perform computation-intensive functions (such as equalization adaptation) during the jitter/noise retrieval. You can still retrieve jitter/noise numbers by manually clicking the Manual Jitter/Noise Update button.
• Manual Jitter/Noise Update—When the Automatic Jitter/Noise Update option is disabled, turning on this option allows you to manually update the jitter/noise figures from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later).
• DLL_Path—Specify a folder or path name where the supporting files of an IBIS-AMI model are stored. Refer to the IBIS standards for details.
• CDR Type—Three options are available:
  • IBIS-AMI—If the receiver IBIS-AMI model contains a CDR model, Advanced Link Analyzer uses the IBIS-AMI model's clock tick output to analyze the link performance. If there is no embedded CDR model in the IBIS-AMI model, the ideal clock is used to access the link's performance.
  • Ideal Clock—Advanced Link Analyzer always uses the ideal click to access link performance.
  • Bang-Bang—Advanced Link Analyzer uses its internal bang-bang CDR model to access the link performance. If the embedded CDR model is present in the IBIS-AMI model, it is neglected.
• Bandwidth—When the Bang-Bang CDR is selected, the CDR loop bandwidth can be set to Low, Medium, or High. (This is the same as the generic custom receiver's CDR settings.)

AMI tab

The AMI tab shows the following AMI configuration parameters.

Figure 43. Receiver IBIS-AMI Model AMI Configuration Tab

• Model Name—IBIS-AMI model name
• Reserved Parameters:
  • The IBIS-AMI reserved parameters are shown. The reserved parameters are meant for the Advanced Link Analyzer simulation configuration.
  • Advanced Link Analyzer supports the IBIS-AMI Rev. 5.0 and 6.0 jitter format. IBIS-AMI receiver jitter parameters (Rx_Clock_PDF) are extracted and automatically set in the Receiver's Jitter/Noise window with the interpretation shown in the following tables:

• Model Specific Parameters— This section lists all the model specific parameters that the IBIS-AMI model provides. You can use their selections or specify parameters for the simulation.

Figure 44. Receiver IBIS-AMI Parameter Type Designation for Link Optimization

Advanced Link Analyzer 17.0 supports link optimization with IBIS-AMI receiver models. On the left are the model specific parameters. For each parameter that Advanced Link Analyzer determines is tunable, a pull-down menu allows you to assign the receiver parameters. The types of receiver parameters are as follows:

• No Sweep—No sweeping or link optimization is performed
• Sweep—Advanced Link Analyzer sweeps or performs link optimization using available options provided by the IBIS-AMI model. This parameter is not supported in the Advanced Link Analyzer 17.0 release.
• CTLE Adapt Controller—This receiver parameter enables or disables automatic adaptation of the CTLE or analog equalizer. This sweep parameter is used when the link optimization method is CTLE=>FIR=>DFE, CTLE=>FIR=>CTLE=>DFE, CTLE=>FIR+DFE, or CTLE=>FIR+DFE=>CTLE+DFE.
• DFE Adapt Controller—This receiver parameter enables or disables automatic adaptation of the DFE. This sweep parameter is used when the link optimization method is CTLE=>FIR=>DFE, CTLE=>FIR=>CTLE=>DFE, CTLE=>FIR+DFE, or CTLE=>FIR+DFE=>CTLE+DFE.
• Sweep as CTLE—This receiver parameter is swept as the CTLE or analog equalizer with all available options.
• Sweep as CTLE AC Gain—This receiver parameter is swept as the CTLE’s AC gain controller. This sweep parameter is generally used in conjunction with the Sweep as CTLE DC Gain parameter.
• Sweep as CTLE DC Gain—This receiver parameter is swept as the CTLE’s DC gain controller. This sweep parameter is generally used in conjunction with the Sweep as CTLE AC Gain parameter.

With the information provided in the IBIS-AMI model and parameter type selections, Advanced Link Analyzer determines the link optimization approach and conducts the simulation. If you cannot determine the nature of the model specific parameters, consult with the IBIS-AMI vendors. An example of transmitter IBIS-AMI parameter type designations is shown in the above figure.

Status tab

The Status tab shows the parameters that are fed into the IBIS-AMI model for simulations.

Figure 45. Receiver IBIS-AMI Model Status Tab

The channel connects the transmitter and the receiver. It contains transmission media such as PCB traces, connectors, backplanes, cables, and device packages. A channel is a combination of numerous components described by channel models. Advanced Link Analyzer’s channel processing engine first interprets the channel models and then connects and cascades channels to construct one channel component for link simulations.

Advanced Link Analyzer supports single-ended Touchstone 1.0 and selected types of Touchstone 2.0 S-parameter channel models. It can access and process n-port S-parameters and extract transmission responses and crosstalk responses. After successfully extracting the channel characteristics, it performs differential-pair channel cascading for subsequent link simulation.

Advanced Link Analyzer supports Channel Designer components such as stripline, microstrip, coax, RLGC, ideal transmission line, coupled stripline, and coupled microstrip. When you select a Channel Designer component, you can choose different configurations in the associated channel designer GUI. PCB stackup is also supported, in which you can enter PCB substrate and stackup information. Supported channel models, which include stripline, microstrip, coupled stripline, and coupled microstrip, can utilize any available PCB stackup dataset in the design. Multiple PCB stackup dataset is supported in Advanced Link Analyzer. Refer to the Advanced Link Analyzer Channel Designer section for detailed information about the usage of channel designer components.

Advanced Link Analyzer implements the Link Designer, which allows you to graphically construct the communication link. In the following figure, the Channel List shows a channel construction example with one transmission channel (such as a loss channel or a victim channel) and two crosstalk channels.

Figure 46.  Advanced Link Analyzer Channel Setting with Link Design and Channel List

An S-parameter channel component such as a connector, cable, or backplane can be described by the following parameters or information:

• ID—Sequence or location of the channel component. The top channel is connected to the transmitter and the bottom channel is connected to the receiver.
  Note: Embedded package models (such as Package models for Intel devices and PCI Express^® Gen3 devices) are not shown in the channel list or Link Designer.
• Channel Name—An S-parameter file that describes the channel component. The S-parameter can be 4-port, 8-port, 12-port, 16-port, and so forth. When your cursor hovers on a channel list, a tooltip shows the S-parameter file location. This information is useful if you share Advanced Link Analyzer configuration files.
• Type—Specify the type of channel characteristics to be used in the link simulation. The type of channel characteristics can be insertion loss (Loss), far-end crosstalk (FEXT), or near-end crosstalk (NEXT). You can change the channel (or channel type) by selecting the channel from the Link Designer using the Channel Wizard.

• Port Configuration—Depending on the S-parameter measurement condition, the port configuration can be one of the following types. Use the Channel Wizard to change the port configuration of an S-parameter.

Figure 47. S-parameter with Port Configuration – Type 1

Figure 48. S-parameter with Port Configuration – Type 2

Figure 49. S-parameter with Port Configuration – Type 3

Figure 50. S-parameter with Custom Port Configuration

If the S-parameter file is not Type 1, Type 2, or Type 3, you can use the Custom option in the Channel Wizard’s Port Config pull-down menu, as shown in the following figure. When a Custom port configuration is selected in the Channel Wizard, a text box named Port Map appears below the port configuration figure (one of the configurations in the above figure). Enter the port numbers in the sequence [P1, P2, P3, …Pn], where n is the number of ports, as illustrated in the figure above that matches the selected S-parameter model. In the figure below, the Port Map sequence 1 3 2 4 corresponds to a 4-port (n=4) S-parameter model with port configuration Type 2 where P1=1, P3=Pn/2+1=2, P2=3, and P4=Pn/2+2=4. When a custom port configuration is assigned to an S-parameter model, it is displayed as port configuration Type 4 in the channel table.

Figure 51. Custom Port Configuration in Channel Wizard

• Lane—This field lists the channel lane ID number. For channel lane S-parameters that are 8-port and above, a channel lane must be chosen for link simulations. For example, the above figures show a 12-port 3-lane S-parameter. After loading the channel file, Advanced Link Analyzer assigns the center lane as the default simulating channel (or victim channel for crosstalk simulations). Use the Channel Wizard to change the lane ID. For 2-port or 4-port S-parameter models, the lane ID is ignored.
• Rev—This field indicates whether the channel signal flow direction is to be reversed. This is generally used for the device package model when you want to make sure transmitter and receiver devices are connected to the die side of the package S-parameter model. Refer to the S-parameter comment section for S-parameter signal flow configuration.
• AC Cap—This field records AC coupling capacitor value in nF (nano-Farad, 10^-9 F).
• Shunt Cap—This field records shunt capacitance value in pF (pico-Farad, 10^-12 F).

A crosstalk aggressor has the following parameters:

• Source—Each crosstalk aggressor can be of Inline, Transmitter, or Aggressor type.
  • With an inline aggressor, the input to the crosstalk channel is the input waveform at the last transmission/victim channel segment.
  • With a transmitter aggressor, the aggressor waveform is the same as the victim transmitter with the above aggressor effects, such as frequency offset, delay, and relative amplitude, applied.
  • If the aggressor type is “Aggressor X”, the aggressor is modeled by the Xth aggressor type as shown in the Aggressor Transmitter tab (refer to the Crosstalk Aggressor Transmitter Setting section).

  The following figure shows the three crosstalk aggressor transmitter types. Inline aggressor means the signal feeding into the crosstalk channel comes from the immediate victim channel in parallel with the XTLK channel (as shown in the red dotted arrow line). TX Aggressor means that, regardless of where the XTLK channel is located, this XTLK always uses the VICTIM TX output as its signal source (shown in the green dotted line). The Individual Aggressor TX is similar to the Victim TX Aggressor, but it can be generated separately.

  Figure 52. Crosstalk Aggressor Types

  

• Location—For multiple channel/lane S-parameters simulating crosstalk effects, you must specify the aggressor location. For example, the above figures show four possible crosstalk configurations from a 12-port S-parameter model. Use the Aggressor Location menu in the Channel Wizard to change the aggressor location. The Aggressor ID field is ignored for a victim channel (Loss type).
  Note: The Aggressor ID index excludes victim lanes. For example, in a 12-port S-parameter, there are three lanes. If the middle lane (Lane ID 2) is a victim lane, the two aggressor channels have Aggressor ID 1 and 2, not 1 and 3.
• Relative Amplitude—Each crosstalk aggressor can have different aggressor amplitude relative to its original amplitude. The default value for aggressor is 1.0, which indicates the aggressor has its original amplitude. The Aggressor ID field is ignored for a victim channel (Loss type).
• Delay—Each crosstalk aggressor can have individual delay or time offset. The delay is input in picoseconds (ps, 10^-12 second). Positive values in aggressor delay indicate the aggressor is lagging behind the victim waveform. Negative values indicate the aggressor is ahead of the victim signal waveform. The Aggressor ID field is ignored for a victim channel (Loss type).
• Frequency Offset—Each crosstalk aggressor can run on an offset frequency compared to the victim channel’s transmitter. The frequency offset is given in negative ppm (parts per million). The maximum frequency is –950,000 ppm.

The Channel Viewer button is a convenient way of observing channel characteristics in the current channel list. Click Channel Viewer to transfer the channels to a new Channel Viewer window. You can then observe various parts of channel characteristics in either frequency- or time-domain. Use the Advanced Link Analyzer Channel Viewer to view cascaded channel characteristics if multiple channel components are used in the victim signal path. The following figure illustrates the Channel Viewer plot of the channel construct shown in Figure 53.

Figure 53.  Advanced Link Analyzer Channel Viewer Example

Refer to the Tutorial: PCI Express^® 8GT chapter for step-by-step channel setup instructions.

Automatic S-parameter Configuration Check (ASCC)

Advanced Link Analyzer uses a proprietary Automatic S-parameter Configuration Checker (ASCC) to help you set and connect the S-parameter in the channel chain. With ASCC, Advanced Link Analyzer inspects the S-parameter model and determines the port number and port configuration. ASCC also selects the middle lane as the victim channel (insertion loss channel) and sets the Lane and Aggressor pull-down menus for user configuration. Channel configuration information is saved individually for each channel. Therefore, S-parameters with different port numbers, port configurations, or both can be mixed and cascaded in Advanced Link Analyzer.

Advanced Link Analyzer provides a convenient way to set up batch channel simulations. Batch channel simulation generation can be accomplished when the following conditions are met:

• A complete link is graphically configured. This requires that:
  • The link contains a transmitter, receiver, and at least one transmission channel.
  • In the Link Designer, the connection lines from the transmitter to the receiver are bold black lines.
• The link configuration is complete and ready for simulating with a variety of channels. Link configurations such as data rate, test pattern, BER target, reference clock setting, transmitter and receiver operation mode, and link optimization method are set and ready for simulations.

When these conditions are met, perform the following steps to set up a batch simulation. This example creates a batch simulation using the same transmitter, receiver, and other link settings while evaluating a group of channels at the place of the channel 20in_4mils.s4p, as shown in the following figure.

Figure 54. Example Link Configuration for Creating Batch Channel Simulations

1. Choose a connected channel from the Link Designer work space. Right-click on the channel to bring up a context menu.
   Figure 55. Batch Channel Simulation Configuration Selection

   

   The Advanced Link Analyzer Batch Simulation Channel Selection window appears.

   Figure 56. Batch Simulation Channel Selection Window

   
2. Click Add Channel to select channel files. A file browser helps you select the channel files you want. You can select multiple channels within the file browser. You can also click Add Channel repeatedly to add more channels. The added channel is listed in the Channel list box with channel type, port configuration, lane (if the channel is 8-port or more), and aggressor identification (if the channel is a crosstalk channel within a multiple-lane S-parameter).
   • Advanced Link Analyzer uses the Automatic S-parameter Configuration Check (ASCC) algorithm to automatically detect S-parameter models’ port configuration and designate default transmission lane.
   • To observe a channel’s characteristics or change a channel’s configuration, you can:
     • Select the channel and then click View using Channel Wizard. The Advanced Link Analyzer Channel Wizard helps you configure the channel.
     • To see all channels' characteristics, click View All using Channel Viewer to start the Channel Viewer (refer to the Advanced Link Analyzer Channel Viewer Module sections for details).
     • Use the pull-down menus or buttons below the channel list boxes to change individual channel configuration.
   • Optionally, you can edit the batch simulation file name header in the pull-down menu or the text box below the channel list boxes. By default, Advanced Link Analyzer uses the Date-Time string as the file name header. You can also type the desired header name in this box.
   Figure 57. Example of Batch Channel Selections

   
3. When channel selection is complete, click Generate Simulation Configuration to generate Advanced Link Analyzer simulation configuration files with the selected channels.
   Note: In the current implementation of Advanced Link Analyzer, all simulation configuration files generated from step 3 are saved in the Advanced Link Analyzer installation directory.

After completing these steps, a series of Advanced Link Analyzer simulation configuration files are generated. For example, by using the Date-Time header option, four sets of Advanced Link Analyzer simulation configuration files are generated.

Figure 58. Batch Generated Advanced Link Analyzer Simulation Configuration Files

Launch Advanced Link Analyzer Batch Simulation Controller to run the generated link simulations (refer to the Advanced Link Analyzer Batch Simulation Controller section for details). The following figure shows the generated batch channel simulations added in the Advanced Link Analyzer Batch Simulation Controller and ready for batch simulations.

Figure 59. Added Generated Batch Channel Simulation Configuration in Advanced Link Analyzer Batch Simulation Controller

Aggressor transmitter configurations allow you to configure crosstalk aggressors individually with different transmitter types, pre-emphasis settings, amplitudes, data rates, and so forth. The following figure shows a 2-aggressor link with three different aggressor transmitters.

Figure 60. Aggressor Transmitter with Two Individual Aggressor Transmitters

Follow the steps described in the previous section to set up a link with crosstalk channels. In the Channel Wizard window, in the Signal Source menu of the Crosstalk Aggressor panel, select the Inline, Transmitter, or one of the eight available Aggressor types.

Figure 61. Setting Up the Crosstalk Aggressor for a Crosstalk Channel

Advanced Link Analyzer supports up to eight individual crosstalk aggressor transmitters. However, a crosstalk aggressor transmitter can be shared among crosstalk channels. By combining the aggressor relative amplitude, frequency offset, and delay setting, Advanced Link Analyzer can generate a variety of crosstalk aggressor signal sources.

After completing the configuration in the Channel Wizard, go to the Advanced Link Analyzer GUI and select the Aggressor Transmitter tab.

Figure 62. Aggressor Transmitter Tab

Within the Aggressor Transmitter tab, there are eight aggressor types associated with the aggressor types in the Channel Wizard’s Signal Source menu. Each aggressor can be configured as follows:

• Data Rate—Data rate of the selected aggressor transmitter in Gbps.
• Test Pattern—Aggressor transmitter’s test pattern. Advanced Link Analyzer supports the following test patterns:
  • Same as victim TX
  • PRBS-7, PRBS-9, PRBS-11, PRBS-15, PRBS-23, PRBS-31
• VOD—Differential output voltage of the aggressor transmitter in volts.
• Transmitter Type—Aggressor transmitter can be one of the following transmitter types:
  • Same as victim TX
  • Stratix^® V GX
  • Arria^® V GZ
  • Stratix^® V GT
  • Custom
• Pre-emphasis / FIR—Pre-emphasis or FIR setting of the aggressor transmitter. You can set it to be the same as the victim TX or you can type in the setting.
  Note:

  • In manual pre-emphasis/FIR input mode, the pre-emphasis/FIR setting must be in the same format as used in the Transmitter tab. This does not mean that the aggressor transmitter must be the same type as the victim transmitter, but that the pre-emphasis setting format must be in the format as if it is a victim transmitter. For example, if the aggressor transmitter type is Intel Stratix^® V GX, the pre-emphasis/FIR setting is in a list of TX-FIR levels such as -1, 0, 20, 3, where -1 is the pre-tap 1 value, 20 is the post-tap 1 value, and 3 is the post-tap 2 value. The main tap can be any value, because Advanced Link Analyzer determines the main tap's value based on the values of other FIR taps.
  • If the user input TX pre-emphasis /FIR is invalid for the selected transmitter type, pre-emphasis/FIR is disabled.

If the transmitter type is Custom, the following parameters are also used:

• Edge Rate—Advanced Link Analyzer generates a transmitter output waveform with the specified edge rate. Edge rate is in the format of ps/Volt.
• TX-FIR Length—Length of TX-FIR for custom aggressor transmitter.
• Main-Tap Location—Location of main tap of aggressor transmitter.

The example shown in Figure 62 indicates an aggressor transmitter, which is a custom transmitter type, running at 6.5 Gbps with the PRBS-23 test pattern and a VOD of 1.2 V. The TX FIR coefficients are [-0.1, 0.8, -0.1] with a TX-FIR length of 3 and the main tap is at 2nd tap. According to the link configuration shown in Figure 60, this aggressor transmitter is associated with Crosstalk (FEXT) channel ID = 2.

Advanced Link Analyzer supports repeater and retimer simulations. A repeater is a device that can be placed within a link where it can provide additional equalization capabilities. It is typically constructed with two major stages: an equalizer stage and a driver stage. The equalizer stage usually contains continuous-time linear equalizer (CTLE) circuitry that compensates the channel before and, possibly, after the repeater depending on the design of the driver stage. The driver stage usually amplifies the equalized signal and may contain an emphasis function so that it may compensate the channel after the repeater. Depending on the driver stage design, a repeater can be a linear repeater, where the driver maintains linear characteristics within the majority of the signal amplitude range, or a non-linear repeater, where a limiting amplifier between the equalizer stage and driver stage can sharpen the waveform’s transition time. Both linear and non-linear repeater simulations are supported in Advanced Link Analyzer.

Similar to a repeater, a retimer is a device that can be placed within a link where it provides additional equalization and jitter/noise cleaning capabilities. A retimer is constructed with two major stages: an equalizer stage, which is equipped with the clock data recovery (CDR) circuitry, and a driver stage. The equalizer with a CDR stage first compensates the channel effects for the link before the retimer, and then the CDR recovers the bit time and data for its output. During this process, it not only compensates for channel effects, but also resets or reduces jitter and noises that may come from the reference clock, transmitter, or other channel components. Also, with the presence of a CDR, more advanced equalization schemes, such as decision feedback equalizer (DFE), can be incorporated in a retimer. The driver stage is similar to that of a repeater. A retimer is non-linear by nature as both the bit time and amplitude are re-generated.

A repeater/retimer IBIS-AMI model consists of two internal models: an IBIS-AMI receiver model, i.e., the equalizer/CDR stage, and an IBIS-AMI transmitter model, i.e., the driver stage. In Advanced Link Analyzer, you explicitly place a pair of a receiver link component (Repeater/Retimer RX) plus a transmitter link component (Repeater/Retimer TX) in the schematic editor for a repeater/retimer model. Figure 63 shows the repeater/retimer GUI entries and Figure 64 shows a typical repeater/retimer link configuration. Note that while Advanced Link Analyzer does enforce or limit how the link components are connected within a link, a user has to make sure the repeater/retimer RX and repeater/retimer TX model are connected in the correct signal flow order and no other link or channel component is placed between the repeater/retimer RX and TX models.

Note that the repeater and retimer IBIS-AMI model may be provided in various formats. The equalizer/CDR stage model, which is with IBIS receiver component type, and the driver stage, which is with IBIS transmitter component type, may belong to the same IBIS model or may be provided in two separate IBIS models. Please consult the vendors for the usage.

Figure 63. Link component GUI entries

Figure 64. Typical link topology with a repeater/retimer

Advanced Link Analyzer supports noise source generation and simulation in the link level. While most high-speed serial links’ noise are generated by the transmitter and receivers (and their supporting networks and components like power supplies, reference clock, and crosstalk), many industrial standards use external noise sources, which are applied on pre-defined test points within a link, for channel or device compliance tests. Notable industrial standards such as PCISIG and IEEE 802.3 use such external noise injection schemes. With the support of noise source generation and simulation capabilities, we can accurately model such compliance test conditions in Advanced Link Analyzer.

Figure 71. Noise source GUI entry

Figure 71 shows the GUI entry for noise source generator. Turning Noise Source w/ Channel on makes the Advanced Link Analyzer Channel Wizard appear (see Figure 72). By default, an ideal channel (no loss with ideal impedance) is chosen. If there is a channel between the noise generator and the test point, you can click the Change Channel button and select a different channel file. Note that the Signal Source pull-down menu is set to NoiseSouce1 by default. A user can also configure or modify the noise source’s relative amplitude, delay, or frequency offset in the same way as setting a crosstalk aggressor. After click OK button, the noise source can be placed in the schematic design space. A typical link topology with a noise source is shown in Figure 73.

Figure 72. Noise source channel configuration

Figure 73. Typical link topology with a noise source

Figure 74. Noise source configuration

Use the System Option windows to set the simulation setting.

• System tab
  Figure 75.  Advanced Link Analyzer System Options Window: System Tab

  
  • Output Directory—Specify an output directory for the simulation results according to the Output Directory Mode setting.
  • Output Directory Mode
    • Sync with .jne file location—Automatically sets the output directory to the directory location when .jne/.jneschm is created by a user with the Save or Save as command.
    • As specified in the Output Directory—Sets the output directory to the location specified in the Output Directory text box.
  • Default Output Image Format—Set the default output image format to PNG, JPG, or GIF.
  • Generate Plots Measured with Ideal Clock
    • Yes—Always generate plots that are measured with the ideal clock.
    • Do not plot when RX CDR is enabled—Skip ideal clock-based plots in RX outputs. (default value)
    • Do not plot when TX scope is enabled—Skip ideal clock-based plots in TX outputs.
    • Do not plot when the TX scope, RX CDR, or both are enabled—Skip ideal clock-based plots when the TX scope, RX CDR, or both are enabled.

• • Jitter Sensing Sensitivity—Select the sensitivity of jitter detection when Advanced Link Analyzer performs jitter analysis (Beta feature in the 17.0 release). The selections are: Default, Ideal, Low, Medium, and High. The Default setting is equivalent to the Ideal setting.
  • Link Optimization Option— The choices are Accuracy or Speed. The default is Accuracy. By selecting Speed, the link optimization process runs faster at the cost of possibly less optimal solutions.

• Simulation tab
  Figure 76. System Options Window: Simulation Tab

  
  • Default Eye Diagram Plot Length—This parameter controls the waveform length used to construct the eye diagram when the Build Eye Diagram w/ Whole Waveform option is disabled. You can increase the length as long as the length is less than the simulation length. The default value is 4096 bits.
  • Build Eye Diagram w/ Whole Waveform—If Enable is selected, Advanced Link Analyzer uses the whole simulated waveform to build the eye diagrams. If the simulation length is large, this takes more time. The default setting is Enable.
  • Channel Generation Max Frequency—Sets the default maximum frequency of the channel models generated in Advanced Link Analyzer. The default value is 35 GHz.
  • Channel Generation Frequency Step—Sets the default frequency step of the channel models generated in Advanced Link Analyzer. The default value is 10 MHz.
  • S-parameter Caching—If Enable is selected, the last read S-parameter file is cached in memory for faster access and processing. Doing this greatly improves GUI performance when reading a multiple-lane S-parameter file with large file size. You can disable this feature.

• Channel Model tab
  Figure 77. System Options Window: Channel Model Tab

  
  • S-Parameter Extrapolation Options
    • Extrapolation Usage Method—This menu selects the method used in the extrapolation S-parameter channel model.
      • Default—The S-parameter is extrapolated but capped at the final amplitude value.
      • Always Apply—The S-parameter is extrapolated without restriction.
    • Extrapolation Method—This menu selects the extrapolation method.
      • Default—Linear extrapolation.
      • IL Fitting Extrapolation—Extrapolation is done by insertion loss fitting.
  • Channel Integrity Options—Enable or disable channel integrity checking in Advanced Link Analyzer. The default setting is Enable. Choose Disable if Advanced Link Analyzer has issues opening or accessing certain S-parameter models.
  • S-parameter Causality Check Extrapolation Options
    • Extrapolation Usage Method—Same as the same name entry in the S-Parameter Extrapolation Options. This entry only applies during S-parameter causality checking.
    • Extrapolation Method—This menu selects the extrapolation method during S-parameter causality checking.
      • Default—Insertion loss fitting based extrapolation method.
      • Last Amplitude Value—Linear extrapolation is used, but the amplitude is capped by the last amplitude value.

• • S-parameter Touchstone Option—Touchstone 2.0 Support.
    • Enable—Enable Touchstone 2.0 support. (default value)
    • Disable—Disable Touchstone 2.0 support.
  • Integrity Enforcement— Select how the integrity, e.g. causality, enforcement is applied in the simulation.
    • Type 1: Enforce integrity on individual channel components
    • Type 2: Enforce integrity on overall channel after cascading
    • Type 3: Enforce integrity both on individual channel component and after channel cascading
    • Disable: Disable integrity enforcement. Default setting is Disable.

The Advanced Link Analyzer Channel Viewer provides a convenient way of observing and comparing channel characteristics. The following types of channel characteristics, which are represented by Touchstone S-parameter format, can be displayed in the Channel Viewer:

• Standard-mode / Single-ended S-parameter—for example, S₁₁, S₁₂, S₂₁
• Mixed-mode / Differential S-parameters—for example: S_dd11, S_dd21, S_cd21
• Frequency Domain Plots: Amplitude and propagation/group delay plots
• Time Domain Plots: Impulse responses and single-bit responses

Channel Viewer also provides channel compliance checks and channel analysis. Use these features to observe a channel's characteristics and its associated signal integrity matrices.

Figure 95. Start Advanced Link Analyzer Channel Viewer from Advanced Link Analyzer Controller Module

There are four ways to start Advanced Link Analyzer Channel Viewer:

• Double-click the adv_link_analyzer_channel_viewer.exe icon in Windows Explorer.
• Click Channel Viewer in the Advanced Link Analyzer Control Module to start a new Channel Viewer (refer to the previous figure).
• Click Channel Viewer in the Advanced Link Analyzer Control Module’s Channel tab (refer to the following figure). When you start Advanced Link Analyzer Channel Viewer from the Channel tab, the channel information from the link configuration is transferred to the Channel View and is ready for viewing.
• Select a channel in Advanced Link Analyzer Control Module’s Link Designer, right-click, and select View in Channel Viewer.

The following figure shows the Advanced Link Analyzer Channel Viewer user interface. The viewer has six panels that allow you to select and control the channel plot options.

Figure 96.  Advanced Link Analyzer Channel Viewer User Interface

The following figure shows the Channel Viewer GUI panel partitions.

Figure 97.  Advanced Link Analyzer Channel Viewer GUI Panel Partitions

This panel contains the Channel Viewer and Plot Selector. The Advanced Link Analyzer Channel Viewer shows the characteristics of the channels in the channel list with the plot options specified. Use the Channel Viewer to plot channels with different options and browse the plots. Use the Plot Selector to choose one of the existing plots.

The Channel Viewer provides the following GUI capabilities:

• Zoom In, Zoom Out, Pan, Data Select—Right-click on the Channel Plot panel to select one of these functions. To zoom in on the plot, select Zoom In and then click and drag a rectangle box to show the details of the plot. To zoom out, select Zoom Out. Up to ten previous scalings are saved, so you can restore older versions by clicking Zoom Out more than once. To pan over the plot, select Pan and then click and drag the plot.
• Data Cursor—Turn on Data Cursor to show the data cursor boxes. You can select and drag a data cursor box with the data values shown in the box. The data values are colored according to the data lines.
• Legends—Plot legends are shown when plots are generated. Use the Page-Up, Page-Down, Home, and End keys on the keyboard to move the legend box. You can also check or uncheck the Legends check box to show or hide the legend box.

This panel maintains the channels of interest. Channels can be either transferred from the Advanced Link Analyzer Control Module or added within the Channel Viewer. The channel list in the Channel Viewer is independent from the list in Advanced Link Analyzer Control Module. Therefore, you can add and delete channels in the Channel Viewer without affecting the lsimulation configuration in the Advanced Link Analyzer Control Module.

An S-parameter channel component, such as a connector, cable, or backplane, can be described by the following parameters or information as shown in the Channel List:

• ID—Sequence or location of the channel component.
• Channel Name—An S-parameter file that describes the channel component. The S-parameter file can be 4-port, 8-port, 12-port, 16-port, and so forth.
• Type—Specify the type of channel characteristics in the link simulation. The type of channel characteristics can be insertion loss (Loss), far-end crosstalk (FEXT), or near-end crosstalk (NEXT). Change the channel type by selecting the channel from the channel list and then selecting the appropriate channel type from the Type menu.
• Port Configuration (Port Cfg)—Depending on the S-parameter measurement condition, the port configuration can be one of the types shown in the following figures. You can change the port configuration of an S-parameter by using the menu below the Port Configuration list box.

Figure 98. S-parameter with Port Configuration—Type 1

Figure 99. S-parameter with Port Configuration—Type 2

Figure 100. S-parameter with Port Configuration—Type 3

Figure 101. S-parameter with Custom Port Configuration

• Lane ID (Lane)—For multiple channel/lane S-parameters (8-port and above) a channel/lane must be chosen for link simulations. For example, the above figures show a 12-port 3-lane S-parameter. After loading the channel file, Advanced Link Analyzer assigns the middle lane as the default simulating channel (or victim channel for crosstalk simulations). You can change the Lane ID by using the menu below the Lane ID list box. For 2-port or 4-port S-parameter models, the Lane ID is ignored.
• Aggressor ID (Agg ID)—For multiple channel/lane S-parameters simulating crosstalk effects, you must specify the aggressor location. For example, the above figures show four possible crosstalk configurations from a 12-port S-parameter model. Use the menu below the Aggressor ID list box to change the aggressor location. For Victim channel (Loss type), the Aggressor ID field is ignored.
  Note: The Aggressor ID is indexed in a way that excludes the victim lane. For example, in a 12-port S parameter, there are three lanes. The middle lane (Lane ID 2) is the victim lane. The two aggressor channels have Aggressor IDs 1 and 2, not 1 and 3.
• Relative Amplitude (Rel Amp)—You can manually adjust the amplitude of crosstalk (NEXT/FEXT) channel components. The amplitude adjustment is reflected in the channel plots and the channel compliance results. The amplitude adjustment is in a linear scale.

The Channel List Panel contains the following command buttons:

• Add Channel—Open a file browser and locate the required channel model files.
• Delete—Delete a channel or test point.
• Duplicate—Duplicate the selected channel component or test point in the channel list.
• Disable—Disable the selected channel component or test point.
• Enable—Enable the selected channel component or test point.
• Clear—Delete all channel components and test points.
• Load—Load channel list and channel viewer configuration.
• Save—Save current channel list and channel viewer configuration.
• Save as—Save current channel list and channel viewer configuration in a new configuration file .
• Move Up (/\)—Move the selected channel component or test point up toward the transmitter side.
• Move Down (\/)—Move the selected channel component or test point down toward the receiver side.

The Plot Option panel has the following sub-panels:

• S-parameter mode panel
• Plot configuration panel

Figure 102. S-parameter Mode Panel

• Mixed-Mode Selector Panel—This panel allows you to select and plot an S-parameter’s mixed-mode characteristics. The Advanced Link Analyzer Channel Viewer can convert standard-mode (that is, single-ended) frequency responses into its differential–pair format (mixed-mode) frequency responses. For high-speed serial links with differential signaling scheme, Intel recommends you observe channel characteristics and performance in mixed-mode.
• Standard-Mode Selector Panel—This panel allows you to select and plot an S-parameter’s standard-mode characteristics. An open 4-port single-ended S-parameter is supported in this plot mode.

The Channel Analysis and Compliance Module menu controls the channel characteristics plotting modes:

• Off—Channel Viewer plots channel characteristics as directed by user configuration. In the mode, you can plot frequency responses, impulse responses, and single bit responses. This is the default Channel Viewer plotting mode.
• Channel Analysis—Channel Viewer performs a sequence of operations to calculate and show channel performance in terms of ILD (Insertion Loss Deviation), RL (Return Loss), ICR (Insertion Loss to Crosstalk Ratio), and Crosstalk Noise calculations. This allows you to determine the wellness of the channels.

  Channel Analysis supports customizable compliance masks for IL, ILD, RL, ICN, and ICR. This feature can be used to perform custom channel compliance checks for proprietary links. When Custom is selected, you can enter channel compliance mask definition in each text box with the format: frequency (Hz) and amplitude (dB). You can also load a predefined custom channel compliance mask definition from a file.

• 10GBASE-KR Channel Compliance—Channel Viewer performs channel compliance checks per 10 Gbps Ethernet over backplane (IEEE 802.3ap, 10GBASE-KR) standards.
• OIF CEI-28G-SR 3.0 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-28G-SR 3.0 standards.
• OIF CEI-25G-LR 3.0 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-25G-LR standards.
• OIF CEI-28G-MR 3.1 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-28G-MR standards.
• COM 802.3 100GBASE-CR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-CR4 standards.
• COM 802.3 CAUI-4 C2C Channel Compliance Channel viewer performs channel compliance checks per IEEE 802.3 CAUI-4 C2C standards.
• COM 802.3 100GBASE-KP4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KP4 standards.
• COM 802.3 100GBASE-KR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KR4 standards.
• COM Analysis—Channel Viewer performs a sequence of operations to calculate and show channel performance based on COM (Channel Operating margin) methodology. Channel Viewer allows users to customize parameters that configure COM calculation.
• COM 802.3 CAUI-4 C2C Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 CAUI-4 C2C standards.
• COM 802.3 200GAUI-4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GAUI-4 standards.
• COM 802.3 400GAUI-8 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 400GAUI-8 standards.
• COM 802.3 200GAUI-4 C2M Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GAUI-4 C2M standards.
• COM 802.3 400GAUI-8 C2M Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 400GAUI-8 C2M standards.
• COM 802.3 200GBASE-CR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GBASE-CR4 standards.
• COM 802.3 100GBASE-CR2 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-CR2 standards.
• COM 802.3 50GBASE-CR Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 50GBASE-CR standards.
• COM 802.3 200GBASE-KR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GBASE-KR4 standards.
• COM 802.3 100GBASE-KR2 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KR2 standards.
• COM 802.3 50GBASE-KR Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 50GBASE-KR standards.
• COM OIF-CEI-56G-LR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-56G-LR standards.
• COM OIF-CEI-56G-MR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-56G-MR standards.

User-Directed Channel Plotting

Figure 103. Plot Configuration Panel (Frequency Response)

Figure 104. Plot Configuration Panel (Impulse Response, Single Bit Response, Step Response, and TDR)

This panel allows you to select and configure the channel plotting. The Advanced Link Analyzer Channel Viewer can plot channel characteristics in either frequency domain or time domain. Typical frequency domain amplitude and group delay plots are shown in the following figure.

Figure 105. Typical Frequency Domain Channel Characteristics Plots

The Advanced Link Analyzer Channel Viewer plots the channels’ amplitude and group delay frequency responses in a linear or logarithmic frequency scale. It also allows you to limit the plot frequency range. When multiple transmission channels (such as loss or victim) are in the Channel List, you can plot the cascaded channel response by turning on the Plot Combined Channel Response option in the Systems Options panel. An example of a combined channel response is shown in the following figure, in which a lossy backplane channel is cascaded with a 5” microstrip PCB trace.

Figure 106. Combined Channel Response Example

The Advanced Link Analyzer Channel Viewer can also plot channel responses in the time-domain. It can compute the impulse response (IR) and single-bit response (SBR) of a channel or a combined response of channels. When performing a time-domain plot, you must specify the maximum frequency and plot length of the time-domain response. The following figure shows examples of impulse response and single-bit response of a 5” microstrip PCB trace.

Figure 107. Impulse Response and Single-Bit Response Examples

Combined time-domain channel responses can also be done in the Advanced Link Analyzer Channel Viewer. The following figure shows examples of combined time-domain channel response of a lossy backplane channel and a 5” microstrip PCB trace.

Figure 108. Combined Time-Domain Channel Responses

By turning on the Remove Propagation Delay option, the Advanced Link Analyzer Channel Viewer can mathematically remove the delay of channels so that more direct comparison among channels can be seen. The following figure shows an example of “Remove Propagation Delay” channel response of the same channels used in the previous figure.

Figure 109. Time-Domain Channel Plots with "Remove Propagation Delay" Option

Modulation Type – Select the modulation type that the channels operate and are checked against.

Channel Analysis

The following figure shows the Channel Analysis GUI.

Figure 110. Channel Analysis User Interface

In the Channel Analysis Configuration panel, the following parameters can be configured to your link configuration or preferences:

• Max. Freq.—Maximum frequency where channel analysis is performed
• 20%-80% Tr/Tf—20%-80% rise/fall time of the input signal to the victim or transmission channel(s)
• Nom max IL at Nyquist—Nominal maximum insertion loss at Nyquist frequency. This parameter specifies the maximum allowed insertion loss at Nyquist frequency, which is defined as half of the maximum frequency specified above. This frequency is used to safe guard the correctness of the fitted insertion curves so that the results meet fundamental transmission line characteristics.
  Note: Please enter the nominal maximal IL value which approximates to the selected channel at the Nyquist frequency. This value does not need to be precise as the fitting algorithm usually have enough tolerance margins in computing the fitted curves. If the channel's insertion loss at Nyquist frequency is less than 15dB, please enter 15 for best performance. If multiple channel are selected for the channel analysis, please enter the insertion loss value of the most lossy channel.
• NEXT Amplitude—Near-end crosstalk aggressor signal amplitude
• FEXT Amplitude—Far-end crosstalk aggressor signal amplitude
• NEXT Tr/Tf—Near-end crosstalk aggressor 20%-80% rise/fall time
• FEXT Tr/Tf—Far-end crosstalk aggressor 20%-80% rise/fall time
• Crosstalk dB Factor—This parameter, Y, defines how dB is calculated where dB = Y*log10(amplitude)
• Modulation Type—Select the modulation type that the channels operate and are checked against. The supported modulation types are NRZ (default) and PAM4.
• Compliance Mask—Select the channel compliance mask for channel analysis. The Compliance Mask menu contains the following selections:
  • 10GBASE-KR—Use the 10GBASE-KR channel compliance mask.
  • OIF CEI-28G-SR 3.0—Use the OIF CEI-28G-SR channel compliance mask.
  • OIF CEI-25G-LR 3.0—Use the OIF CEI-25G-LR channel compliance mask.
  • Custom—Refer to Figure 110. Several text boxes for each channel compliance check item are shown. You can copy or manually input the mask definitions. The format for each mask definition data point is “Frequency (in Hz)", followed by "Amplitude (in dB)”. The number of data points is limited to the maximum text length allowed by the text box (the maximum size is 32767 bytes). The frequency grid of a mask must be monotonic increasing.
  • Load from file—Allows you to load a predefined custom channel compliance. Each mask definition starts with a keyword, followed by a pair of numbers that represent the data points for “Frequency (Hz)" and "Amplitude (dB)”. Following is a sample of a custom channel compliance mask file:

    IL Mask Min 
    1 0
    1e9 -1
    10e9 -2.5
    IL Mask Max
    1 0
    1e9 1
    10e9 2.5
    ILD Mask Min
    1 0
    1e9 -4
    10e9 -4
    ILD Mask Max
    1 0
    1e9 4
    10e9 4
    RL Mask
    1 -10
    1e9 -10
    10e9 -4
    ICR Mask
    1e9 55
    25e9 25
    ICN Mask
    1 10
    5 10
    25 0

When you click Plot, the Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list

• Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, crosstalk channels’ amplitude, and power sum of all crosstalk channels is shown. An example is illustrated in the above figure.
• Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation is shown, as in the following figure.

Figure 111. Channel Analysis Module’s Insertion Loss Deviation (ILD) Analysis Example

• Return Loss Plot—This plot is labeled CP: RL. In this plot, the return loss characteristics (both ends, i.e., Sdd11 and Sdd22) of channels are shown, as in the following figure.

Figure 112. Channel Analysis Module’s Return Loss (RL) Analysis Example

• Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels is plotted. ICR is calculated as the distance between the insertion loss and combined crosstalk channels, as in the following figure. When the Crosstalk Limit plot is not enabled, the Channel Viewer also calculates and displays integrated crosstalk noise (ICN or XTLKrms) in mV-RMS units.

Figure 113. Channel Analysis Module’s Insertion Loss to Crosstalk Ratio (ICR) Analysis Example

• Crosstalk Limit Plot—This plot is labeled CP: XTLK Limit. In this plot, a crosstalk noise figure, integrated crosstalk noise (ICN), or XTLKrms in mV-RMS units, is calculated based on the user configurations, as in the following figure.

Figure 114. Channel Analysis Module’s Crosstalk Limit Analysis Example

10GBASE-KR Channel Compliance

The following figure shows the 10GBASE-KR channel compliance check GUI.

Figure 115. 10GBASE-KR Channel Compliance Check User Interface

All parameters are predefined as described in the IEEE 802.3ap/10GBASE-KR standards, so there is no user input. Click Plot to proceed. Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list.

• Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, maximum insertion loss limits, crosstalk channels’ amplitude, and power sum of all crosstalk channels is shown. An example is illustrated in the above figure.
• Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation and ILD masks are shown, as in the following figure.

Figure 116. 10GBASE-KR Channel Compliance Module’s Insertion Loss Deviation (ILD) Analysis Example

• Return Loss Plot—This plot is labeled CP: RL. In this plot, return loss (RL) characteristics of channels and the RL mask are shown, as in the following figure.

Figure 117. 10GBASE-KR Channel Compliance Module’s Return Loss (RL) Analysis Example

• Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels and the ICR mask are plotted, as in the following figure.

Figure 118. 10GBASE-KR Channel Compliance Module’s Insertion Loss to Crosstalk Ratio (ICR) Analysis Example

OIF CEI-28G-SR 3.0 and OIF CEI-25G-LR Channel Compliances

The following figure shows the OIF CEI-28G-SR 3.0 channel compliance check GUI.

Figure 119.  OIF CEI-28G-SR 3.0 Channel Compliance Check User Interface

OIF CEI-25G-LR, OIF CEI-28G-MR, and OIF-CEI-28G-SR channel compliances are similar in configuration and usage. Both cases are covered in this section. All parameters are predefined as described in the OIF CEI-25G-LR, OIF CEI-28G-MR, and OIF-CEI-28G-SR standards, so there is no user input. Click Plot to proceed. Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list.

• Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, insertion loss masks, crosstalk channels’ amplitude, and power sum of all crosstalk channels are shown. An example is illustrated in the above figure.
• Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation and ILD masks are shown, as in the following figure.

Figure 120. OIF CEI-28G_SR 3.0 Channel Compliance Module’s Insertion Loss Deviation (ILD) Analysis Example

• Return Loss Plot—This plot is labeled CP: RL. In this plot, return loss (RL) characteristics of channels and RL mask are shown, as in the following figure.

Figure 121. OIF CEI-28G-SR 3.0 Channel Compliance Module’s Return Loss (RL) Analysis Example

• Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels and the ICR mask are plotted, as in the following figure.

Figure 122. OIF CEI-28G-SR 3.0 Channel Compliance Module’s Insertion Loss to Crosstalk Ratio (ICR) Analysis Example

• Crosstalk Limit Plot—This plot is labeled CP: XTLK Limit. In this plot, a crosstalk noise figure, XTLKrms in mV at Nyquist frequency, is calculated based on the user configurations, as in the following figure

Figure 123. OIF CEI-28G-SR 3.0 Channel Analysis Module’s Crosstalk Limit Analysis Example

Channel Operating Margin (COM) Channel Compliance and Analysis

Advanced Link Analyzer Channel Viewer is equipped COM computation engine that can compute COM values for selected channels. Users can select and import channels, via Add Transmission/FEXT/NEXT pull down menu or click Channel Viewer button within Advanced Link Analyzer main GUI, select the intended standards or COM Analysis, and then followed by clicking the Plot button. Channel Viewer performs a sequence of computation and present the results.

Insertion Loss (IL): Note that the power sum of all cross talk channels is also shown in the figure.

Figure 124.  Insertion Loss (IL) Plot of all channels

Insertion loss deviation (ILD)

Figure 125.  Insertion loss deviation (ILD) of the victim channel

Return loss (RL)

Figure 126.  Return loss (RL) of the victim channel

Insertion loss to crosstalk ratio (ICR)

Figure 127.  Insertion loss to crosstalk ratio (ICR) of selected channel

Single bit response (SBR) of equalized channel

Figure 128.  Single bit response (SBR) of equalized channel

Single bit response (SBR) of combined channel

Figure 129.  Single bit response (SBR) of combined channel

Bathtub curve

Figure 130.  Bathtub curve of the selected channel

COM

Figure 131.  COM value

• COM Analyzer

  The COM Analyzer allows you to perform customized COM analysis. In the COM Analysis mode, the COM parameters can be edited.

  Users can use the Template (Temp in the GUI) pull-down menu below the COM parameter table to select a COM standard and use it as a starting point for customizations. One can also save and load customized COM parameters from the Template menu.

  The original COM calculations assume certain scaling among the data rate (fb) and parameters, such as receiver continuous time linear equalizer’s (CTLE) pole and zero locations. When a user wants to compute COM at non-standard datarates or variable datarates (for OIF CEI standards for example), various COM parameters may need to be manually calculated and input into the table. The Channel Viewer’s COM analysis model implements the CTLE Auto Scale feature which allows the automatic frequency scaling of four CTLE parameters when CTLE_Auto_Scale is set to 1 in the COM configuration table. In the COM analysis:

  • CTLE_f_p1_div_factor: f_p1 is equal to fb/CTLE_f_p1_div_factor
  • CTLE_f_p2_div_factor: f_p2 is equal to fb/CTLE_f_p2_div_factor
  • CTLE_fz_div_factor: fz is equal to fb/CTLE_fz_div_factor
  • CTLE_f_HP_PZ_div_factor: f_HP_PZ is equal to fb/CTLE_f_HP_PZ_div_factor

Figure 132.  Systems Options Panel

Use this panel to select the following plot options:

• Enable Instant Plot—Enable and disable instant channel plotting when a new channel is added to the channel list. When you disable this option, you must click Plot to plot the channel response.
• Plot Combined Channel Response—When you enable this option, the Channel Observer cascades the channels with Loss type and plots it along with other channel characteristics. The crosstalk channels (NEXT and FEXT) are not cascaded.
• Auto. S-parameter Configuration Checker (ASCC)—Enable and disable the ASCC function. The Channel Viewer uses the ASCC function to determine the port configuration of S-parameters. When you disable ASCC, you must manually select the port configuration of each S-parameter channel model.
• Enable Channel Wizard—If checked, when you select a channel file, Channel Wizard helps configure the channel configuration. If unchecked, you must manually configure the channel configuration.
• S-parameter Integrity Check—If enabled, Channel Wizard checks the channel integrity (the passivity and causality). If Advanced Link Analyzer has problems with opening or accessing an S-parameter, you can disable the S-parameter Integrity Check.
• Touchstone 2.0 Support—Enable or disable Touchstone 2.0 S-parameter file support.
• Plot Axis Precision—Users can set the number of decimal points in the x- and y-axis of all plots.
• Time Domain Plot—Channel Views can automatically choose the common channel characteristics for time-domain analysis. For example, when Auto is selected, Channel Viewer chooses Sdd21 for impulse response, single bit response, and step response plots, and chooses Sdd11 for the TDR plot. If Auto Skip is selected, Channel Viewer chooses the likely matched channel types (if you selected any) for time domain analysis . For example, if you choose Sdd11, Sdd12, Sdd21, and Sdd22 and want to plot single bit responses, Sdd12 and Sdd21 are used for the plots, and Sdd11 and Sdd22 are skipped. When "Plot as is" is selected, Channel Viewer plots all time domain results for all selected S-parameter items.

The Advanced Link Analyzer Batch Simulation Controller allows you to run multiple simulations by not invoking the Advanced Link Analyzer Control Module. This capability allows you to run multiple link simulations and then review the results offline.

Figure 135.  Advanced Link Analyzer Batch Simulation Controller

The Advanced Link Analyzer Batch Simulation Controller accepts Advanced Link Analyzer simulation configuration (.jne) files. You can set up and save their link simulation configurations using the Advanced Link Analyzer Control Module. You can then add each individual Advanced Link Analyzer job to the batch job list and execute all the jobs.

The Advanced Link Analyzer Batch Simulation Controller has a built-in timer and house-keeping routine that constantly monitors the status of simulating tasks. It can also launch more than one simulation job at a time to better utilize the multi-core/multi-processor computing environment. Check whether your Advanced Link Analyzer license or license server supports multiple simulations at the same time.

After adding jobs, some key job information is shown in the job list, including simulation data rate, test pattern, simulation length, and initial job status of “Not Run”. After simulation, key simulation results, such as the final eye diagram height and weight, are displayed in the job list along with the simulation time.

The following options are available in the Advanced Link Analyzer Batch Simulation Controller user interface:

• Add—Add a Advanced Link Analyzer simulation job to the job list. Use the file browser to locate .jne configuration files.
• Delete—Delete the highlighted job in the job list.
• Enable/Disable—Enable or disable the highlighted job in the job list.
• Reset Select Jobs—Reset the status of highlighted jobs to “Not Run”
• Reset All Jobs—Reset all jobs in the job list to “Not Run”
• Clear All Jobs—Clear and delete all jobs in the job list
• View Job Configuration—Open and load Advanced Link Analyzer Control Module with the highlighted job
• Run Selected Job—Execute the highlighted job
• View Select Sim Result—Open and load simulation result (if available) of the selected job
• Move Up (/\)—Move the highlighted job forward in the job list
• Move Down (\/)—Move the highlighted job toward to back of the job list
• Load— Load Advanced Link Analyzer Batch Simulation Controller configuration file
• Save/Save as—Save or save new Advanced Link Analyzer Batch Simulation Controller configuration file
• Exit—Exit the Advanced Link Analyzer Batch Simulation Controller
• Stop—Stop batch simulation of jobs
• Start Batch Simulation—Start batch simulation of all not-executed jobs in the job list
• Maximum Concurrent Simulation Session—Set the number of concurrent simulations. Advanced Link Analyzer Batch Simulation Controller monitors the number of executing jobs. It starts a new simulation job when the computing resource is available.
• Simulation Result Display Option—This menu controls the simulation result display option. There are three options:
  • Display Result—When each simulation is completed, a new Data Viewer window shows the result.
  • Ask to Display Result—When each simulation is completed, a message box asks if you want to see the simulation results.
  • Manually Select Job & Display Result—This is the default option. When a job is finished, no result is shown. You must manually select the job and click View Selected Sim Result to see the simulation results.
• Simulation Window Close Time—When a simulation is completed, the Advanced Link Analyzer Simulation Engine window remains open for the specified time before closing.
• Output Directory—Specify the output directory in which to save all batch simulation results. This output location overrides the output directory option specified in each individual simulation job.

The Advanced Link Analyzer Channel Designer contains the following channel components:

• Stripline
• Coupled stripline
• Microstrip
• Coupled microstrip
• Coax
• RLGC transmission line
• Ideal transmission line
• Via model based on composite transmission line blocks
• Shunt and series capacitance
• Series inductance
• S-parameter model
• PCB stackup

A channel design can include one or multiple channel components. Advanced Link Analyzer Channel Designer can combine and generate Touchstone S-parameter models that can be used in link simulations. Advanced Link Analyzer Channel Designer provides user-friendly and integrated interfaces. The channel components and resulting channel models can be observed and analyzed using embedded plot functions or the Advanced Link Analyzer Channel Viewer.

In the 18.0 Advanced Link Analyzer release, a 2-port single-ended channel model is generated internally for the following components:

• Stripline
• Microstrip
• Coax
• RLGC transmission line
• Ideal transmission line
• Via model based on composite transmission line blocks
• Shunt and series capacitance
• Series inductance

After the single-ended model is generated, Advanced Link Analyzer Channel Designer converts it into a 4-port differential-pair format by assuming that these two single-ended channels are uncoupled.

A full 4-port single-ended channel model is generated for the following components:

• Coupled stripline
• Coupled microstrip
• S-parameter model

Advanced Link Analyzer supports PCB stackup dataset entries in the design space. You can specify multiple PCB stackup datasets within a channel designer project. Stripline, microstrip, coupled stripline, and coupled microstrip models can be generated from substrate parameters within each individual channel designer or using one of the PCB stack datasets in the design space.

Channel cascading of all channel components, which include coupled stripline, coupled microstrip, and S-parameter channel components, are done in the 4-port level.

Starting the Advanced Link Analyzer Channel Designer

You can start Advanced Link Analyzer Channel Designer in two ways:

• Double-click adv_link_analyzer_channel_designer.exe
• Click Channel Designer in the Advanced Link Analyzer Control Module

The Advanced Link Analyzer Channel Designer’s graphical user interface is shown in the following figure.

Figure 136.  Advanced Link Analyzer Channel Designer User Interface

• Connect—Use the straight line or right-angled line to connect channel components
• Edit—Delete, copy, or paste channel components
• Component—Individual channel components to be added to the channel. See sessions below for details
• Design Space
• Parameters—Set up system level parameters
  • S-parameter Max Frequency—Set the maximum frequency of the resulting channel model
  • S-parameter Frequency Step—Set the frequency step of the resulting channel model
  • Reference Impedance—Set the reference impedance of the resulting channel model
  • System Options
    • S-parameter Integrity Check—Select if checking channel integrity, such as passivity and causality, on the input S-parameter model. If Advanced Link Analyzer Channel Designer has issues opening or accessing certain S-parameter files, disable the channel integrity check to see if the issue is resolved.
    • Channel Caching—Advanced Link Analyzer stores the recent read S-parameter model in memory for quicker accesses. Select Enable to enable the caching capability. Select Disable to disable the caching capability. Channel caching is enabled by default.
    • Touchstone 2.0 Support—Use this menu to enable or disable Touchstone 2.0 S-parameter support.
    • Causality Check Options
      • SP Extrap Method—Use this menu to select S-parameter extrapolation method during causality checking. The default method is insertion loss fitting extrapolation method. The Last Amplitude Value option uses linear extrapolation and caps the amplitude at the last amplitude value from the S-parameter file.
      • Extrap Usage—The default is to cap the amplitude of the extrapolation at the last amplitude value in the S-parameter file. The Always Apply option uses the values from the extrapolation without any restrictions.
• Project management and Commands
  • Load—Load previously saved Channel Designer project
  • Save/Save as—Save current project
  • Reset—Clear all channel components
  • Plot All Components—Plot all individual channel components in the Design Space using Advanced Link Analyzer Channel Viewer
  • Plot Result Channel—Generate the result channel and plot its characteristics using Advanced Link Analyzer Channel Viewer
  • Generate s4p File—Generate the result channel and save it in a 4-port Touchstone S-parameter file
  • Quit—Exit Advanced Link Analyzer Channel Designer

Constructing a Channel in Channel Designer

Similar to the Link Designer operations in Advanced Link Analyzer’s Control Module, a channel consists of one or more channel components between the input port (Port 1) and the output port (Port 2). After the channel components are placed into the workspace, click Connect to connect the components. In Connect mode, one or two connectors are shown on each component. Connect the channel components by dragging the line from one connector to another. Two types of connections are provided in Channel Designer: Right Angled Line and Straight Line.

The following rules of channel construction apply to the Channel Designer:

• The Input port (Port 1) has one output port or connector
• The Output port (Port 2) has one input port or connector
• A channel component has one input and one output port
• A connection between two components can be established from an output port to an input port
• An Input port cannot be connected directly to an Output port

A channel establishment checking algorithm runs constantly in the background, checking whether a channel is established for channel generation. When a channel is established between an input port and an output port, the link lines become bold. The User Interface figure above shows an established channel link.

Channel Components

The Channel Designer contains the following components:

• Port 1—Port 1 is the input port of the channel under construction.
• Port 2—Port 2 is the output port of the channel under construction.
• S-parameter channel component—Use an S-parameter channel model file as part of the channel under construction. When you click the S-parameter icon, the Channel Wizard appears to help you configure the S-parameter file. Refer to the Advanced Link Analyzer Control Module’s Channel Wizard section for detailed usage. The following figure shows an example of the Channel Wizard.

Figure 137. Channel Wizard Example

Capacitance and Inductance Model Components

You can insert the following capacitance and inductance components as part of the channel:

• Shunt capacitance
• Series capacitance—Listed in the Channel Wizard under the AC Coupling Capacitor
• Series Inductance

Advanced Link Analyzer Channel Designer uses the Channel Wizard to configure these capacitance and inductance components so you can input the capacitance and inductance values there. The following figure shows an example.

Figure 138. Capacitance and Inductance Channel Component Configuration in Channel Wizard

Stripline Component

A stripline uses a flat strip of metal that is sandwiched between two parallel ground planes. The insulating material of the substrate forms a dielectric. The width of the strip, the thickness of the substrate, and the relative permittivity of the substrate determine the characteristic impedance of the strip which is a transmission line. A typical stripline structure is shown in the following figure with these parameters:

• Input parameters
  • W—Signal trace width (in various units)
  • L—Signal trace length (in various units)
  • Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The stripline cannot be placed on the top and bottom layers.
  • T—Signal trace thickness (in various units)
  • H—Separation between ground planes (in various units)
  • Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
  • TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
  • Cond—Conductor conductivity (S/m)
  • Rough—Surface roughness (in various units)
  • Mur—Relative permeability (no unit)
  • Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
  • Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
  • View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
• Output parameters
  • Z0—Impedance at specified frequency Freq (Ohm)
  • E-Eff—Electrical length (in various units)

Figure 139. Stripline Channel Component Configuration

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Microstrip Component

Microstrip is a type of electrical transmission line. It consists of a conducting strip separated from a ground plane by a dielectric layer known as the substrate. A typical microstrip structure is shown in the following figure with these parameters:

• Input parameters
  • W—Signal trace width (in various units)
  • L—Signal trace length (in various units)
  • Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The microstrip can only be placed on the top and bottom layers.
  • T—Signal trace thickness (in various units)
  • H—Separation between ground planes (in various units)
  • Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
  • TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
  • Cond—Conductor conductivity (S/m)
  • Rough—Surface roughness (in various units)
  • Mur—Relative permeability (no unit)
  • Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
  • Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
  • View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
• Output parameters
  • Z0—Impedance at specified frequency Freq (Ohm)
  • E-Eff—Electrical length (in various units)

Figure 140. Microstrip Channel Component Configuration

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Coax Component

A coax transmission line consists of two round conductors in which one completely surrounds the other. The two conductors are separated by a continuous solid dielectric. A typical coax structure is shown in the following figure with these parameters:

• Input parameters
  • a—Diameter of inner conductor (in various units)
  • b—Diameter of outer conductor (in various units)
  • t—Thickness of outer conductor (in various units)
  • Length—Length of the coax (in various units)
  • Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
  • TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
  • Cond (a)—Conductor conductivity of inner conductor (S/m)
  • Cond (b)—Conductor conductivity of outer conductor (S/m)
  • Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
• Output parameters
  • Z0—Impedance at specified frequency Freq (Ohm)
  • E-Eff—Electrical length (in various units)

Figure 141. Coax Channel Component Configuration

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

RLGC Transmission Line Component

The channel is constructed with unit length RLGC models. A typical RLGC transmission line structure is shown in the following figure with these parameters:

• Input parameters
  • L—Unit Length inductance (in various units)
  • Rdc—Unit length DC resistance (in various units)
  • Rac—Unit length skin-effect resistance (in various units)
  • C—Unit length capacitance (in various units)
  • Gdc—Unit length DC conductance (in various units)
  • Gac—Unit length AC conductance (in various units)
  • Length—Length of the coax (in various units)
  • Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
• Output parameters
  • Z0—Impedance at specified frequency Freq (Ohm)
  • E-Eff—Electrical length (in various units)

Figure 142. RLGC Transmission Line Channel Component Configuration

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Ideal Transmission Line Component

• Input parameters
  • Z0—Target impedance (Ohm)
  • Electrical length (in various units)

Figure 143. Ideal Transmission Line Channel Component Configuration

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Via Component

In printed circuit board design, a via consists of two pads in corresponding positions on different layers of the board. The pads are electrically connected by a hole through the board. In Advanced Link Analyzer Channel Designer, an analytical PCB Via model is constructed. A typical PCB via structure is shown in the following figure and the analytical via model structure is shown in the figure after that. The via is configured with the following parameters:

• Input parameters
  • Via
    • Impedance (Z3) (Ohm)
    • Electrical Length (td3) (in various units)
  • Pad 1
    • Capacitance (C1) (in various units)
  • Pad 2
    • Capacitance (C2) (in various units)
  • Via Stub 1
    • Impedance (Z1) (Ohm)
    • Electrical Length (td1) (in various units)
    • Termination (R1) (in various units)
  • Via Stub 2
    • Impedance (Z2) (Ohm)
    • Electrical Length (td2) (in various units)
    • Termination (R2) (in various units)

Figure 144. PCB Via Channel Component Configuration

Figure 145. PCB Via Analytical Model Structure

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

CHDE Component

Advanced Link Analyzer Channel Design can use an existing Advanced Link Analyzer Channel Designer project as a channel component. When you click the CHDE icon, a file browser opens and lets you select an existing Channel Designer configuration file.

Coupled Stripline Component

A coupled stripline uses a pair of flat strip of metal that is sandwiched between two parallel ground planes. The insulating material of the substrate forms a dielectric. The width of the strip, the separation/space between the strips, the thickness of the substrate, and the relative permittivity of the substrate determine the characteristic impedance of the strip which is a transmission line. A typical coupled stripline structure is shown in the following figure with these parameters:

Input parameters:

• W—Signal trace width (in various units)
• L—Signal trace length (in various units)
• Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The coupled stripline cannot be placed on the top and bottom layers.
• S—Signal trace separation distance (in various units)
• T—Signal trace thickness (in various units)
• H—Separation between ground planes (in various units)
• Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
• TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
• Cond—Conductor conductivity (S/m)
• Rough—Surface roughness (in various units)
• Mur—Relative permeability (no unit)
• Freq— Frequency where the Z0 (Impedance), K (coupling coefficient), Z0even (even mode impedance), Z0odd (odd mode impedance), and E-Eff (electrical length) are reported (in various units)
• Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
• View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.

Output parameters:

• Z0—Impedance at specified frequency Freq (Ohm)
• K— Coupling coefficient
• Z0even— Even mode impedance at specified frequency Freq (Ohm)
• Z0odd— Odd mode impedance at specified frequency Freq (Ohm)
• E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Figure 146. Coupled Stripline Channel Component Configuration

Coupled Microstrip Component

Coupled Microstrip is a type of electrical transmission line. It consists of a pair of conducting strips separated from a ground plane by a dielectric layer known as the substrate. A typical coupled microstrip structure is shown in the following figure with these parameters.

Input parameters:

• W—Signal trace width (in various units)
• L—Signal trace length (in various units)
• Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The coupled microstrip can only be placed on the top and bottom layers.
• S—Signal trace separation distance (in various units)
• T—Signal trace thickness (in various units)
• H—Separation between ground planes (in various units)
• Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
• TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
• Cond—Conductor conductivity (S/m)
• Rough—Surface roughness (in various units)
• Mur—Relative permeability (no unit)
• Freq— Frequency where the Z0 (Impedance), K (coupling coefficient), Z0even (even mode impedance), Z0odd (odd mode impedance), and E-Eff (electrical length) are reported (in various units)
• Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
• View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.

Output parameters:

• Z0—Impedance at specified frequency Freq (Ohm)
• K— Coupling coefficient
• Z0even— Even mode impedance at specified frequency Freq (Ohm)
• Z0odd— Odd mode impedance at specified frequency Freq (Ohm)
• E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.

After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Figure 147. Coupled Microstrip Channel Component Configuration

PCB Stackup Component

A printed circuit board (PCB) stackup describes the basic construction of a PCB. Specifically, the stackup defines the total number of PCB layers and the type and characteristics of each of these layers.

The PCB stackup structure is shown in the following figure.

Figure 148. PCB Stackup Configuration

Input parameters:

• Number of Layers—Specify the number of PCB layers.
• Material Type—Select the type of PCB material. This sets the default relative dielectric constant (Er or Dk) and dielectric loss tangent (TanD or Df) associated with the selected PCB material. Each layer can have its own Er and TanD values. You can manually update the Er and TanD of each layer. The supported material types are:
  • FR4—Default: Dk/Er = 3.8 and TanD/Df = 0.011
  • Rogers—Default: Dk/Er = 3.4 and TanD/Df = 0.0027
  • Nelco—Default: Dk/Er = 3.7 and TanD/Df = 0.009
  • Megtron4—Default: Dk/Er = 3.8 and TanD/Df = 0.005
  • Megtron6—Default: Dk/Er = 3.63 and TanD/Df = 0.004
  • Material Option 1—When selected, the Dk/Er and TanD/Df values are specified in the Material Option 1 tab page. This material option supports frequency-dependent Er/Dk and TanD/Df. See Figure 149 for an example.
  • Material Option 2—When selected, the Dk/Er and TanD/Df values are specified in the Material Option 2 tab page. With this option, you can specify the Dk/Er and TanD/Df values for top/bottom and middle layers separately. This material option also supports frequency-dependent Er/Dk and TanD/Df. See Figure 150 for an example.
• Top/Bottom Substrate Height—This is the default substrate layer height value for the top and bottom layers when the PCB stackup table is initiated. You can select the appropriate length unit that suits their use.
• Middle Substrate Height—This is the default substrate layer height value for the middle PCB layers when the PCB stackup table is initiated. You can select the appropriate length unit that suits their use.
• Top/Bottom Metal Thickness—This is the default metal layer thickness for the top and bottom PCB layers. You can select the appropriate length unit that suits their use.
• Middle Metal Thickness—This is the default metal layer thickness for the middle PCB layers. You can select the appropriate length unit that suits their use.
• Conductivity—The default conductor conductivity (S/m) when the PCB stackup is initiated.
• Surface Roughness—The default surface roughness (in various units) when the PCB stackup is initiated.
• Copper mils/oz—The conversion factor when the metal thickness is specified in copper weight (oz)
• Enforce Symmetry—Choose to enforce the symmetry of the to-be-generated PCB stackup. If enabled, only the top half of the PCB stackup can be edited or modified; the lower-half PCB layers are automatically matched to the top layers. The default setting is Enable.
• Generate—Click Generate to generate the PCB stackup using the default values mentioned above.

Figure 149. PCB Stackup with Material Option 1

Figure 150. PCB Stackup with Material Option 2

If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

This tutorial uses Advanced Link Analyzer to run a link simulation. This example and its associated channel models are provided with the Advanced Link Analyzer distribution. The configuration file Demo.jne (included in the software distribution) contains the same link topology and a majority of the link settings discussed in this tutorial.

In this tutorial, a link that approximates a typical PCI Express^® 8GT system with an Intel Stratix^® V GX transmitter and a generic PCI Express^® 8GT receiver is built and simulated in Advanced Link Analyzer. The following figure shows the link topology.

Figure 151. Example of PCI Express^® 8GT Link Topology

This simulation emulates an Intel Stratix^® V GX transmitter (with embedded package model), a PCI Express^® 8GT receiver (with embedded package model), and a ~18-inch backplane channel. Per PCI Express^® 8GT specifications, the link operates at 8 Gbps with a bit error rate (BER) < 10^–12. The transmitter must have a minimum differential output voltage of 800 mV and a rise/fall time of ~35 ps (at 0.8 V V_OD). In this simulation, the Stratix^® V GX transmitter is set to 800 mV V_OD (VOD level = 40). Additionally, the Stratix^® V GX transmitter has a 4-tap FIR to compensate for channel effects. The PCI Express^® 8G receiver has CTLE and a 1-Tap DFE per PCI-SIG definition.

To accomplish these goals, set up a transmitter model, a receiver model, and a link with the following parameters:

• Data rate: 8 Gbps
• Test pattern: PRBS-23
• BER target: BER < 10^–12
• Stratix^® V GX transmitter
  • V_OD: 800 mV (VOD Level = 40)
  • Edge rate: Per Stratix^® V GX characteristics
  • 4-Tap TX FIR (1 pre-tap and 2 post-taps)
  • Stratix^® V GX package model (embedded)
  • PLL: ATX (LC) set to low bandwidth
  • Output Jitter: Retrieved from the Intel Characterization Database (embedded in Advanced Link Analyzer; contact your Intel representative to enable this function)
    • DCD = ~0.012 UI
    • BUJ = ~0.032 UI
    • RJ = ~1.00 ps_RMS (8 Gbps, BER < 10^–12)
• Receiver
  • CTLE:
    • Programmable with 6 dB~12 dB boost at 4 GHz
    • Per PCI-SIG specifications
  • 1-tap DFE
  • PCI-SIG receiver package model (12-port S-parameter model from PCI-SIG)
  • CDR: Generic binary CDR with high loop bandwidth ~26 MHz
  • Receiver Jitter:
    • DJ = ~7 ps
    • RJ = ~1.55 ps_RMS (at BER < 10^–12)

The ~18-inch backplane channel is described by a 12-port S-parameter model. The S-parameter is measured (or generated) with port configuration type 2, as shown in the following figure:

Figure 152. 12-port S-parameter with Port Configuration Type 2

Figure 153. Channel Characteristics (Using Advanced Link Analyzer Channel Viewer with Data Cursor Enabled)

The Advanced Link Analyzer Channel Viewer shows that the backplane channel has approximately 17.15 dB loss at 4 GHz. The PCI-SIG RX package has 3.5 dB insertion loss at 4 GHz. The overall link has about 21 dB of loss (as shown in the Combined Channel black curve, not including Stratix^® V GX transmitter package) at 4 GHz, which requires heavy TX and RX equalizations to achieve the required BER target.

For comparative purposes, the following table and figure show a typical external 100 MHz transmitter reference clock with measured phase noise characteristics and spurs at three different frequencies.

Figure 154. Transmitter Reference Clock Characteristics

The PLL in the Stratix^® V GX transmitter is enabled using ATX (LC) with low bandwidth configuration. The PLL effectively reduces the noise effects from the external reference clock.

Use the Advanced Link Analyzer’s link optimization algorithm to find the optimal equalization settings for both the transmitter and receiver. In this demonstration, you use the CTLE=>FIR+DFE link optimization method.

Link and Simulation Setting Tab

Figure 155. Link and Simulation Setting

Set the following parameters in the Link and Simulation Setting tab:

• Data Rate: 8 (Gbps)
• Simulation Length: 65536 (Bits)
• Target BER: 10^ -12
• Test Pattern: PRBS-23
• Reference Clock: 100 (MHz)
• Link Optimization Method: CTLE=>FIR+DFE
• FOM of Link Optimization: Area
• Compliance Mask: PCI Express^® 8GT
• FEC: Off. This disables forward error correction (FEC) modeling since the transmitter and receiver do not support FEC.
• Project Name: Demo
• Simulation Mode: Hybrid
• Output Options: Data Viewer with Image Output. This option tells Advanced Link Analyzer to generate image files (.png) for all output plots.
• Jitter Analysis Options: Disable. This selection disables the jitter analysis function during the link simulation.

Click Reference Clock Option.

Figure 156. Reference Clock Configuration

• Turn off the Ideal Reference Clock option
• Click the Option 2: Phase Noise tab
• Turn on the Select TX Reference Clock Option 2 option
• Type or copy the phase noise and spur data in the text boxes as shown in the above figure. The reference clock phase noise data can be found in the example configuration file Demo.jne.

Transmitter Tab

Figure 157. Transmitter Settings

Set the following parameters in the Transmitter tab:

• Transmitter: Stratix^® V GX
• Package: Stratix^® V GX
• VOD Selection: 40 (~800 mV)
• Pre-emphasis: Auto
• PLL Type: ATX (LC)
• PLL Bandwidth: Low
• Jitter/Noise Component:
  • If the Intel Device Characterization Data Access function is enabled, click Characterization Data Access. (A message box appears. Read and close the message box.) Transmitter jitter figures are populated automatically and the jitter/noise modeling mode is selected.
  • If Intel Device Characterization Data Access is not available, manually type in the jitter numbers shown in the above figure. Note that the simulation results might differ slightly if the jitter data is from manual input.

Receiver Tab

Figure 158. Receiver Settings

Set the following parameters in the Receiver tab:

• Receiver: PCI-Express 8GT
• Package: PCI-Express 8GT
• CTLE Setting: Auto
• DFE Mode: Auto
• CDR Type: Bang-Bang
• CDR Bandwidth: Medium
• PVT Process: Typical
• PVT Voltage: Typical
• PVT Temperature: 25 deg C
• DJ: 0.056 (UI, 7 ps)
• RJ: 1.55 ps (RMS) (key-in and then use pull-down menu to set RJ unit)

Click Receiver Options. In the Receiver Configuration window, click the Equalization tab. Set DFE Tap Length to 1 and Step Size to 0.0078125.

Figure 159. Additional Receiver Configuration

Next, construct the channel between the transmitter and receiver. In Advanced Link Analyzer, the package models for the Stratix^® V GX transmitter and PCI Express^® 8GT receiver are embedded. The transmitter and receiver packages are automatically included in the simulation.

Advanced Link Analyzer supports crosstalk modeling capabilities. The channel engine and simulation engine can extract and interpret crosstalk characteristics from a single or a multi-lane S-parameter file and compute the crosstalk effects. In the channel list, crosstalk channels are assumed to run in parallel with the victim channel and the crosstalk noises are superimposed. This section describes how to set up crosstalk simulation in Advanced Link Analyzer.

The backplane model is provided as a 12-port S-parameter. It consists of both insertion loss and crosstalk characteristics. However, Advanced Link Analyzer requires you to add them one at a time (even if the loss and crosstalk characteristics are from the same multiple-lane S-parameter file). Therefore, you are going to insert three channel components during channel setup: one backplane victim channel and two backplane aggressor channels.

Perform the following steps to add a victim channel:

1. Click Channel in the Link Designer and select Transmission.
2. Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as victim.
3. The Advanced Link Analyzer Channel Wizard displays the Sdd21 characteristics of the middle lane (lane 2) in the 12-port S-parameter.
4. Click OK to close the Channel Wizard.
5. Place the channel icon in the Link Designer.

Figure 160. Configure Victim Channel with Advanced Link Analyzer Channel Wizard

Perform the following steps to add the first crosstalk channel:

1. Click Channel in the Link Designer panel and select Far-end Crosstalk (FEXT).
2. Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as FEXT.
3. The Advanced Link Analyzer Channel Wizard displays the FEXT #1 characteristic. Note that the Crosstalk Aggressor Location 1 is selected in for this channel.
4. Click OK to close the Channel Wizard.
5. Place the channel icon in the Link Designer.

Figure 161. First Far-end Crosstalk Configuration in Channel Wizard

Perform the following steps to add the second crosstalk channel:

1. Click Channel in the Link Designer panel and select Far-end Crosstalk (FEXT).
2. Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as second FEXT.
3. The Advanced Link Analyzer Channel Wizard displays the first FEXT channel characteristic by default.
4. Change the Crosstalk Aggressor Location to 2. This tells Advanced Link Analyzer to select the second FEXT in the12-port S-parameter.
5. Set the aggressor frequency offset to 300 ppm to emulate the phase shifting effect for this crosstalk noise source. This setting indicates the 2nd crosstalk is not frequency synchronous to the victim channel.
6. Click OK to close the Channel Wizard.
7. Place the channel icon in the Link Designer.

Figure 162.  Second Far-end Crosstalk Configuration in Channel Wizard

All the link components are now chosen and placed in the Link Designer. Click Connect in the Link Designer to begin connecting the components. Refer to the Link and Simulation Setting section for link construction in the Link Designer. The following figure shows the completed link system.

Figure 163. Complete Link Connection in Link Designer

The link configuration is complete. Use the Save/Save as buttons to save the configuration for later use.

Use the Channel Viewer to observe and analyze the channel characteristics. The Channel Viewer button is located on the right side of the Channel tab. This example shows the Sdd21 of the three channels you selected as well as the channel responses at test points and the overall channel. You can leave the Channel Viewer module open or close it by clicking OK or Exit.

Figure 164. Channel Characteristics of Victim and 2 FEXT Channels (with Data Cursor Enabled)

Start the channel simulation by clicking Simulate in the lower right corner of the Advanced Link Analyzer Control Module. The Advanced Link Analyzer Simulation Engine simulates all the models and generates eye diagrams at test points and inside the receiver (after CTLE and DFE).

A goal of this tutorial was for Advanced Link Analyzer to automatically find the optimal link setting for both transmitter and receiver. In the simulation time, the progress bar flashes, indicating the Advanced Link Analyzer Simulation Engine is exploring the solution space. The link performance and result of the final setting is shown in a Advanced Link Analyzer Data View.

At TX output, which is located after the Intel Stratix^® V GX transmitter output pin (after the TX package model), the results are shown in the following figure. Advanced Link Analyzer found the optimal TX-FIR setting: Pre-tap 1 = –4, Post-tap 1 = 2, and Post-tap 2 = 0. The configured transmitter generates ~0.83 UI of jitter at BER = 10^-12. This set of TX outputs is measured with an ideal clock. In addition to the transmitter’s intrinsic jitter, the reference clock’s jitter and noise (recall that external reference clock phase noise and spurs in this simulation are filtered by the Stratix^® V GX ’s PLL) are seen here.

• The first figure is a hybrid eye diagram that includes deterministic jitter and probability density function (PDF) because of unbounded jitter and noise sources.
• The second figure (top right) contains the cumulative distribution (CDF) eye diagram with BER bathtub curves (for both width and height in the eye diagram opening).
• The third plot (lower left) is a BER contour plot that shows the eye diagram opening area at various BER targets.
• The fourth plot shows Q-Factor curves, which are another representation of BER bathtub curve using Q-factor by assuming the noise/jitter is Gaussian.

With the Gaussian random jitter injected into the link, the BER bathtub and Q-Factor plots clearly show the effects where this unbounded jitter narrows the eye diagram width as the BER target reduces.

Figure 165. TX Output Hybrid Eye Diagrams and BER Analysis Measured with Ideal Clock

The second set of TX outputs are measured with the golden CDR, which has a loop bandwidth of 1/1667 of the data rate. This set of outputs reflects the common lab scope measurement. With the golden CDR in place, the low frequency jitter and noise, which are included in phase noise and spurs, are tracked.

The following figure shows the Time Interval Error (TIE) plots before and after the golden CDR. With reference to the ideal clock (that is, before the golden CDR), the low frequency sinusoidal jitter from the reference clock characteristics can be clearly observed in the plot on the left. After the golden CDR, those low frequency sinusoidal jitters are tracked as shown in the plot on the right. The figure also shows the jitter components results that reflect the effects of the golden CDR (Beta feature).

Figure 166. Transmitter Output TIE (Time Interval Error) Plots with Reference Clock Phase Noise and Spurs Before and After the Golden CDR

In the following figure, the transmitter output jitter, which includes transmitter intrinsic jitter and PLL filtered reference clock jitter, is about 0.17 UI at BER 10^-12.

Figure 167. Transmitter Scope Output Measured with Golden CDR

When you enable a PLL in a transmitter, the reference clock’s phase noise is shaped and filtered with the PLL’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after the transmitter PLL (green), after the transmitter PLL plus the transmitter’s intrinsic jitter (red), after the Golden CDR (most likely in a scope, cyan), and after the Golden CDR with transmitter’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages are calculated and displayed in the text below the plot.

Figure 168. Reference Clock Phase Noise Characteristics Before and After TX PLL

At the channel output, which is located at the end of backplane channel with crosstalk, the eye diagram is largely closed because of the large channel loss from the TX package and the backplane.

Figure 169. Channel Output Hybrid Eye Diagrams and BER Analysis

The CTLE is a PCI Express^® 8GT CTLE behavior model output stage. The Advanced Link Analyzer's link optimization algorithm has identified the optimal gain setting at 10 dB level. Similar to the TX output case, when the receiver CDR is enabled or included in the simulation, two sets of CTLE outputs can be shown but, by default, Advanced Link Analyzer only outputs CDR retimed output when the receiver CDR is enabled. The first set of outputs is with the ideal clock and the second one is with the CDR recovered clock. The total jitter is ~0.94 UI (at BER < 10^-12, with ideal clock, result not shown by default because receiver CDR is enabled) or ~0.56 UI (with CDR recovered clock). The eye diagram opening height is ~7 mV (with ideal clock, result not shown by default because receiver CDR is enabled) and ~42 mV (with recovered clock). The eye diagram opening is marginal to PCI Express^® 8GT requirements. Therefore, further equalization of the signal with DFE is needed.

Figure 170. CTLE Output Hybrid Eye Diagram and BER Analysis with CDR Recovered Clock

When you enable CDR in a receiver, the reference clock’s phase noise is shaped and filtered with the CDR’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after the transmitter PLL (red), after the transmitter PLL plus the transmitter’s intrinsic jitter (red), after the RX CDR (cyan), and after the RX CDR with transmitter and receiver’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages was calculated and displayed in the text below the plot.

Figure 171. Phase Noise of Reference Clock and Its Transitions through PLL and CDR

At the output of the PCI Express^® 8G receiver’s 1-Tap DFE, the following figures show that the DFE has further opened the eye diagram with a total jitter of ~0.96 UI (at BER < 10^-12, with ideal clock and sinusoidal jitter from the transmitter reference clock, result not shown by default because receiver CDR is enabled) and ~0.59 UI (with CDR recovered clock) and eye diagram opening height of ~3 mV (with ideal clock, result not shown by default because receiver CDR is enabled) and ~60 mV (with recovered clock). The BER bathtub curve and contour show good behavior and successfully meet the PCI Express^® 8GT RX requirements (TJ < 0.7 UI and eye diagram height > 25 mV; refer to PCI Express^® Base Specification 4.3).

The PCI Express^® 8GT eye diagram mask is shown in the following figure to see the margins to the specification limits.

Figure 172. TP4 Hybrid Eye Diagram Measured with CDR Recovered Clock and PCI Express^® 8GT Receiver Eye Diagram Mask

When you enable a CDR in a receiver, the reference clock’s phase noise is shaped and filtered with the CDR’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after transmitter PLL (red), after transmitter PLL plus transmitter’s intrinsic jitter (red), after RX CDR (cyan), and after RX CDR with transmitter and receiver’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages are calculated and displayed in the text below the plot.

Figure 173. Phase Noise of Reference Clock and Its Transitions through PLL and CDR

These examples demonstrated how to use Advanced Link Analyzer to set up a serial link and evaluate its link performance. Advanced Link Analyzer allows you to:

• Configure a link
• Configure an external reference clock
• Configure a transmitter and receiver
• Configure a channel
• Configure and model jitter and noise sources
• Derive accurate jitter figures for Intel devices from the Intel JBE database
• Load and save a link configuration
• Observe the channel characteristics
• Set up test points within the link
• Compute and observe an eye diagram
• Perform BER analysis