Advanced Link Analyzer: User Guide
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 21.1 |
1. System Requirements and Installation Guide

Advanced Link Analyzer is a high-speed transceiver link simulator. When you design high-speed, multi-gigabit transceiver links, you must ensure the end-to-end performance from transmitter (TX) to receiver (RX) and all interconnects in between.
Advanced Link Analyzer's graphical user interface (GUI) and link simulator allows you to quickly and easily set up and evaluate high-speed link performance early in your design cycle. Advanced Link Analyzer also helps you identify possible issues in board level design. With Advanced Link Analyzer, you can quickly estimate optimal link equalization and other electrical parameter settings for transmitter and receiver. You can also use Advanced Link Analyzer to predict link performance such as jitter and noise at a small probability level.
1.1. System Requirements
Advanced Link Analyzer has the following minimum system requirements:
- Microsoft Windows 7, Windows 8, Windows 10, Windows Server 2008, Windows Server 2012, Windows Server 2016, and Windows Server 2019
- 4 GB RAM
- 9 GB storage space
- Microsoft .NET Framework 4.8
Advanced Link Analyzer requires an Intel® Quartus® Prime software pro/standard license to perform simulations, design channels, and view channel characteristics. Contact My Intel® support if you have questions regarding accessing the Intel® Quartus® Prime software pro/standard license. Advanced Link Analyzer works independently without the Intel® Quartus® Prime software (except the licensing check). Thus, you do not need to install the Intel® Quartus® Prime software for installing or using Advanced Link Analyzer.
Starting with the Intel® Quartus® Prime software version 21.1 release, Advanced Link Analyzer utilizes the Intel® Math Kernel Library (MKL), which improves simulation and analysis performance. The Advanced Link Analyzer installer includes all required MKL run-time library files, so you do not need to install Intel MKL separately on your system.
1.2. Installation
Installing the Advanced Link Analyzer
To install Advanced Link Analyzer, perform the following steps:
- Acquire the current
version of the
Advanced Link Analyzer Installation Package from the
Intel Download Center.
- Go to the Intel Download Center.
- Click Select by Software.
- Select Select Software Products > Intel® Advanced Link Analyzer Pro Edition or Intel® Advanced Link Analyzer Standard Edition.
- Select Select Version or Product and select a version. Intel® recommends selecting the latest version.
- Click Download to start downloading the installer.
- Execute the installation file to install Advanced Link Analyzer.
- Execute Advanced Link Analyzer.exe to start Advanced Link Analyzer. Advanced Link Analyzer comes with both 32-bit and 64-bit executables. 32-bit Advanced Link Analyzer is located in <Advanced Link Analyzer Installation Directory>\bin and 64-bit Advanced Link Analyzer is in <Advanced Link Analyzer Installation Directory>\bin64. For example, the most common installation folder for 64-bit is C:\intelFPGA_pro_ala\<current version>\adv_link_analyzer\bin64.
- Starting with the 19.3 version, the Advanced Link Analyzer installation directory is write-protected so that no data or files can be created or modified in it.
Specifying a Different Working Directory
When you execute the Advanced Link Analyzer for the first time, the Advanced Link Analyzer might request for your permission to create an Advanced Link Analyzer working directory at C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\GUI_Work. Click Yes to use the default location.
- Exit the Advanced Link Analyzer.
- Create an environment variable ALAUserWorkDirectory, and specify the full path name of the desired work directory location.
- Start the Advanced Link Analyzer. The Advanced Link Analyzer requests you to create a work directory in the specified location.
- Click Yes to complete.
Preserving Existing Settings and Installed Device Models
If you upgrade from the previous version of the Advanced Link Analyzer and you want to preserve your existing settings and installed device models, Intel® recommends you follow these steps:
- Install the Advanced Link Analyzer using the installer.
- Start the newly installed Advanced Link Analyzer main GUI and allow the GUI to complete the setup process, for example, creating a work directory.
- Close the Advanced Link Analyzer.
- Copy the existing settings and/or data files, for example, files in C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<previous version>\ to a new location, for example, C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\.
- Start the Advanced Link Analyzer.
With the above steps, your license and settings should be migrated to the current version.
Handling Write-protection Issue During Simulation
Due to the Intel® Quartus® Prime software write protection, some legacy Intel® IBIS-AMI models, for example, Intel® Stratix® 10 L-tile and H-tile receiver models, can cause issues during simulations. This does not happen universally, and the issues depend on your computer’s security and access control settings. An internal solution was developed during the 20.4 release to redirect the simulation output to the project output folder, which should resolve this issue (see System Options for details). In case you still experience the write-protection related issue, perform one of the following:
- Get administration write access to your account or computer. You may need to contact your IT support for this option.
- Copy your Advanced Link Analyzer installation to somewhere outside the original installation folder. For example, you can copy your installation from C:\intelFPGA_pro\21.1\adv_link_analyzer to C:\tmp\adv_link_analyzer, and then change the new folder’s (include folder, sub-folders, and files) attributes so that it is not read-only. Launch Advanced Link Analyzer from this new location.
Intel recommends that you install and run the Advanced Link Analyzer in local storage space. Because the Advanced Link Analyzer can create temporary working files in storage space, simulation speed can be impacted if the installation or temporary files are located in a network drive or remote storage space. If you need to use remote storage space, the Advanced Link Analyzer provides an option to specify the simulation working directory. You can configure your local storage space as the simulation working directory to improve simulation speed. See System Options for details.
The Advanced Link Analyzer requires an Intel® Quartus® Prime software license to perform simulations, design channels, and view channel characteristics. Contact My Intel support if you have questions regarding accessing the Intel® Quartus® Prime software pro/standard license.
Configuring License Checking Configurations
The Advanced Link Analyzer automatically checks the license server specified in the system environment variable LM_LICENSE_FILE for the required license. You can configure the license checking configuration by editing the following entries in the configuration file JNEye_Config.dat:
- %% LM_License_File_Name—License file name. If a license file is specified, the Advanced Link Analyzer validates the license in this file. If the license is not valid, the license server (specified in LM_LICENSE_FILE) is used. The default value is na.
- %% LM_License_Feature_Name—The feature or type of license to be checked out for the Advanced Link Analyzer use. The default value is quartus.
The JNEye_Config.dat file is located in Advanced Link Analyzer's C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\ <current version> folders.
Troubleshooting
If you have problems running the Advanced Link Analyzer after installing the program, follow these instructions:
- Verify that Microsoft
Visual C++ 2017 library is installed on your system. If you
execute Advanced Link Analyzer in a system
that does not have the Microsoft Visual C++ 2017 library, you get an error
message.
- If you do not
have the Visual C++ 2017 library installed, download it from the
Microsoft web site, and install it. Note: For 64-bit Windows operating systems, the 32-bit version of the Visual C++ 2017 library is required for running the 32-bit version of the Advanced Link Analyzer.
- If you do not
have the Visual C++ 2017 library installed, download it from the
Microsoft web site, and install it.
- Verify that the
Microsoft .NET Framework 4.8 is installed on your system. If you execute the
Advanced Link Analyzer in a system that does
not have Microsoft .NET Framework 4.8, you get an error message.
- You may have to install Windows Imaging Component (WIC) before installing .NET Framework 4.8. You can download WIC from the Microsoft web site.
- Download .NET Framework 4.8 from the Microsoft web site and install it.
1.3. Program and File Types
Advanced Link Analyzer comes with the following executable files:
- adv_link_analyzer.exe—Advanced Link Analyzer’s main user interface
- adv_link_analyzer_sim_eng.exe—Advanced Link Analyzer simulation engine
- adv_link_analyzer_sim_eng_console.exe—Advanced Link Analyzer simulation engine (console version)
- adv_link_analyzer_data_viewer.exe—The Advanced Link Analyzer Data Viewer displays simulation results
- adv_link_analyzer_channel_viewer.exe—The Advanced Link Analyzer Channel Viewer displays channel characteristics
- adv_link_analyzer_batch_sim.exe—The Advanced Link Analyzer Batch Simulation Controller runs simulations in batch mode
- adv_link_analyzer_channel_designer.exe—Advanced Link Analyzer’s channel designer that generate S-parameter channel models for link simulations
Advanced Link Analyzer uses the following file extensions:
- .jne—Advanced Link Analyzer simulation configuration
- .jneschm—Advanced Link Analyzer simulation schematic configuration
- .jnetxdata, .jnerxdata, .jnedevdata, .jneledata, and others—Advanced Link Analyzer internal data
There are two ways to share an Advanced Link Analyzer project:
- Project Archiver/Project Unarchiver method: Project Archiver and Project Unarchiver are GUI-based functions that collect and package channel model files, device model files (if applicable), and link settings in a single data file for sharing. See Archiving and Unarchiving Projects for details.
- Manual method: Both .jne and .jneschm files are needed for other users to reload the link configuration in their Advanced Link Analyzer session. Make sure all other associated files, such as channel model files and device model files, are available or included so that simulations can run correctly.
Advanced Link Analyzer provides limited backward compatibility with link configuration files saved in previous versions.
1.4. Accessing the User Guide
- Click the Advanced Link Analyzer logo located in the upper left of the GUIs to open the license/version window.
- Click the User Guide button in version/license window.
2. Functional Description
2.1. Advanced Link Analyzer Control Module

2.1.1. Constructing Communication Links in the Link Designer Module
The Link Designer module allows you to construct communication links.

Transmitter (TX) Component |
Channel/Link Component |
Receiver (RX) Component |
---|---|---|
Intel® Agilex™
Stratix®
Arria®
Generic
IBIS-AMI
Intel®
Cyclone® 10
|
Channel
Crosstalk
Channel Designer
Basic Component
Link Component
|
Intel® Agilex™
Stratix®
Arria®
Generic
IBIS-AMI
Intel®
Cyclone® 10
|
Advanced Link Analyzer supports the following simulations:
- Intel TX to Intel RX
- Intel TX to non-Intel RX
- Non-Intel TX to Intel RX
- Non-Intel to non-Intel link simulations are not supported.
- For Intel® devices that are not listed in Table 1, contact My Intel® support, and acquire the IBIS-AMI models.
- Devices supported with wrapper technology can be added, removed or updated to Advanced Link Analyzer after the tool is installed. Please refer to IBIS-AMI Wrapper for further details.
A link consists of a transmitter, a receiver, and one or more channel/link components. Select the transmitter, receiver, and channel/link components from the menus at the top of the Link Designer workspace.
After the link components are placed into the workspace, click Connect to connect the components. In connect mode, one or two connectors are shown on each component. Connect the link components by dragging the line from one connector to another. Two types of connections are provided in Link Designer: Right Angled Line and Straight Line. Right Angled Line is the default connection method. Test points can be manually placed into the link by clicking Test Point and connecting to the desired location in the link.
The following rules of link construction apply to the Link Designer module:
- A transmitter can only have one output port or connector
- A receiver can only have one input port or connector
- A channel/link component has one input and one output port
- A test point can only be connected to an input port
- A connection between two components can be established from an output port to an input port
- A transmitter cannot be connected directly to a receiver
A link establishment checking algorithm runs constantly in the background, checking whether a link is established for simulations. When a link is established between a transmitter and receiver, the link lines become bold and color-coded. Bold black lines indicate signal paths, green lines indicate crosstalk signal paths, and purple lines point to test point port locations. The following figure shows an example link topology. A table of link components is displayed in the Channel tab for reference.

When a channel component (for example, a transmission line, connector, far-end crosstalk (FEXT), near-end crosstalk (NEXT), package, AC coupling capacitor, or shunt capacitor) is chosen, the Channel Wizard helps you verify or set the channel configuration.

The Channel Wizard displays the channel characteristics and allows you to verify the correctness of the channel component, such as a component represented by an S-parameter. The Channel Wizard allows you to select the following components:
- channel type
- port configuration
- signal lanes (for multiple-lane S-parameters with eight and more ports)
- crosstalk aggressor location (for multiple-lane S-parameters)
- aggressor
- series inductance value (in nH)
- AC coupling capacitor value (in nF)
- shunt capacitance value (in pF)
The Channel Wizard checks the integrity of the channel component in terms of passivity and causality characteristics. When the Channel Wizard detects passivity and causality violations, it displays messages about the severity of the violations in the text box on the left of the OK button. The levels of channel integrity violation are listed in the following tables. Advanced Link Analyzer provides the option to enforce or improve causality of the selected channel during a simulation when Enforce Causality is turned on.
Passivity Violation Check Results | Impact on Link Simulation Accuracy | Recommendations |
---|---|---|
No Passivity Violation | No impact | No action needed |
Slight Passivity Violation | There may not be a noticeable effect in the simulation result. | The channel model can be further improved but the improvement in terms of simulation results accuracy can be small. |
Minor Passivity Violation | There may be a noticeable effect in the simulation result. | The channel model can be further improved. Simulation result accuracy can be reduced. |
Passivity Violation | Simulation result impact | The channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low. |
Causality Violation Check Results | Impact on Link Simulation Accuracy | Recommendations |
---|---|---|
Channel is causal | No impact | No action needed |
Slight non-causal | There may not be a noticeable effect in the simulation result | The channel model can be further improved but the improvement in terms of simulation results accuracy can be small. |
Somewhat non-causal | There may be a noticeable effect in the simulation result | The channel model can be further improved. Simulation result accuracy can be reduced. |
Non-causal | Simulation result impact | The channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low. |
An existing channel can be changed by adding a new channel component or by modifying an existing channel component. Right-click in the Link designer module and select Properties.
When using the package channel component, follow these guidelines:
- Package models should be placed next to the devices.
- Each device can have only one package model. Therefore, the external package model can only be used when the device’s package type is “Custom”.
- The package model type is used by the simulation engine to identify the boundary of the devices and generate a waveform for observation and analysis.
- The package model is treated the same way as the “Transmission” channel type. Therefore, use the “Transmission” channel type even if the model represents a physical package (in your system) but it is not a package of the TX and RX.
2.1.2. Link and Simulation Setting
The Link and Simulation Setting tab sets the global link parameters and simulation configurations.

The Link and Simulation Setting dialog box contains the following fields.
Data Rate
Link data rate is specified in Gbps.
Simulation Length
Simulation length is specified in the number of bits running at the specified data rate. Simulation length should be at least 4096 bits. Intel recommends that the length is a power-of-2 factor for the best computation efficiency. The simulation length does not apply in Statistical mode.
Target BER
Target bit error rate (BER) is used to calculate the jitter and noise at low BER conditions. If the simulation length is greater than the inverse of the target BER, the link performance is directly assessed and calculated. If the simulation length is shorter than the inverse of the specified target BER, Advanced Link Analyzer uses specific methodology and algorithms to calculate the link performance. The methodology of jitter and noise at low BER can be found in HST Jitter and BER Estimator Tool User Guide for Stratix® IV GT and GX Devices.
Test Pattern
Allows you to specify the test pattern used in the simulation. The following test patterns are available:
-
PRBS-7, PRBS-9, PRBS-11, PRBS-15, PRBS-23,
PRBS-31, and
QPRBS13-CEI
- The PRBS test patterns are generated using Advanced Link Analyzer’s built-in pattern generator.
- If the whole PRBS pattern is shorter than the simulation length, the PRBS pattern is inverted and repeated. The inversion is applied to achieve DC balance of the generated PRBS test pattern.
- If the PRBS patterns are longer than the simulation length, a partial test pattern of the PRBS pattern is used. The default initial condition of PRBS test pattern generation is with logic 1s in all shift registers for the valid PRBS patterns.
- The most commonly used PRBS test patterns are listed in the Test Pattern menu. Other PRBS test pattern can be selected or configured in the Pattern Designer.
-
Pattern Designer—Allows you to specify your own custom test patterns. The following figure shows the Pattern Designer user interface.
Figure 6. Advanced Link Analyzer Pattern DesignerThe Pattern Designer includes the following test pattern generation methods:
-
PRBS—Provides
an extensive list of common PRBS test patterns. You can also specify custom
PRBS polynomials and seeds. The internal linear feedback shift register (LFSR)
engine uses the information to generate the desired test pattern. Other options
include selecting how the test pattern is repeated or extracted when the
simulation length is longer or shorter than the generated test patterns. There
are two options for selecting the partial test patterns:
- Use First Part of Generated PRBS Sequence
- Include Longest Run-Length Bit Sequence—The longest run-length test pattern is located at the ending portion of the test bit sequence.
- Consecutive Bit Patterns—Defines the test patterns with repeating patterns.
- Clock—Generates a clock-like pattern.
- All 1's—Generates an all-ones test pattern that usually feeds into a coder or scrambler.
- All 0's—Generates an all-zeros test pattern that usually feeds into a coder or scrambler.
- Encoder and Scrambler—Advanced Link Analyzer supports the following encoders and scramblers: 8B/10B, 64B/66B, 64B/67B, and 128B/130B.
-
PRBS—Provides
an extensive list of common PRBS test patterns. You can also specify custom
PRBS polynomials and seeds. The internal linear feedback shift register (LFSR)
engine uses the information to generate the desired test pattern. Other options
include selecting how the test pattern is repeated or extracted when the
simulation length is longer or shorter than the generated test patterns. There
are two options for selecting the partial test patterns:
-
Custom—Click the open-file dialog button to select a custom
test pattern file. Figure 7. Custom Test Pattern File Browser Button
The custom pattern files are in the following formats:
- Hexadecimal—Hexadecimal strings start with 0x. For example, a PRBS-7 test pattern can be specified by 0x8cd501fbe7ae1ba62b05e3b64a4272d0. The custom file name must have a .hex extension.
- Binary—Binary strings have a format such as "001000111…". Blank characters and new lines/returns are allowed in the input binary string file. The custom file name must have a .bin extension.
Note: The custom test pattern has a maximum text length of 262,142 characters (about 1M bits with a hexadecimal text format or about 246K bits with a binary text format). Intel recommends that the test pattern string (hexadecimal or binary) is specified in a single row without spaces, especially for long custom test patterns. If a custom test pattern is input with multiple lines of text, the line returns or end-of-line control characters on each line of text are counted as an item or entry by the text parser.
Modulation Scheme
Advanced Link Analyzer support NRZ and PAM4 modulation schemes. Choose PAM4 only when the device supports it.
Forward Error Correction (FEC)
FEC is a coding scheme that encodes the data pattern with additional code words that can help the receiver to recover bit errors. Intel® Arria® 10 and Intel® Stratix® 10 devices support FEC schemes. In Advanced Link Analyzer, the FireCode, Reed-Solomon RS (528, 514), RS (544, 514), and JESD204 FEC models are supported. When FEC is enabled, Advanced Link Analyzer produces additional FEC related results. The default FEC setting is Off.
Reference Clock
You can specify the reference clock that feeds into the transmitter. The supported clock frequencies are shown in MHz. By default, the reference clock is assumed to be ideal without any noise or jitter. You can configure and specify the reference clock characteristics by clicking Reference Clock Option.
The reference clock can be fed to a transmitter with or without enabling a phase-locked loop (PLL) module. When the transmitter PLL is disabled or not present, the reference clock noise and jitter directly affect the serial output signal.
With integer PLLs, Advanced Link Analyzer supports an integer divider ratio between the data rate and the reference clock frequency. If the ratio is not an integer, the reference clock frequency is rounded to the closest integer-divided-ratio frequency. The actual reference clock frequency used in the simulation is displayed in the message box next to the pull-down menu. With fractional-N PLLs, fractional divider ratios are allowed.
In the simulation with specific transmitter devices, such as Intel® Arria® 10 GX/SX/GT, Stratix® V GT, Stratix® V GX, and Arria® V GZ devices, the supported data rate to reference clock divider ratios are limited. If a specific combination of data rate, PLL divider ratio, and reference clock frequency cannot be found, the reference clock used in the simulation can be further adjusted.
The reference clock frequencies listed are commonly used in most serial link protocols. If you cannot find the exact reference clock frequency from the list, you can add your reference clock frequency with the following procedure:
- Close Advanced Link Analyzer.
- Navigate to the Advanced Link Analyzer installation directory. Typically, Advanced Link Analyzer is installed in C:\intelFPGApro\<version number>\adv_link_analyzer\.
- Under the Database folder, find RefCLK_List.jnetxdata.
- Copy RefCLK_List.jnetxdata to your local directory (typically at C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\Database\.
- Edit the file by adding your desired reference clock frequencies.
- Save the change and exit the editor.
- Restart Advanced Link Analyzer.
Reference Clock Option
The reference clock option user interface allows you to configure the characteristics of the reference clock used in the simulation. The reference clock can be specified with the following methods:
-
Ideal Reference Clock—With this setting,
the reference clock is ideal without any noise or jitter. Figure 8. Ideal Reference Clock Setting
-
Option 1: Reference Clock Jitter
Figure 9. Reference Clock Option 1: Reference Clock Jitter
Option 1 configures the reference clock with the following options:
-
Random Jitter— Specify the frequency
range (in ps). Note: Intel recommends that the maximum frequency range (fMAX) of the phase noise be set to the reference clock frequency. If the fMAX is less than the reference clock frequency, Advanced Link Analyzer uses linear extrapolation to calculate the phase noise at fMAX, which can lead to inaccurate results.
-
Periodic Jitter Type—Specify the shape
profile, frequency (in Hz), and amplitude (in ps). The shape profile can be:
- Triangle
- Hershey with programmable Hershey shape parameter
- Sharkfin with programmable Sharkfin shape parameter
- Sinusoidal
-
Spurs—Specify clock spectrum spurs with
individual frequency (in Hz) and amplitude (in dBc). For example, if the
reference clock has three spurs: –110 dBc at 100
kHz,
–90 dBc at 1 MHz, and –80 dBc at 10 MHz, you can input the following text into
the Spurs text box:
100e3 -110 1e6 -90 10e6 -80
-
Spur
Phase Offset
Use the Spur Phase Offset pull-down menu to configure the initial phase of spur noises. The options are:
- Auto—Advanced Link Analyzer automatically selects the default initial spur noise phase. The default initial spur phase is 0 rad.
- Random—Advanced Link Analyzer randomly sets the initial spur noise phases.
- Zero—Advanced Link Analyzer sets the initial spur noise phase to 0 rad.
-
Specified—You can manually specify the initial spur phase
individually by adding the phase value after the amplitude value. The following
example shows the initial spur noise phases are 1.0, 2.0, and 3.0 rad.
100e3 -110 1.0 1e6 -90 2.0 10e6 -80 3.0
-
Option 2: Phase Noise
Figure 10. Reference Clock Option 2: Phase Noise
Option 2 configures the reference clock with the following options:
-
Phase Noise—Specify reference clock
jitter using a phase noise profile. Reference clock phase noise is specified
with the noise power spectrum described with frequency and amplitude. The above
figure demonstrates a phase noise profile with a measured reference clock phase
noise data set. Note: Intel recommends that the maximum frequency range (fMAX) of the phase noise be set to the reference clock frequency. If the fMAX is less than the reference clock frequency, Advanced Link Analyzer uses linear extrapolation to calculate the phase noise at fMAX, which can lead to inaccurate results.
-
Spurs—Specify clock spectrum spurs with
individual frequency (in Hz) and amplitude (in dBc). For example, if the
reference clock has three spurs: –80 dBc at 100
kHz,
–90 dBc at 1 MHz, and –96 dBc at 10 MHz, you can input the following text into
the text box:
100e3 -80 1e6 -90 10e6 -96
- Spur Phase Offset—Same as in Option 1 Reference Clock Jitter.
- Periodic Jitter Type—Same as in Option 1 Reference Clock Jitter.
- Plot / Update Plot—You can plot the input phase noise and spurs in the plotting area and confirm the reference clock characteristics.
Link Optimization Method
Advanced Link Analyzer can find optimal transmitter and receiver equalization settings with a user-specified link configuration.
Transmitter Mode |
Receiver Mode |
Notes |
---|---|---|
Manual |
Manual |
Both TX and RX equalizations are manually set. |
Auto / Auto with Manual Starting Point |
Manual |
Advanced Link Analyzer finds optimal TX equalization setting. RX EQ setting is manually set. |
Manual |
Auto |
TX EQ is manually set. Advanced Link Analyzer finds optimal RX EQ setting. |
Auto / Auto with Manual Starting Point |
Auto |
Advanced Link Analyzer finds both TX and RX EQ settings. |
Advanced Link Analyzer has four link optimization methods for finding the optimal link setting, such as a transmitter pre-emphasis and receiver CTLE and DFE with a given link configuration.
- FIR=>CTLE=>DFE— (default) Optimizes the link performance by finding the optimal transmitter setting, receiver equalization setting, or both. This method prioritizes the transmitter equalization, such as pre-emphasis, de-emphasis, or FIR-based, over receiver equalization schemes. However, the optimization algorithm is also capable of detecting and utilizing optimal receiver equalization. In practice, this usually implies that most of the "heavy-lifting" in channel compensation is performed by the transmitter equalization.
- FIR=>CTLE+DFE—Extends the FIR=>CTLE=>DFE method by enabling RX DFE (Decision Feedback Equalizer) when RX optimization is performed. This method exploits DFE capabilities by possibly reducing the channel compensation from CTLE (depending on the channel characteristics).
- CTLE=>FIR=>DFE—Prioritizes the receiver's CTLE capability over the transmitter's equalization. Most of the channel compensation is performed by the receiver's CTLE while the TX equalization provides additional compensation if needed. RX DFE is adapted in the final stage. This method is supported in non-IBIS-AMI devices. For Intel transmitters, you can manually set initial TX FIR configurations so the link optimizations can yield better solutions with shorter simulation time when the initial conditions are proper.
- CTLE=>FIR+DFE—Extends the CTLE= FIR=>DFE method by joint-optimizing TX pre-emphasis/FIR and RX DFE. This method allows co-optimization between the TX FIR and RX DFE. For Intel transmitters, you can manually set the initial TX FIR configurations so the link optimizations can yield better solutions more quickly when the initial conditions are proper.
- CTLE=>FIR=>CTLE=>DFE—Extends the CTLE=>FIR=>DFE method by performing an additional CTLE adaptation stage after FIR setting is found.
- CTLE=>FIR+DFE=>CTLE+DFE—Extends the CTLE=>FIR+DFE method by performing an additional CTLE+DFE adaptation stage.
- ALA-COM—COM (Channel Operating Margin) based joint link optimization method. This is a beta feature in 21.1 that supports Custom and Intel® Agilex™ transceiver models only.
Use the following guidelines for choosing the best link optimization method:
- FIR=>CTLE=>DFE is a good choice for most applications or channels for time efficient link optimizations. It is the default link optimization method in Advanced Link Analyzer.
- For heavy insertion loss channels such as when insertion loss > 25 dB at Nyquist frequency, FIR=>CTLE=>DFE provides good coverage.
- For strong impedance discontinuities, CTLE=>FIR=>DFE and CTLE=>FIR=> CTLE=>DFE methods provide better performance in general.
- For large crosstalk noises, choose FIR=>CTLE+DFE for high loss channels or CTLE=>FIR+DFE and CTLE=>FIR+DFE=>CTLE+DFE for moderate loss applications.
Notes:
- Advanced Link Analyzer supports link optimization for selected IBIS-AMI models for the link optimization modes and the methods shown above. Refer to the IBIS-AMI model support sections for details.
- For a transmitter equalization sweep simulation, Advanced Link Analyzer provides batch simulation capability using the Advanced Link Analyzer Batch Simulation Controller tool. Refer to the Advanced Link Analyzer Batch Simulation Controller section for details.
FOM of Link Optimization
Use this menu to select the figure of merit (FOM) for optimizing the serial link. There are three options: Area, Width, and Height. The signal conditioning mechanisms, which include transmitter pre-emphasis, de-emphasis, and receiver equalizers, use these selections to optimize the waveform so that it has the best eye diagram opening in terms of area, width, or height.
Compliance Mask
Advanced Link Analyzer plots link compliance eye diagram masks after the simulations are completed. Use a compliance mask to examine whether the waveform or eye diagram meets the receiver's requirements at certain conditions (such as BER target). PCI Express* 8GT/16GT and selected devices’ receiver eye masks are provided.
Eye Diagram Mask Designer
Advanced Link Analyzer supports custom eye diagram mask definitions at various locations within a link. When the Eye Diagram Mask Designer option is selected, the custom eye diagram mask configuration window opens. You can then specify the dimension of the eye diagram mask. The custom eye diagram mask is used in the simulation. Two eye diagram mask types are supported. Four different eye diagram masks cane be specified for transmitter output, channel output, receiver CTLE output, and link/receiver output. Each eye diagram mask can be individually configured and enabled.


A custom eye diagram mask can be saved and loaded for future use.
Project Name
Project Name is a user-defined name for the current task/project. Currently, the session name is the saved user configuration file name when the simulation configuration is saved.
Notes:
- The simulation results are automatically written to a directory with the same project name.
- The location of the output
directory can be configured as one of the following:
- The same location as the project configuration file (.jne/.jneschm) (this is the default).
- A location you specify in the System options. Refer to the System Options section for details.
- Intel® recommends that there should be no space (or bland) characters in the project name.
Simulation Mode
Advanced Link Analyzer provides three simulation modes (statistical, full waveform, and hybrid) to meet your simulation and link analysis preferences and needs. Hybrid mode is the default.
Statistical Mode |
Full Waveform Mode |
Hybrid Mode (Default) |
|
---|---|---|---|
Simulation Method |
Statistical Method |
Time-domain Method |
Time-domain and Statistical Methods |
Jitter Injection and Simulation |
Statistical Domain (PDF-based) |
Time Domain |
Mixed Domain (Time Domain and PDF-based) |
Noise Injection and Simulation |
Statistical Domain (PDF-based) |
Time Domain |
Mixed Domain (Time Domain and PDF-based) |
Simulation Speed (to meet your specified BER target) |
Fast |
Slow |
Optimal |
Accuracy |
Lower |
Best |
Optimal |
Recommended Simulation Length |
N/A (You do not need to specify simulation length in statistical mode.) |
>1,000,000 bits |
60,000-1,000,000 bits |
Further information and comparisons among the three simulation modes can be found in the following papers:
- Comparison of Two Statistical Methods for High-Speed Serial Link Simulation by M. Shimanouchi, M. Li, and H. Wu. DesignCon, 2013, Santa Clara, CA.
- Advancements in High-Speed Link Modeling and Simulation by M. Li, M. Shimanouchi, and H. Wu. IEEE Custom Integrated Circuits Conference, 2013.
- High-Speed Link Simulation Strategy for Meeting Ultra Long Data Pattern under Low BER Requirements by H. Wu, M. Shimanouchi, and M. Li, DesignCon, 2014, Santa Clara, CA.
Output Options
- Data Viewer—When simulation is complete, a new Advanced Link Analyzer Data Viewer opens and the results are shown. The simulation results can be loaded and viewed at a later time with Advanced Link Analyzer Data Viewer.
- Data Viewer with Image Output—When simulation is complete, all the simulation results are also saved as image files that can be used in documentation. Advanced Link Analyzer supports three image output options: PNG, JPEG, and GIF. The saved images are located in the same directory as the simulation results for each project.
Test Point Options
Advanced Link Analyzer provides the following default test point options:
-
Data Latch Only—Simulation results at
the data latch
are
saved and displayed. Data latch can be at DFE output, CTLE
output, or
the
input stage of
the
receiver depending on the link or device configuration. Custom
test points
and
simulation
results at test points
are
not
shown.
Note: For simulation length longer that 1 million bits, it is suggested to use Data Latch Only mode to reduce overall simulation time.
-
TX/Channel/CTLE-/DFE-Latch—Advanced Link Analyzer
automatically sets up to four test points for the link:
- Transmitter output—(default option) If a transmitter package model is present (for example, the package model is embedded, as in Intel devices and PCI Express* 8GT) or external (for example, using the "Custom" package option), the output appears after the package model. If no package model is present, the output appears at the transmitter output.
- Channel output—The second test point is at the end of channels.
- CTLE output—If you enable the receiver CTLE, the third test point is at the output of the CTLE.
- DFE output—The fourth test point is at the output of the receiver DFE.
Note: Custom test points are neglected with this test point option. - Custom Test Point and Data Latch—Advanced Link Analyzer plots the output at custom test points and the final data latch point.
Probe Type
Advanced Link Analyzer provides two type of probes:
- Ideal—With an ideal probe, the waveform, signal, or eye diagram is plotted by assuming that the link is terminated with an ideal 50 ohms termination at the probe location.
- High-Impedance—With a high-impedance probe, the waveform, signal, or eye diagram is plotted by emulating a high-impedance probe sensing the probe location.
Jitter Analysis Options
Advanced Link Analyzer can perform jitter decomposition and analysis on a waveform at specified test points. The jitter analysis feature is in the beta testing stage in the current Advanced Link Analyzer version.
- Disable—Jitter analysis is disabled.
- Jitter Component—Using proprietary algorithms, Advanced Link Analyzer performs a series of spectrum and probability density function (PDF) analyses on the time-interval-error (TIE) record of the simulated waveforms. The jitter decomposition algorithms extract various jitter components as shown in the following figure.

The jitter decomposition process (conceptual) is shown in the following figure.

The following jitter components are extracted and reported:
- PJ—Periodic jitter (peak-peak)
- DCD—Duty cycle distortion (peak-peak)
- ISI—Inter-symbol interference (peak-peak)
- BUJ—Bounded uncorrelated jitter (peak-peak)
- RJ-RMS—Random jitter (RMS)
2.1.3. Transmitter Setting
The transmitter generates signals based on the transmitter clock and test pattern conditions.

Transmitter
The following transmitter types are supported:
- Stratix® V GX
- Stratix® V GT
- Intel® Stratix® 10 L-tile
- Intel® Stratix® 10 H-tile
- Intel® Stratix® 10 E-tile (wrapper support)
- Intel® Stratix® 10 P-tile (wrapper support)
- Intel® Agilex™ E-tile (wrapper support)
- Intel® Agilex™ P-tile (wrapper support)
- Intel® Agilex™ R-tile (wrapper support)
- Intel® Agilex™ F-tile general-purpose transceiver block (wrapper support)
- Intel® Agilex™ F-tile high-speed transceiver block (wrapper support)
- Arria® V GZ
- Intel® Arria® 10 GX/SX
- Intel® Arria® 10 GT
- Intel® Cyclone® 10 GX
- IBIS-AMI
- Custom
- PCI Express* 8 GT
- PCI Express* 16 GT
- PCI Express* 32 GT
The transmitter type determines what other transmitter settings you can select. When a transmitter is chosen, it is automatically inserted into the Link Designer, ready to connect to other link components.
Package
Select a package type for the transmitter device. For Intel products and IBIS-AMI models, the package models are included in the device models. For Custom devices, the package model is specified in the channel setting. When you select the Custom package type (for any transmitter devices), the embedded package model (if available) is disabled. You can then add a channel component (such as an S-parameter) with type Package in the Link Designer workspace. The Custom package model must be placed next to the transmitter module so it can be simulated and analyzed correctly. If you choose the Custom package type but do not add a channel component with Package type to the Link Designer workspace, the transmitter is simulated without any package model.
Selecting Package Designer from the Package pull-down menu opens the Transmitter Package Designer for you to design or customize package models.

Advanced Link Analyzer’s Package Designer supports three package model generation methods. You can use the Package Designer Method pull-down menu to select one of following:
- IEEE 802.3 cd/bj COM: With this method, a package model is generated using the IEEE 802.3 50 Gbps Ethernet (802.3cd/bj is the task group name) Channel Operating Margin (COM) reference package modeling method. You can configure die capacitance, package material characteristics and length, and PCB bump. Refer to IEEE 802.3 Annex 92 for details.
- IEEE 802.3 ck COM: With this method, a package model is generated using the IEEE 802.3ck (task group for 100 Gbps Ethernet) COM reference package modeling method (shown in above figure). You can configure die capacitance, die termination network, die bump, package material characteristics and length, package vertical transition (for example, via) material characteristics and length, and PCB bump. Refer to IEEE 802.3 Annex 92 and 802.3ck for details.
Custom S-parameter: With this method, you can specify an S-parameter to represent the package model.
Advanced Link Analyzer comes with the following transmitter package models:
- Stratix® V GX
- Stratix® V GT
- Arria® V GZ
-
Intel® Arria® 10 GX/SX
Options: Additional package models (shown in the following figure) are available for Intel® Arria® 10 devices. The package model is specified as its trace length inside the package. These models are chosen to cover the range of package trace lengths in Intel® Arria® 10 transceiver transmitters.
- Default—The default package model is the same as the 14 mm option
- 14mm
- 16.5mm
- 20mm
- 24mm
Contact My Intel support representative if you want to know how to pair your design with the Intel® Arria® 10 package model options.
Figure 17. Intel® Arria® 10 Transmitter Package Options
- Intel® Stratix® 10 L-tile—Typical, Minimum, and Maximum package models are provided
- Intel® Arria® 10 GT—Same options as Intel® Arria® 10 GX/SX
- PCI Express* 8 GT
- PCI Express* 16 GT (place holder only; use custom package model for simulations)
- PCI Express* 32 GT
- Intel® Stratix® 10 H-tile— Same options as Intel® Stratix® 10 L-tile
- Intel® Stratix® 10 E-tile— Same options as Intel® Stratix® 10 L-tile
- Intel® Cyclone® 10 GX—Typical, Minimum, and Maximum package models are provided
VOD Selection
Select the VOD (differential output voltage) for the transmitter. VOD selections can be either by voltage level or by index, depending on the transmitter selected. For supported devices, the target VOD value is displayed in the Transmitter tab page. The VOD value depends on the device type, supply voltage, and PVT.
Slew Rate
Select the transmitter output signal slew rate. Slew rate options are available for selected devices. For details, refer to the associated transceiver user guides.
Pre-Emphasis
Select or specify the transmitter pre-emphasis, de-emphasis, or TX-FIR configuration in one of the following modes:
- Auto—Advanced Link Analyzer uses its link optimization algorithm to find the optimal transmitter FIR settings.
- Auto with Manual Starting Point—Specify the initial TX pre-emphasis or FIR configuration. Advanced Link Analyzer’s link optimization engine uses the TX settings as initial conditions.
- Manual—For non-Intel devices, you can manually input the tap coefficients. For Intel devices, select individual FIR levels from the menus for each FIR tap. The FIR selection for Intel devices is VOD dependent. Therefore, changing the VOD or device type can reset the TX FIR menu contents. For a generic transmitter type, a set of typical FIR coefficients is included in the pull-down menu.
- Off
When you select the Intel® Agilex™ F-tile high-speed transceiver with wrapper support enabled, the transmitter GUI is capable of translating between high-speed transmitter’s FIR settings and register settings, which are used in the Intel® Quartus® Prime software.

Estimated TX EQ AC Gain
Select pre-tap and post-tap values to estimate the AC gain in dB scale. The TX EQ AC gain is calculated as the gain between the DC (0 Hz) and the Nyquist frequency of the link. This gain assumes a FIR type of transmitter pre-emphasis scheme and an ideal transmitter output waveform.
PLL Type and Bandwidth
Select the type and bandwidth of the PLL used in the transmitter to generate the transmitter clock.
- Ideal Clock—The default PLL setting. The PLL is disabled and the clock is passed from the external reference clock.
- For
Intel transmitters, PLL models and configurations
are automatically set based on the following settings:
- Data rate
- Reference clock frequency
- Oscillator type:
- Stratix® V GX and Arria® V GZ—ATX (LC) or CMU
- Stratix® V GT—ATX (LC)
- Intel® Arria® 10 GX/SX/GT—ATX (LC), Fractional PLL, or CMU
- Intel® Stratix® 10 10 L-tile/H-tile/E-tile—ATX (LC), Fractional PLL, or CMU
- Intel® Cyclone® 10 GX— ATX (LC), Fractional PLL, or CMU
- PLL bandwidth
- Intel transmitter PLL configurations such as internal divider ratios
Intel recommends that you follow Intel’s reference clock selection and PLL configurations recommendations when setting up the transmitter PLL. Without following the reference clock and PLL guidelines, you might operate and simulate an unstable PLL and see unexpected results.
- For Custom transmitters, PLL models and configuration are set automatically based on settings similar to that of Intel PLLs while more comprehensive PLL configuration capabilities are under development. With custom transmitters, the VCO can be either LC type or ring oscillator (Ring) type. More PLL to reference clock divider ratios are supported in the custom PLL type. Follow Intel's PLL and reference clock guidelines when setting up transmitter PLLs to avoid unexpected results.
- PLL is currently not supported for native IBIS-AMI transmitters.
Supply Voltage
For supported devices, you can choose the supply voltage.
- 0.95 V ( Intel® Arria® 10 GX/SX/GT)
- 1.03 V ( Intel® Arria® 10 GX/SX/GT)
- 1.12 V ( Intel® Arria® 10 GT)
- 1.03 V
- 1.12 V
- 1.03 V
- 1.12 V
- 0.95 V
- 1.03 V
Vcm
Vcm is the common voltage of the transmitted signal.
Scope Option
Advanced Link Analyzer has four options for TX output scope emulation:
- Default
- BW = Data Rate / 1667 (default value)
- BW = 4 MHz
- Disable
PVT
Select the process, voltage, and temperature (PVT) models for the selected transmitter device. PVT model support varies depending on device type, device data availability, and model coverage. A message is shown on the Transmitter tab page to indicate the PVT model coverage. Transmitter PVT model coverage and conditions are shown in the following table.
Transmitter Type | Waveform PVT Model | Jitter/Noise PVT Model |
---|---|---|
Stratix® V GX | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: –40°C to 100°C |
Arria® V GZ | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: –40°C to 100°C |
Stratix® V GT | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: 0°C to 100°C |
Intel® Arria® 10 GX/SX | Typical/Fast/Slow | Slow |
Intel® Arria® 10 GT | Typical/Fast/Slow | Slow |
Intel® Stratix® 10 L-tile | Typical/Fast/Slow | Slow |
Intel® Stratix® 10 H-tile | Typical/Fast/Slow | Slow |
Intel® Cyclone® 10 GX | Typical/Fast/Slow | Slow |
Wrapper-supported Intel IBIS-AMI Models | Provide by IBIS-AMI model | Provide by IBIS-AMI model |
IBIS-AMI | Provide by IBIS-AMI model | Provide by IBIS-AMI model |
Custom | None | None |
PCI Express* 8GT | None | None |
PCI Express* 16GT | None | None |
Temp Range
For Intel® Arria® 10, the device model have temperature range dependency. The temperature range for Industrial is -40 °C to 100 °C, 0 °C tp 105 °C for Extended, and -40 °C to 125 °C for Military. The default setting is Industrial temperature range. Refer to the device's data sheet for the supported temperature range; values in the datasheet take precedence over the values in this document.
Advanced Link Analyzer to Intel® Quartus® Prime Parameter Translation for Intel® Arria® 10 GX/SX/GT Transmitters
The following table provides a translation from Advanced Link Analyzer Intel® Arria® 10 GX/SX/GT transmitter parameter names to the equivalent Intel® Quartus® Prime parameter names. Use the Intel® Quartus® Prime software to transfer optimum device settings from a Advanced Link Analyzer simulation to an actual device configuration.
Advanced Link Analyzer Name | Intel® Quartus® Prime Name |
---|---|
Vod Selection | Transmitter Output Swing Level |
Post-Tap 1 1 | Transmitter Pre-Emphasis First Post-Tap Magnitude |
Post-Tap 2 1 | Transmitter Pre-Emphasis Second Post-Tap Magnitude |
Pre-Tap 1 1 | Transmitter Pre-Emphasis First Pre-Tap Magnitude |
Pre-Tap 2 1 | Transmitter Pre-Emphasis Second Pre-Tap Magnitude |
Sign of Post-Tap 1 1 | Transmitter Pre-Emphasis First Post-Tap Polarity 2 |
Sign of Post-Tap 2 1 | Transmitter Pre-Emphasis Second Post-Tap Polarity 2 |
Sign of Pre-Tap 1 1 | Transmitter Pre-Emphasis First Pre-Tap Polarity 2 |
Sign of Pre-Tap 2 1 | Transmitter Pre-Emphasis Second Pre-Tap Polarity 2 |
PLL Type
|
Intel®
Quartus® Prime PLL Type
|
Slew Rate | XCVR_A10_TX_SLEW_RATE_CTRL |
PLL Bandwidth | Bandwidth in PLL Configuration Options in selected PLL type |
2.1.3.1. Jitter/Noise Component
The following figure shows the jitter decomposition diagram and the breakdown of jitter components.

Name |
Description |
Unit |
Support in Advanced Link Analyzer |
Comments |
---|---|---|---|---|
DJ |
Deterministic Jitter |
Unit Interval (UI) |
Yes |
DJ can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. Select the DJ generation method in the Transmitter Jitter/Noise Options Window. The default DJ method is dual-Dirac. DJ consists of periodic jitter, bounded uncorrelated jitter, inter-symbol interference, and duty-cycle distortion. The DJ value is used in the simulation when the DJ/RJ-DN/RN method is selected. |
ISI |
Inter-Symbol Interference |
UI |
Yes |
ISI can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. Select the ISI generation method in the Transmitter Jitter/Noise Options Window. The default ISI method is dual-Dirac. |
DCD |
Duty Cycle Distortion |
UI |
Yes |
The DCD parameter models two types of jitter: Positive pulse width jitter (PPWJ) and Clock DCD. The PPWJ shortens or lengthens the logic 1 waveform. The Clock DCD emulates distorted clock waveform effects on the transmitter output waveform. You can select the DCD generation method in the Transmitter Jitter/Noise Options Window. The default DCD method is PPWJ – (shortened positive waveform). |
BUJ |
Bounded Uncorrelated Jitter |
UI |
Yes |
Same as Deterministic Jitter. The default BUJ method is Uniform distribution. |
RJ |
Random Jitter |
UI-RMS or ps-RMS |
Yes |
RJ is assumed to be Gaussian. RJ can be specified in either pico-second (ps-RMS) or UI-RMS. |
SJ |
Sinusoidal Jitter |
Amplitude: UI Frequency: MHz |
Yes |
Sinusoidal jitter can be specified with amplitude and frequency. |
DN |
Deterministic Noise |
mV |
Yes |
DN can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DN generation method in the Transmitter Jitter/Noise Options Window. The default DN method is uniform. |
BUN |
Bound Uncorrelated Noise |
mV |
Yes |
Same as DN. The default method is Truncated Gaussian method with a Peak-to-RMS ratio of 14. You can select the BUN generation method and parameters in the Transmitter Jitter/Noise Options Window. |
RN |
Random Noise |
mV-RMS |
Yes |
RN is assumed to be Gaussian. |
Jitter PDF |
Jitter Probability Density Function (PDF) |
Jitter amplitude, Probability (Jitter amplitude can be in absolute time or UI (unit interval) unit) |
Yes |
Jitter PDF defines the jitter probability density function. The input format is jitter amplitude in second and probability. The following is a jitter PDF example: -5e-12 1e-10 -4e-12 3e-7 -3e-12 1e-4 -2e-12 1e-2 -1e-12 0.29 0 0.4 1e-12 0.29 2e-12 1e-2 3e-12 1e-4 4e-12 3e-7 5e-12 1e-10 |
Noise PDF |
Noise Probability Density Function |
Noise amplitude, Probability |
Yes |
Noise PDF defines the noise probability density function. The input format is Noise amplitude in volt and probability. The following is a noise PDF example: -50e-3 1e-10 -40e-3 3e-7 -30e-3 1e-4 -20e-3 1e-2 -10e-3 0.29 0 0.4 10e-3 0.29 20e-3 1e-2 30e-3 1e-4 40e-3 3e-7 50e-3 1e-10 |
CMN |
Common Mode Noise |
mV-rms |
Yes |
It injects common noise into the link. User can specify the location of the noise injection either after the package or after the die. |
Click Jitter/Noise Options to further configure each jitter and noise type. There are two jitter/noise modes for Advanced Link Analyzer’s transmitters: Jitter/Noise Component mode and DJ/RJ-DN/RJ mode. Only one jitter/noise mode is active at a time and you must determine which mode to use in your simulations.
-
Jitter/Noise Component mode—Advanced Link Analyzer uses a flat jitter/noise structure that assumes
no overlapping among all the jitter and noise components. Avoid double counting
when inputting or importing jitter/noise figures. In the following figure, there
are six specific jitter components: DCD, ISI, SJ, BUJ, RJ, and jitter PDF. The
noise components DN, BUN, RN, and noise PDF must also be specified separately.
Figure 20. Specifying Transmitter Jitter and Noise in Jitter/Noise ModeFigure 21. Transmitter Jitter/Noise Configuration in Jitter/Noise Component Mode
-
DJ/RJ-DN/RJ mode—All deterministic jitter/noise
components are included in DJ and DN. Figure 22. Specifying Transmitter Jitter and Noise in DJ/RJ-DN/RJ ModeFigure 23. Transmitter Jitter/Noise Configuration in DJ/RJ-DN/RJ Method
2.1.3.2. Transmitter Options
Termination tab
This section specifies the transmitter impedance.

For selected Intel devices, use the TX Impedance pull-down menu to select a termination configuration. You can also customize the termination configuration by selecting the Custom option. When the Custom TX Impedance method is chosen, the termination can be configured as follows:
- Ideal TX termination—The transmitter is ideal with a 50 ohms (single-ended) termination.
-
Non-ideal TX termination—Select one of
the following options:
- R—Transmitter impedance is modeled as a resistance R ohms (single-ended).
- R//C1—Transmitter impedance is modeled as an RC network with a parallel resistor (in ohms) and a capacitance (in pF).
- File Input (Frequency Real Imaginary)—Transmitter impedance is modeled by a frequency-dependent complex impedance table described in the input file.
For an Intel transmitter, the default termination configurations are automatically selected and specified.
Pulse Shaping tab
Advanced Link Analyzer supports three pulse shaping methods for Custom transmitters:
- Edge Rate—A pulse-shaping filter is generated by using a Gaussian low-pass filter that matches the specified edge rate.
- Rise/Fall Time —A pulse shaping filter is generated by using a Gaussian low-pass filter that matches the specified 20%-80% rise/fall time.
- S-parameter—A pulse-shaping filter is specified by your S-parameter file. Only the differential insertion loss (for example, Sdd21), is applied in the pulse shaping.
- For standards-based transmitters, for example, PCI Express* 8GT/16GT, pulse shaping types and configurations are set by the transmitter model and, hence, cannot be changed. You can override the default standards-based transmitter model setting by turning on Override generic/standard device setting.

PAM-n Options
- PAM-n Codec Method— Select PAM-n coder/decoder method. The selections are Default, Gray, and Linear. The default setting is Gray coding.
- PAM-n Gray Coding Option— Select Gray coding options. Selections are Default, MSB first, and LSB first. The default setting is MSB first.
- PAM-n TX Linearity— Set the linearity of PAM-n output waveform. PAM-n linearity means mismatch between amplitude levels. The default value is 1.0. The PAM-n TX linearity is defined in the same way as specified in IEEE 802.3 PAM-4 transmitter linearity (RLM).
FIR / Pre-emphasis tab
Specify the length of the TX FIR and the location of the main cursor tap. This setting is only valid for the Custom transmitter type.
When Custom TX is selected, TX FIR configuration table is displayed. You can configure the range of TX FIR coefficients to be used in the TX EQ optimization process.

TX Analysis
- TX FIR Fitting— TX FIR Fitting measures the effective transmitter equalization approximated by FIR (finite impulse response) coefficients. The selections are Default, IEEE 802.3bj/CEI-25G-LR, CEI-56G-MR, Custom, and Disable. The default setting is Disable.
- TX SNDR— TX SNDR measures the signal-to-distortion-and-noise ratio of transmitter output. The selections are Default, IEEE 802.3bj/CEI-25G-LR, CEI-56G-MR, Custom, and Disable. The default setting is Disable.
- Enforce Fitting Length— This setting is in effect when custom TX FIR Fitting is selected. The selections are Default, Enable, and Disable. When Enable is selected, the fitting algorithm ignores the transmitter configuration and performs the FIR fitting per the tap-length specified in the Fitting Length and Fitting Pre-cursor Length settings. When Disable is selected, the FIR fitting uses the transmitter's FIR configuration to perform the fitting calculation. The default setting is Enable.
- Fitting Length— TX FIR fitting length.
- Fitting Pre-cursor Length— TX FIR fitting pre-cursor tap length.

PLL tab
Use this panel to set the custom PLL divider ratio. This panel provides an alternative to Advanced Link Analyzer’s automatic divider ratio configuration. For example, Intel transmitters provide three programmable dividers: L, M, and N. You can set the divider ratio manually. Refer to Intel transceiver documentation for PLL setting recommendations.

Options tab and Die Model tab
Reserved. These tabs are blank.
2.1.3.3. Characterization Data Access
Use the following guidelines for characterization data access:
- When Stratix® V GX, Stratix® V GT, Arria® V GZ, Intel® Arria® 10 GX/SX/GT, Intel® Stratix® 10 L-Tile/H-Tile/E-Tile/P-Tile, or Intel® Agilex™ E-Tile/P-Tile is selected, the Characterization Data Access button appears and you can include the transmitter jitter parameters in the simulation.
- Characterization Data Access covers PVT variations. You can select appropriate process, voltage, and temperature conditions that best match the desired operation conditions.
- After clicking the
button, Characterization Data Access configures Advanced Link Analyzer to use the characterization data by:
- Selecting Jitter/Noise Component Mode for characterization data entries
- Turning on Jitter/Noise Data Lock
- Importing
device characterization data based on the jitter unit selection
- RJ—Unit selection can be UI (RMS) or ps (RMS)
- Other Jitter—Unit selection can be UI (pk-pk), UI (pk), ps (pk-pk), or ps (pk)
These actions inform the Advanced Link Analyzer simulation engine to use the characterization data from the database.
- The characterization data is displayed in the text box for reference purposes. The Advanced Link Analyzer simulation engine uses proprietary algorithms to accurately model the jitter and noise in the simulations.
- You can unlock the jitter and noise contents by turning off Jitter/Noise Data Lock. However, the jitter and noise models and values can be different from those when Jitter/Noise Data Lock is turned on.
- Characterization Data Access is supported when the data rate is in the following range:
- Stratix® V GX: 5 Gbps to 14.1 Gbps
- Stratix® V GT: 19.6 Gbps to 28.1 Gbps
- Intel® Stratix® 10 L-tile: 3 Gbps to maximum data rate specified in the data sheet (Typical PVT only)
- Arria® V GZ: 5 Gbps to 14.1 Gbps
- Intel® Arria® 10 GX/SX: 3 Gbps to 17.4 Gbps
- Intel® Arria® 10 GT: 3 Gbps to maximum data rate specified in the data sheet
- Intel® Stratix® 10 L-tile: As per Intel® Stratix® 10 L-tile specifications
- Intel® Stratix® 10 H-tile: As per Intel® Stratix® 10 H-tile specifications
- Intel® Stratix® 10 E-tile: As per Intel® Stratix® 10 E-tile specifications
- Intel® Stratix® 10 P-tile: As per Intel® Stratix® 10 P-tile specifications
- Intel® Agilex™ E-tile: As per Intel® Agilex™ E-tile specifications
- Intel® Agilex™ P-tile: As per Intel® Agilex™ P-tile specifications
- Intel® Agilex™ R-tile: As per Intel® Agilex™ R-tile specifications
- Intel® Agilex™ F-tile: As per Intel® Agilex™ F-tile specifications
- After changing the link and device configurations, such as data rate, VOD, PLL type and bandwidth, and PVT condition, you must update the jitter value by clicking Characterization Data Access.
- When
Jitter/Noise Data Lock
is
turned on, Advanced Link Analyzer examines whether the jitter data matches the
simulation configuration during the following conditions:
- Start simulation
- Save link configuration
- In batch simulation mode, jitter data is retrieved and calculated based on the link configuration
When the link configuration exceeds the supporting range of Characterization Data Access, a warning message (conditions 1 and 2) is shown and jitter is reset (all conditions).


2.1.3.4. IBIS-AMI Transmitter Configuration

-
Package—Package models are required in
all IBIS models. Advanced Link Analyzer includes the IBIS package model in the simulation by
default. You can choose other package models by changing the Package selection
to Custom and specifying the external
package model (Channel type Package) as a
channel component. Note: Make sure there is only one package model for the IBIS-AMI transmitter. Use either package type IBIS-AMI or package type Custom with external package model in the schematic. Simulation errors may occur if you have more than one transmitter package model in the link.
-
IBIS Files—Click the file open button
next to the IBIS File text box to select an IBIS model file. Advanced Link Analyzer scans through
the IBIS file and allocates all available transmitter components and models. If
Advanced Link Analyzer encounters the following issues in opening or interpreting the IBIS-AMI
model, a warning message is displayed.
- No transmitter component or model can be located.
- The DLL for the computer platform cannot be located. The IBIS-AMI model is platform dependent. For example, a 32-bit DLL is required to simulate in a 32-bit link simulator and a 64-bit DLL is required to simulate in a 64-bit simulator. A 32-bit DLL cannot simulate in a 64-bit DLL simulator.
- The DLL occupies too much memory and Advanced Link Analyzer was not able to load it. However, Advanced Link Analyzer might be able to run the simulation with such a DLL because of memory allocation differences in the Advanced Link Analyzer GUI and the simulation engine.
- Component—Select an IBIS component from the IBIS model.
-
IBIS tab—The IBIS tab shows the following
configuration parameters:
- Model—Select a device model within a component of an IBIS model.
- Model Selector—Select a model from the model selector list.
- Corner—Select the corner type of a device model. The choices are Typ, Min, and Max.
-
AMI File—Shows the AMI file
specified in the IBIS model. Note: Advanced Link Analyzer currently only supports device models with AMI modeling components.
- DLL File—Shows the DLL file specified in the IBIS model.
- Use External Termination—Indicates that an external termination is used in the simulation. The external termination (single-ended) is specified in the text box on the right. The default setting is not using external termination and the default external termination (if applicable) is 50 ohms (single-ended).
- Use Rising/Falling Waveform—If rising/falling waveforms are available in the IBIS model, the rising/falling waveforms are used to model the transmitter by default. If you turn off this option, ramp data (in the IBIS model) is used in the simulation.
-
Automatic Jitter/Noise
Update—Allows automatic jitter/noise updates from the
IBIS-AMI model (available for models which are compliant with IBIS-AMI
6.0 and later).Note: If you experience unexpected long delay when loading an IBIS-AMI model, you can disable the Automatic Jitter/Noise Update by turning it off. It was seen that certain IBIS-AMI models perform computation-intensive functions (such as equalization adaptation) during the jitter/noise retrieval. You can still retrieve jitter/noise numbers by manually clicking the Manual Jitter/Noise Update button.
- Manual Jitter/Noise Update—When the Automatic Jitter/Noise Update option is disabled, turning on this option allows you to manually update the jitter/noise figures from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later).
- DLL_Path—Specify a folder or path name where the supporting files of an IBIS-AMI model are stored. Refer to the IBIS standards for details.
AMI tab
The AMI tab shows the following AMI configuration parameters.

- Model Name—IBIS-AMI model name
-
Reserved Parameters:
- The IBIS-AMI reserved parameters are shown. The reserved parameters are meant for the Advanced Link Analyzer simulation configuration.
- IBIS-AMI Rev
5.0 and 6.0 jitter parameters (Tx_Jitter) are extracted and
automatically set in the Transmitter's Jitter/Noise window with the
interpretation shown in the following table:
Table 9. IBIS-AMI Jitter Parameters IBIS-AMI Tx_Jitter Parameter
Advanced Link Analyzer Interpretation
(Tx_Jitter (Usage Info)(Type Float)
(Format Gaussian <mean> <sigma>))
DJ = <mean> UI (pk) or ps (pk). Uniform distribution
RJ = <sigma> UI (RMS) or ps (RMS)
(Tx_Jitter (Usage Info)(Type Float)
(Format Dual-Dirac <mean> <mean> <sigma>))
DJ = (<mean> + <mean>)/2 UI (pk) or ps (pk). Dual-Dirac distribution
RJ = <sigma> UI (RMS) or ps (RMS)
(Tx_Jitter (Usage Info)(Type Float)
(Format DjRj < minDj > < maxDj > <sigma>))
DJ = <maxDJ> UI (pk) or ps (pk). Uniform distribution
RJ = <sigma> UI (RMS) or ps (RMS)
(Tx_Jitter (Usage Info)(Type Integer Float/UI Float)
(Format Table (Labels Row_No Time or UI Probability)
(-5 -5e-12 1e-10)
(-4 -4e-12 3e-7) … ))
Refer to the transmitter jitter description in the Jitter/Noise Component section.
IBIS-AMI Tx_DCD Parameter
Advanced Link Analyzer Interpretation
(Tx_DCD (Usage Info)(Type Float)
(Format Range <typ> <min> <max>))
DCD = <typ or min or max based on corner selection> UI (pk) or ps (pk), Clock jitter distribution
-
Model Specific Parameters—This section
lists all the model specific parameters that the IBIS-AMI model provides. You
can use their selections or specify parameters for the simulation. Figure 33. Transmitter IBIS-AMI Parameter Type Designation for Link Optimization
Advanced Link Analyzer supports link optimization with IBIS-AMI transmitter models. On the left are the model specific parameters. For each parameter that Advanced Link Analyzer determines is sweepable, a pull-down menu allows you to assign the transmitter parameters. The types of transmitter parameters are as follows:
- No Sweep—No sweeping or link optimization is performed
- Sweep—Advanced Link Analyzer sweeps or performs link optimization using available options provided by the IBIS-AMI model
- Sweep as TX Main Tap—Advanced Link Analyzer treats this parameter as the main cursor tap of transmitter equalizer in link optimization
- Sweep as TX Main Tap Sign—Advanced Link Analyzer treats this parameter as the sign bit of the main cursor tap in link optimization
- Sweep as TX Post-Tap n—Advanced Link Analyzer treats this parameter as the n-th post-cursor tap of transmitter equalizer in link optimization
- Sweep as TX Post-Tap n Sign—Advanced Link Analyzer treats this parameter as the sign bit of the n-th post-cursor tap in link optimization
- Sweep as TX Pre-Tap n—Advanced Link Analyzer treats this parameter as the n-th pre-cursor tap of transmitter equalizer in link optimization
- Sweep as TX Pre-Tap n Sign—Advanced Link Analyzer treats this parameter as the sign bit of the n-th pre-cursor tap in link optimization
With the information provided in the IBIS-AMI model and parameter type selections, Advanced Link Analyzer determines the link optimization approach and conducts the simulation. All link optimization methods are supported with IBIS-AMI transmitter models, but generally the CTLE=>FIR=>DFE and CTLE=>FIR+DFE methods are more efficient (in terms of simulation time) and effective. If you cannot determine the nature of the model specific parameters, consult with the IBIS-AMI vendors. An example of transmitter IBIS-AMI parameter type designations is shown in the above figure.
For Intel devices, link optimization is further and better supported using Advanced Link Analyzer IBIS-AMI Wrapper Technology. Therefore, Intel recommends installing and using the IBIS-AMI wrapper for all supported devices.
Status tab
The Status tab shows the parameters that are fed into the IBIS-AMI model for simulations.

Consider the following for the IBIS-AMI transmitter modeling support in Advanced Link Analyzer:
- Advanced Link Analyzer only supports the IBIS model with an AMI component. An IBIS model without an AMI component is not simulated.
- Transmitter PLL is not supported when the IBIS-AMI transmitter is selected.
- Advanced Link Analyzer supports IBIS-AMI transmitter models with the on-die S-parameter model (IBIS BIRD 158.3) using the txic, Tstonefile, or Ts4file IBIS-AMI keyword. When Advanced Link Analyzer detects the txic, Tstonefile, or Ts4file keyword, the Channel Wizard helps you determine the on-die S-parameter configuration.
2.1.3.5. Pulse Fitting Analysis

Pulse fitting analysis can be customized to suit specific transmitter configurations. See the "TX Analysis" section of Transmitter Options and Analysis Functions and Pre-Simulation and Pre-Analysis Checklist for details.
2.1.3.6. SNDR Analysis
Click SNDR Calc or select SNDR Analysis from the Analysis pull-down menu to perform SNDR (Signal to Distortion and Noise Ratio) analysis. The calculation and analysis are implemented according to IEEE 802.3bj and OIF CEI 56G standards. The result provides an indication of transmitter or channel output quality. The fitted pulse, which is a part of the SNDR computation, is shown so that you can observe the fit quality as well as the possible impedance discontinuity locations in your link. The SNDR calculation is performed at the end of the channel. If you want to test the transmitter’s SNDR, you can use an ideal channel, for example, Ideal.s4p in Advanced Link Analyzer’s Database folder, to perform the analysis.

SNDR analysis can be customized to suit specific transmitter configurations. See the "TX Analysis" section of Transmitter Options and Analysis Functions and Pre-Simulation and Pre-Analysis Checklist for details.
2.1.3.7. Jnu/Jrms/Jeo Analysis (beta)
Click Jnu/Jrms Calc or select Jnu/Jrms Analysis from the Analysis pull-down menu to perform PAM4 Jnu/Jrms/Jeo analysis. A Jnu/Jrms/Jeo pre-analysis GUI guides the analysis. There are two jitter analysis methods:
Jitter PDF: Jitter PDF method gets jitter information from users or the TX model. It calculates the Jnu/Jrms at target BER using jitter component convolutions. The Option selection is ignored for Jitter PDF method.
Waveform (beta feature): The calculation and analysis are implemented according to IEEE 802.3 (50 Gbps 802.3cd and 100 Gbps 802.3ck) and OIF CEI (56G and 112G) standards. The result provides an indication of transmitter or channel output quality. The averaged waveform is displayed. The Jnu/Jrms calculation is performed at the end of the channel. If you want to analyze the transmitter’s jitter performance, you can use an ideal channel, for example, Ideal.s4p in Advanced Link Analyzer’s Database folder, to perform the analysis.

Jnu/Jrms analysis can be customized to suit specific transmitter configurations. See Analysis Functions and Pre-Simulation and Pre-Analysis Checklist for details.

2.1.4. Receiver Setting
A receiver receives waveforms from the channel and processes the waveforms through the receiver equalizer and clock and data recovery module.

Advanced Link Analyzer provides the following settings and configurations for receivers:
Receiver
The following receiver types are supported:
- Stratix® V GX
- Arria® V GZ
- Stratix® V GT
- Intel® Arria® 10 GX/SX
- Intel® Arria® 10 GT
- Intel® Stratix® 10 L-tile (wrapper support)
- Intel® Stratix® 10 H-tile (wrapper support)
- Intel® Stratix® 10 E-tile (wrapper support)
- Intel® Stratix® 10 P-tile (wrapper support)
- Intel® Agilex™ E-tile (wrapper support)
- Intel® Agilex™ P-tile (wrapper support)
- Intel® Agilex™ R-tile (wrapper support)
- Intel® Agilex™ P-tile (wrapper support)
- Intel® Agilex™ F-tile general-purpose transceiver block (wrapper support)
- Intel® Agilex™ F-tile high-speed transceiver block (wrapper support)
- IBIS-AMI
- Custom
- PCI Express* 8GT
- PCI Express* 16GT
- PCI Express* 32GT
Parameters or selections within the receiver setting are specific to the receiver type. For example, package model, available CDR (Clock and Data Recovery) type and bandwidth, available CTLE (Continuous Time Linear Equalizer) selections, DFE operation mode and settings, and additional receiver options, are set and shown when a new device is selected. When a new receiver is chosen, it is automatically inserted into the Link Designer, ready for connecting to other link components.
Package
Select the package type for a receiver device. For Intel products and PCI Express* 8GT receivers, the package models are included in the receiver models. For Custom devices, you can specify package models in the channel setting by inserting a “Package” channel component. When you select the Custom package type (for any transmitter device), the embedded package mode (if available) is disabled, and you can add a channel component (such as an S-parameter) with type Package in the Link Designer workspace. The Custom package model must be placed adjacent to the receiver module so it can be simulated and analyzed correctly. If you choose the Custom package type but do not add a channel component with Package type to the Link Designer workspace, the receiver is simulated without any package model. Selecting Package Designer from the Package pull-down menu opens the Receiver Package Designer for you to design or customize package models. Refer to the "Transmitter Package Designer User Interface" figure and description in Transmitter Setting for how to configure the package designer.
Advanced Link Analyzer comes with the following receiver package models:
- Stratix® V GX
- Arria® V GZ
- Stratix® V GT
-
Intel® Arria® 10 GX/SX
Options: Additional package models (shown in the following figure) are available for Intel® Arria® 10 devices. The package model is specified as its trace length inside the package. These models are chosen to cover the range of package trace lengths in Intel® Arria® 10 transceiver receivers.
- Default—The default package model is the same as the 14 mm option
- 14mm
- 16.5mm
- 20mm
- 24mm
Contact My Intel support if you want to know how to pair your design with the Intel® Arria® 10 package model options.
Figure 40. Intel® Arria® 10 Receiver Package Options - Intel® Arria® 10 GT—Same options as Intel® Arria® 10 GX/SX
- Intel® Stratix® 10 L-tile/H-tile/E-tile (wrapper support)—Typical, Minimum, and Maximum package models are provided
- PCI Express* 8GT
- PCI Express* 16GT (place holder only; use custom package model for simulations)
- PCI Express* 32GT
CTLE Setting
Select or specify the CTLE (Continuous-Time Linear Equalizer) operation mode and model. Auto, Manual, and Off (if available) settings are supported.
-
Intel device receivers:
- Stratix® V GX, Arria® V GZ, Stratix® V GT, Intel® Arria® 10 GX/SX and Intel® Arria® 10 GT CTLE models are embedded in Advanced Link Analyzer.
- Both Auto and Manual settings are supported.
- In Manual setting, EQ Bandwidth, AC Gain, and DC Gain menus are shown for user selection.
- In Auto setting, you select the EQ bandwidth and maximum CTLE DC gain level (if available) that you want to use.
- Advanced Link Analyzer uses Intel’s proprietary algorithm to find optimal CTLE setting in Auto setting.
Note: In IBIS-AMI wrapper mode, the CTLE Setting menu can contain parameter selections originated from the underlying IBIS-AMI models. Please refer to the user guide of the IBIS-AMI model for operating mode definition. - Custom receiver and PCI Express* 8GT/16GT/32GT receiver—You can select or input the CTLE gain (in dB) listed in the pull-down menu. The custom CTLE model can use the PCI Express* 8GT CTLE behavior model template and IEEE 802.3cd COM CTLE model template. Refer "Receiver Options" sections for further information.
VGA Bandwidth
The VGA Bandwidth selection is available when an Intel® Arria® 10 GX/SX/GT model is selected. The available VGA bandwidth settings are listed in the pull-down menu. The default setting is 4 (highest bandwidth).
VGA Gain
The VGA Gain selection is available when an Intel® Arria® 10 GX/SX/GT, Intel® Stratix® 10 L-tile, or Intel® Stratix® 10 H-tile model is selected. The available VGA gain settings are listed in the pull-down menu. If Auto (default setting) is selected, the VGA gain setting is determined by the receiver model.
DFE Mode
The DFE can operate in Auto mode, Manual mode, or be disabled.
-
Intel receivers:
- Stratix® V GX, Arria® V GZ, Intel® Arria® 10 GX/SX and Intel® Arria® 10 GT models are supported in both Auto mode and Manual mode.
- In Auto mode, Advanced Link Analyzer finds the optimal DFE setting for the given link configuration.
- In Manual mode, you select and set each DFE tap level.
- For Intel® Arria® 10 GX/SX/GT, the floating DFE tap is no longer supported. To disable the floating DFE tap function, select Off in the First Floating DFE Tap pull-down menu.
- Custom receiver and PCI Express* receivers—Advanced Link Analyzer implements a generic behavior DFE model. You can customize the DFE model with the Receiver Options Window.
CDR Type and CDR Bandwidth
Select the type of Clock and Data Recovery (CDR) module used in the receiver. There are two options: Ideal Clock and supported CDR type. When you select the ideal clock option, the eye diagram is plotted using the ideal system clock. When you enable CDR, both ideal clocked and CDR retimed eye diagrams are shown.
- Intel Receivers— Stratix® V GX, Arria® V GZ, Stratix® V GT, Intel® Arria® 10 GX/SX and Intel® Arria® 10 GT, Intel® Cyclone® 10 GX Hybrid CDR models are supported. The CDR models and configurations are automatically set according to the data rate and CDR bandwidth setting. Consult Intel design guides for CDR bandwidth configurations. With Intel® devices supported by IBIS-AMI wrapper technology, CDR is modeled within the underlying receiver IBIS-AMI model. Refer to IBIS-AMI model's user guide for details.
- Custom receiver and PCI Express* 8GT/16GT/32GT receivers—A generic CDR, with bang-bang phase detector, is supported. The CDR bandwidth for the generic receiver is 18 MHz (low bandwidth), 26 MHz (medium bandwidth), and 34 MHz (high bandwidth).
Supply Voltage
For supported devices, you can choose the supply voltage. The Intel® Arria® 10 GX/SX/GT and Intel® Cyclone® 10 GX receiver model provides the following supply voltages:
- 0.95 V ( Intel® Arria® 10 GX/SX/GT and Intel® Cyclone® 10 GX)
- 1.03 V ( Intel® Arria® 10 GX/SX/GT and Intel® Cyclone® 10 GX)
- 1.12 V ( Intel® Arria® 10 GT)
Vcm
Vcm is the common voltage of the receiver input signal. Vcm options are only available when CTLE mode is QPI.
PVT
Select the process, voltage, and temperature (PVT) models for the selected receiver device. PVT model support varies depending on device type, device data availability, and model coverage. A message is shown on the Receiver tab page to indicate the PVT model coverage. Receiver PVT model coverage and conditions are shown in the following table.
Receiver Type | Waveform PVT Model | Jitter/Noise PVT Model |
---|---|---|
Stratix® V GX | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: –40°C to 100°C |
Arria® V GZ | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: –40°C to 100°C |
Stratix® V GT | Typical | Process: Typical/Fast/Slow Voltage: Typical/High/Low Temperature: 0°C to 100°C |
Intel® Arria® 10 GX/SX | Typical/Fast/Slow | Slow |
Intel® Arria® 10 GT | Typical/Fast/Slow | Slow |
Intel® Stratix® 10 L-tile/H-tile/E-tile/P-tile | Typical/Fast/Slow | Slow |
Wrapper supported Intel IBIS-AMI model | Provide by IBIS-AMI model | Provide by IBIS-AMI model |
Intel® Cyclone® 10 GX | Typical/Fast/Slow | Slow |
IBIS-AMI | Provide by IBIS-AMI model | Provide by IBIS-AMI model |
Custom | None | None |
PCI Express* 8GT/16GT/32GT | None | None |
Temp Range
For Intel® Arria® 10, the device model have temperature range dependency. The temperature range is -40 °C to 100 °C for Industrial, 0 °C tp 105 °C for Extended, and -40 °C to 125 °C for Military. The default setting is Industrial temperature range. Refer to the device's data sheet for the supported temperature range; values in the datasheet take precedence over the values in this document.
Advanced Link Analyzer to Intel® Quartus® Prime Parameter Translation for Intel® Arria® 10 GX/SX/GT Receivers
The following table shows the mapping between the Advanced Link Analyzer’s Intel® Arria® 10 GX/SX/GT receiver model parameters and the Assignments Editor entries in the Intel® Quartus® Prime software. Unless otherwise noted, values translate directly between the two domains.
Advanced Link Analyzer Name | Intel® Quartus® Prime Name |
---|---|
Receiver Options > Termination > R | Receiver On-Chip- Termination |
Supply Voltage | Vccer/Vccet Power |
CTLE Setting / Mode |
Eq_bw_sel (Equalizer bandwidth Selection) If Receiver High Data Rate Mode Equalizer = 1
If Receiver High Data Rate Mode Equalizer = 0
|
VGA BW | VGA_bandwidth_Select |
CTLE Setting / Mode |
Receiver High Data Rate Mode Equalizer If Receiver High Data Rate Mode Equalizer = 1
If Receiver High Data Rate Mode Equalizer = 0
|
CTLE Setting
|
Refer to the Intel® Arria® 10 Transceiver PHY User Guide |
AC Gain with CTLE Setting = Manual Mode = High Data Rate |
Receiver High Data Rate Mode Equalizer AC Gain Control |
AC Gain with CTLE Setting = Manual Mode = High Gain |
Receiver High Gain Mode Equalizer AC Gain Control |
DC Gain with CTLE Setting = Manual Mode = High Gain |
Receiver High Gain Mode Equalizer DC Gain Control |
VGA Gain |
Receiver Variable Gain Amplifier Voltage Swing Select |
DFE Mode | Receiver Decision Feedback Equalizer Mode |
DFE Tap 1 | Receiver Decision Feedback Equalizer Fix Tap One Coefficient |
DFE Tap 2 | Receiver Decision Feedback Equalizer Fix Tap Two Coefficient |
DFE Tap 3 | Receiver Decision Feedback Equalizer Fix Tap Three Coefficient |
DFE Tap 4 | Receiver Decision Feedback Equalizer Fix Tap Four Coefficient |
DFE Tap 5 | Receiver Decision Feedback Equalizer Fix Tap Five Coefficient |
DFE Tap 6 | Receiver Decision Feedback Equalizer Fix Tap Six Coefficient |
DFE Tap 7 | Receiver Decision Feedback Equalizer Fix Tap Seven Coefficient |
RX Impedance (R in Receiver Options / Termination) |
Receiver On-Chip- Termination |
CDR Type Hybrid |
Intel® Arria® 10 Transceiver CMU PLL |
CDR Bandwidth | Bandwidth in PLL Options |
2.1.4.1. Jitter/Noise Setting
Advanced Link Analyzer provides extensive jitter and noise modeling and configuration capabilities. The receiver intrinsic jitter and noise types are categorized in the following table. You can configure each jitter and noise type by clicking Receiver Jitter Options, which leads to the Receiver Jitter/Noise Configuration window.
Advanced Link Analyzer uses a flat jitter/noise structure that assumes no overlapping among the jitter and noise components. Avoid double counting when inputting or importing jitter/noise figures. In the following figure, DJ contains DCD, ISI, PJ, and BUJ. This implies that when you specify DCD and BUJ, the DJ should not be used or the DJ figure should not contain any DCD and BUJ components.
Name |
Description |
Unit |
Support in Advanced Link Analyzer |
Comments |
---|---|---|---|---|
DJ |
Deterministic Jitter |
UI |
Yes |
You can generate the receiver DJ by using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DJ generation method in the Receiver Jitter/Noise Configuration Window. The default receiver DJ method is dual-Dirac. |
BUJ |
Bounded Uncorrelated Jitter |
UI |
Yes |
Same as receiver’s Deterministic Jitter. The default method is Uniform distribution. You can select the BUJ generation method in the Receiver Jitter/Noise Configuration Window. |
RJ |
Random Jitter |
UI-RMS or ps-RMS |
Yes |
RJ is assumed to be Gaussian. You can specify the receiver RJ in eighth pico-second (ps-RMS) or unit-interval (UI-RMS). |
DN |
Deterministic Noise |
mV |
Yes |
You can generate the receiver DN by using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DN generation method in the Receiver Jitter/Noise Configuration Window. The default DJ method is uniform. |
BUN |
Bound Uncorrelated Noise |
mV |
Yes |
Same as receiver DN above. The default method is Truncated Gaussian method. You can select the BUN generation method in the Receiver Jitter/Noise Configuration Window. |
RN |
Random Noise |
mV-RMS |
Yes |
RN is assumed to be Gaussian. |
Jitter PDF |
Jitter Probability Density Function (PDF) |
Jitter amplitude, Probability (Jitter amplitude can be in absolute time or UI (unit interval) unit) |
Yes |
Jitter PDF defines the jitter probability density function. The input format is jitter amplitude in second and probability. The following is a jitter PDF example: -5e-12 1e-10 -4e-12 3e-7 -3e-12 1e-4 -2e-12 1e-2 -1e-12 0.29 0 0.4 1e-12 0.29 2e-12 1e-2 3e-12 1e-4 4e-12 3e-7 5e-12 1e-10 |
Noise PDF |
Noise Probability Density Function |
Noise amplitude, Probability |
Yes |
Noise PDF defines the noise probability density function. The input format is Noise amplitude in volt and probability. The following is a noise PDF example: -50e-3 1e-10 -40e-3 3e-7 -30e-3 1e-4 -20e-3 1e-2 -10e-3 0.29 0 0.4 10e-3 0.29 20e-3 1e-2 30e-3 1e-4 40e-3 3e-7 50e-3 1e-10 |
InpN |
Input Referred Noise |
V2/GHz |
Yes (Except IBIS-AMI model and IBIS-AMI wrapper model) |
Receiver input referred noise is specified as one-sided noise spectral density in the unit of V2/GHz. It produces receiver-setting dependent noise figure for link margin calculation. |

2.1.4.2. Characterization Data Access
Use the following guidelines for characterization data access:
- When Stratix® V GX, Stratix® V GT, Arria® V GZ or Intel® Arria® 10 GX/SX/GT is selected, the Characterization Data Access button appears and you can include the receiver jitter parameters in the simulation.
- Characterization Data Access covers PVT variations. You can select the appropriate process, voltage, and temperature conditions that best match the desired operation conditions.
- After clicking
Characterization Data Access,
Advanced Link Analyzer is configured to use
the characterization data by:
- Setting Jitter/Noise Component Mode for characterization data entries
- Turning on the Jitter/Noise Data Lock
- Importing
device characterization data based on the jitter unit selection
- RJ—Unit selection can be UI (RMS) or ps (RMS)
- Other Jitter—Unit selection can be UI (pk-pk), UI (pk), ps (pk-pk), or ps (pk)
The Advanced Link Analyzer simulation engine uses this characterization data from the database.
- Intel® Stratix® 10 receiver's jitter and noise values are sourced from the IBIS-AMI models or from user inputs per the IBIS-AMI model's documents.
- The characterization data is displayed in the text box for reference purposes. The Advanced Link Analyzer simulation engine uses proprietary algorithms to accurately model the jitter and noise in the simulations.
- You can unlock the jitter and noise contents by turning off the Jitter/Noise Data Lock. However, the jitter and noise models and values can be different from those when the Jitter/Noise Data Lock is turned on.
- Characterization
Data Access is supported when the data rate is in the following range:
- Stratix® V GX: 5 Gbps to 14.1 Gbps
- Stratix® V GT: 19.6 Gbps to 28.1 Gbps
- Arria® V GZ: 5 Gbps to 14.1 Gbps
- Intel® Arria® 10 GX/SX: 3 Gbps to 17.4 Gbps
- Intel® Arria® 10 GT: 3 Gbps to maximum data rate specified in the data sheet
- After changing the link and device configurations, such as data rate, bandwidth, and PVT condition, you must update the jitter value by clicking Characterization Data Access.
- When the
Jitter/Noise Data Lock
is
turned on, Advanced Link Analyzer examines whether the jitter data matches the
simulation configuration during the following conditions:
- Start simulation
- Save link configuration
- In batch simulation mode, jitter data is retrieved and calculated based on the link configuration
When the link configuration exceeds the supporting range of Characterization Data Access, a warning message (conditions 1 and 2) is shown and jitter is reset (all conditions).


A message box appears when the Characterization Data Access button is clicked.

2.1.4.3. Receiver Options
Receiver options provide further configuration and setting options for receivers.
-
Termination tab—This section specifies receiver impedance. Figure 45. Receiver Termination Configuration
For selected Intel devices, use the RX Impedance pull-down menu to select a termination configuration. You can also customize the termination configuration by selecting the Custom option. When the Custom RX Impedance method is chosen, the termination can be configured as follows:
- Ideal RX termination—The receiver is ideal with a 50 ohms (single-ended) termination.
-
Non-ideal RX termination—Select
one of the following options:
- R—Receiver impedance is modeled as a resistance R ohms (single-ended).
- R//C1—Receiver impedance is modeled as an RC network with a parallel resistor (in ohms) and a capacitance (in pF).
- File Input (Frequency Real Imaginary)—Receiver impedance is modeled by a frequency-dependent complex impedance table described in the input file.
For an Intel receiver, the default termination configurations are automatically selected and specified.
- Equalization tab—For Intel® Arria® 10 GX/SX/GT, Stratix® V GX, and Arria® V GZ devices, the DFE model is embedded in the Advanced Link Analyzer with limited configurability. For Custom and PCI Express* 8GT/16GT receivers, the DFE configuration options are provided.

Equalization tab:
- DFE Tap Length—For supported Intel devices, you can manually reduce the DFE tap length. If the selected DFE tap length is larger than the device's original DFE tap length, the change is not applied in the simulation. For Intel® Arria® 10 devices, manually setting the DFE tap length disables floating DFE tap capability in the simulation.
Custom RX FFE/DFE tab:
- Algorithm—FFE/DFE is adapted using the LMS algorithm and its variations.
- DFE Tap Length—Number of DFE taps. This option is only available for Custom and PCI Express* 8GT receivers.
- FFE Tap Length—Number of FFE (feed-forward equalization) taps. This option is only available for Custom and PCI Express* 8GT/16GT receivers.
- Floating Tap—Enable or disable floating tap support. The default is Disable.
- Float Tap Length—Number of floating taps. If multiple-group floating taps is enabled, this specifies the number of floating taps in each group. If multiple-group is disabled, this specifies the total number of floating taps. The default is 4.
- Tap Location Type—Specifies how floating taps are organized. Group means that the floating taps are grouped together. In other words, you can have two groups of 3-tap DFE at separate locations. Individual means that floating taps can spread across the allowed range individually. The default is Group. Disable is not supported so do not select it.
- Number of Groups—Specifies the number of floating-tap groups. The default is 1.
- Max Float Tap Location—Specifies the allowable range of floating taps. The default is 64.
- Step Size—Step size of the LMS algorithm. This parameter controls the speed of the LMS adaptation. The default value is 0.01.
-
Summation Node Model—Advanced Link Analyzer supports two generic/custom summation node
modeling methods:
- 3dB Bandwidth (RC filter): Use a first-order RC filter to perform low-pass filtering of the DFE adjustment. Enter -1 to model the ideal summation node where the bandwidth is infinite.
- S-parameter: Use your S-parameter file to specify a pulse-shaping filter. Only the differential insertion loss (Sdd21) is applied in the pulse shaping.
- Reference Tap—Location of main cursor tap in the FFE.
- Override generic/standard device setting—For standard devices, for example, PCI Express* 8GT and 16GT, the DFE tap length, coefficient range, and summation node bandwidth are pre-configured within the device model. Turn on this option if you want to simulate these devices with custom settings.
Custom RX Common Mode Conditioning tab:
- Common Mode Conditioning—Enable or Disable common mode noise conditioning. The default value is Disable.
-
Method—Advanced Link Analyzer supports these methods. The default value is
CMRR (Scalar) method.
- CMRR (Scalar): Filters the common mode noise by scaling its amplitude by the value specified in the CMRR text box.
- Common Mode Noise Transfer (S-parameter): Filters the common mode noise by an S-parameter specified in the Common Mode Noise Transfer (S-parameter) text box.
- CMRR—Common Mode Rejection Ration value in dB.
-
Common Mode Noise Transfer
(S-parameter)—Specifies transfer function applicable to the common mode
noise. You can click the button next to the text box to select an S-parameter.
Advanced Link Analyzer Channel Wizard helps
you to configure the
S-parameter
values:
- Port configuration type
- Port number
- Lane selection
- Signal flow direction
Custom RX CTLE tab:
-
CTLE Configuration & Gain Control
tab:
-
VGA Configuration
- Target Level: The target voltage level of VGA output
- Max VGA Gain (linear scale): The maximum VGA gain in linear scale
- Gain Granularity: When VGA is in auto mode, the step size of VGA gain
Note: Custom RX's VGA has flat gain across frequencies. -
VGA Configuration
-
CTLE Kernel
Options
tab:
-
CTLE Kernel Type: Choices are Default and COM. Default method uses PCI Express* 8GT reference CTLE model which scales with data rate relative to 8 Gbps, i.e. PCI Express* 8GT's data rate. COM method uses IEEE 802.3cd COM reference CTLE model. Advanced Link Analyzer allow users to modify the frequency divider of pole and zero locations and frequency scaling.
-

- Misc tab—Reserved. This tab is blank.
IBIS-AMI Receiver—Advanced Link Analyzer supports IBIS-AMI receiver modeling. When you select the IBIS-AMI receiver, the IBIS-AMI Receiver page appears. The IBIS-AMI page includes three tabs for additional settings of the IBIS-AMI model.

-
Package—Package models are required in all IBIS models.
Advanced Link Analyzer includes the IBIS
package model in the simulation by default. You can choose other package models
by changing the Package selection to Custom and
specifying the external package model (Channel type Package) as a channel component.Note: Make sure there is only one package model for the IBIS-AMI receiver. Use either package type IBIS-AMI or package type Custom with external package model in the schematic. Simulation errors may occur if you have more than one receiver package model in the link.
-
IBIS Files—Click the file open button next to the IBIS
File text box to select an IBIS model file. Advanced Link Analyzer scans through the IBIS file and allocates all
available receiver components and models. If Advanced Link Analyzer encounters any of the following issues in
opening or interpreting the IBIS-AMI model, a warning message is shown.
- No receiver component or model can be located.
- The DLL for the computer platform cannot be located. Note that the IBIS-AMI model is platform dependent. For example, a 32-bit DLL is required to simulate in a 32-bit link simulator. A 64-bit DLL is required to simulate in a 64-bit simulator. A 32-bit DLL cannot simulate with a 64-bit DLL in the same simulation.
- The DLL occupies so much memory that Advanced Link Analyzer was not able to load it. However, Advanced Link Analyzer might be able to run the simulation with such a DLL because of memory allocation differences in the Advanced Link Analyzer GUI and the simulation engine.
- Component—Select an IBIS component from the IBIS model.
IBIS tab
- Model—Select a device model within a component of an IBIS model.
- Model Selector—Select a model from the model selector list.
- Corner—Select the corner type of a device model. The choices are Typ, Min, and Max.
-
AMI File—Shows the AMI file specified in the IBIS model.
Note: Advanced Link Analyzer currently only supports device models with AMI modeling components.
- DLL File—Shows the DLL file specified in the IBIS model.
- Check [R series] during model load time— Turn on this option if you want Advanced Link Analyzer to scan [R series] settings when the IBIS model is loaded which can take extra loading time especially when the IBIS model is large. When you experience long loading time when reading an IBIS-AMI model, you can optionally disable this feature. Use of R series is not common in most IBIS-AMI models. Check the IBIS-AMI model description or consult model vendor for usage of R series.
-
Use External Termination—Indicates that an external
termination is used in the simulation. The external termination (single-ended)
is specified in the text box on the right. The default setting is not using
external termination and the default external termination (if applicable) is 50
ohms (single-ended). Note: Advanced Link Analyzer automatically enables the external termination option when it detects that the IBIS-AMI model is using [series pin mapping] with [R series] configuration.
-
Automatic Jitter/Noise
Update—Allows automatic jitter/noise updates from the IBIS-AMI model
(available for models which are compliant with IBIS-AMI 6.0 and later).
Automatic Jitter/Noise Update is disabled by default.Note: If you experience unexpected long delay when loading an IBIS-AMI model, you can disable the Automatic Jitter/Noise Update by turning it off. It was seen that certain IBIS-AMI models perform computation-intensive functions (such as equalization adaptation) during the jitter/noise retrieval. You can still retrieve jitter/noise numbers by manually clicking the Manual Jitter/Noise Update button.
- Manual Jitter/Noise Update—When the Automatic Jitter/Noise Update option is disabled, turning on this option allows you to manually update the jitter/noise figures from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later).
- DLL_Path—Specify a folder or path name where the supporting files of an IBIS-AMI model are stored. Refer to the IBIS standards for details.
-
CDR Type—Three options
are available:
- IBIS-AMI—If the receiver IBIS-AMI model contains a CDR model, Advanced Link Analyzer uses the IBIS-AMI model's clock tick output to analyze the link performance. If there is no embedded CDR model in the IBIS-AMI model, the ideal clock is used to access the link's performance.
- Ideal Clock—Advanced Link Analyzer always uses the ideal click to access link performance.
- Bang-Bang—Advanced Link Analyzer uses its internal bang-bang CDR model to access the link performance. If the embedded CDR model is present in the IBIS-AMI model, it is neglected.
- Bandwidth—When the Bang-Bang CDR is selected, the CDR loop bandwidth can be set to Low, Medium, or High. (This is the same as the generic custom receiver's CDR settings.)
AMI tab
The AMI tab shows the following AMI configuration parameters.

- Model Name—IBIS-AMI model name
-
Reserved Parameters:
- The IBIS-AMI reserved parameters are shown. The reserved parameters are meant for the Advanced Link Analyzer simulation configuration.
- Advanced Link Analyzer supports the IBIS-AMI Rev. 5.0 and 6.0 jitter format. IBIS-AMI receiver jitter parameters (Rx_Clock_PDF) are extracted and automatically set in the Receiver's Jitter/Noise window with the interpretation shown in the following tables:
IBIS-AMI Rx_Clock_PDF Parameter |
Advanced Link Analyzer Interpretation |
---|---|
(Rx_Clock_PDF (Usage Info)(Type Float) (Format Gaussian <mean> <sigma>)) |
DJ = <mean> UI (pk) or ps (pk), Uniform distribution RJ = <sigma> UI (RMS) or ps (RMS) |
(Rx_Clock_PDF (Usage Info)(Type Float) (Format Dual-Dirac <mean> <mean> <sigma>)) |
DJ = (<mean> + <mean>)/2 UI (pk) or ps (pk), Dual-dirac distribution RJ = <sigma> UI (RMS) or ps (RMS) |
(Rx_Clock_PDF (Usage Info)(Type Float) (Format DjRj < minDj > < maxDj > <sigma>)) |
DJ = <maxDJ> UI (pk) or ps (pk), Uniform distribution RJ = <sigma> UI (RMS) or ps (RMS) |
(Rx_Clock_PDF (Usage Info)(Type Integer Float/UI Float) (Format Table (Labels Row_No Time or UI Probability) (-5 -5e-12 1e-10) (- 4 - 4e-12 3e-7) … )) |
Refer to receiver jitter PDF |
IBIS-AMI Rx_Receiver_Sensitivity Parameter |
Advanced Link Analyzer Interpretation |
---|---|
(Rx_Receiver_Sensitivity (Usage Info)(Type Float) (Format Value <value>)) |
DN = <value>*1000 (unit is mV) with uniform distribution |
(Rx_Receiver_Sensitivity (Usage Info)(Type Float) (Format Range < typ > <min> <max>)) |
DN = <typ>, <min>, or <max> *1000 (unit is mV) with uniform distribution |
(Rx_Receiver_Sensitivity (Usage Info)(Type Float) (Format Corner < typ > <slow> <fast>)) |
DN = <typ>, <slow>, or <fast> *1000 (unit is mV) with uniform distribution |
IBIS-AMI Rx_Noise Parameter |
Advanced Link Analyzer Interpretation |
---|---|
(Rx_Noise (Usage Info)(Type Float) (Format Value <value>)) |
RN = <value>*1000 (unit is mV-rms) |
(Rx_Noise (Usage Info)(Type Float) (Format Range < typ > <min> <max>)) |
RN = <typ>, <min>, or <max>*1000 (unit is mV-rms) |
(Rx_Noise (Usage Info)(Type Float) (Format Corner < typ > <slow> <fast>)) |
RN = <typ>, <slow>, or <fast>*1000 (unit is mV-rms) |
IBIS-AMI Rx_Dj Parameter |
Advanced Link Analyzer Interpretation |
---|---|
(Rx_Dj (Usage Info)(Type Float) (Format Value <value>)) |
DJ = <value>*1012 (unit is ps-pk) |
(Rx_Dj (Usage Info)(Type Float) (Format Range < typ > <min> <max>)) |
DJ = <typ>, <min>, or <max>*1012 (unit is ps-pk) |
(Rx_Dj (Usage Info)(Type Float) (Format Corner < typ > <slow> <fast>)) |
DJ = <typ>, <slow>, or <fast>*101212 (unit is ps-pk) |
(Rx_Dj (Usage Info)(Type UI) (Format Value <value>)) |
DJ = <value>*1012 (unit isUI-pk) |
(Rx_Dj (Usage Info)(Type UI) (Format Range < typ > <min> <max>)) |
DJ = <typ>, <min>, or <max>*1012 (unit is UI-pk) |
(Rx_Dj (Usage Info)(Type UI) (Format Corner < typ > <slow> <fast>)) |
DJ = <typ>, <slow>, or <fast>*1012 (unit is UI-pk) |
IBIS-AMI Rx_Rj Parameter |
Advanced Link Analyzer Interpretation |
---|---|
(Rx_Rj (Usage Info)(Type Float) (Format Value <value>)) |
RJ = <value>*1012 (unit is ps-rms) |
(Rx_Rj (Usage Info)(Type Float) (Format Range < typ > <min> <max>)) |
RJ = <typ>, <min>, or <max>*1012 (unit is ps-rms) |
(Rx_Rj (Usage Info)(Type Float) (Format Corner < typ > <slow> <fast>)) |
RJ = <typ>, <slow>, or <fast>*101212 (unit is ps-rms) |
(Rx_Rj (Usage Info)(Type UI) (Format Value <value>)) |
RJ = <value> (unit is UI-rms) |
(Rx_Rj (Usage Info)(Type UI) (Format Range < typ > <min> <max>)) |
RJ = <typ>, <min>, or <max> (unit is UI-rms) |
(Rx_Rj (Usage Info)(Type UI) (Format Corner < typ > <slow> <fast>)) |
RJ = <typ>, <slow>, or <fast> (unit is UI-rms) |
- Model Specific Parameters— This section lists all the model specific parameters that the IBIS-AMI model provides. You can use their selections or specify parameters for the simulation.

Advanced Link Analyzer supports link optimization with IBIS-AMI receiver models. On the left are the model specific parameters. For each parameter that Advanced Link Analyzer determines is tunable, a pull-down menu allows you to assign the receiver parameters. The types of receiver parameters are as follows:
- No Sweep—No sweeping or link optimization is performed
- Sweep—Advanced Link Analyzer sweeps or performs link optimization using available options provided by the IBIS-AMI model. This parameter is not supported in the current Advanced Link Analyzer version.
- CTLE Adapt Controller—This receiver parameter enables or disables automatic adaptation of the CTLE or analog equalizer. This sweep parameter is used when the link optimization method is CTLE=>FIR=>DFE, CTLE=>FIR=>CTLE=>DFE, CTLE=>FIR+DFE, or CTLE=>FIR+DFE=>CTLE+DFE.
- DFE Adapt Controller—This receiver parameter enables or disables automatic adaptation of the DFE. This sweep parameter is used when the link optimization method is CTLE=>FIR=>DFE, CTLE=>FIR=>CTLE=>DFE, CTLE=>FIR+DFE, or CTLE=>FIR+DFE=>CTLE+DFE.
- Sweep as CTLE—This receiver parameter is swept as the CTLE or analog equalizer with all available options.
- Sweep as CTLE AC Gain—This receiver parameter is swept as the CTLE’s AC gain controller. This sweep parameter is generally used in conjunction with the Sweep as CTLE DC Gain parameter.
- Sweep as CTLE DC Gain—This receiver parameter is swept as the CTLE’s DC gain controller. This sweep parameter is generally used in conjunction with the Sweep as CTLE AC Gain parameter.
With the information provided in the IBIS-AMI model and parameter type selections, Advanced Link Analyzer determines the link optimization approach and conducts the simulation. If you cannot determine the nature of the model specific parameters, consult with the IBIS-AMI vendors. An example of transmitter IBIS-AMI parameter type designations is shown in the above figure.
For Intel devices, link optimization is further and better supported using Advanced Link Analyzer’s IBIS-AMI Wrapper Technology. Therefore, Intel recommends installing and using the IBIS-AMI wrapper for supported devices.
Status tab
The Status tab shows the parameters that are fed into the IBIS-AMI model for simulations.

Consider the following for the IBIS-AMI receiver modeling support in Advanced Link Analyzer:
- Advanced Link Analyzer only supports the IBIS model with an AMI component. An IBIS model without an AMI component is not simulated.
- Receiver CDR is supported by the IBIS-AMI model itself
- Advanced Link Analyzer supports IBIS-AMI receiver models with the on-die S-parameter model (IBIS BIRD 158.3) using the rxic, Tstonefile, or Ts4file IBIS-AMI keyword. When Advanced Link Analyzer detects the rxic, Tstonefile, or Ts4file keyword, the Channel Wizard helps or automatically determines the on-die S-parameter configuration based on IBIS standards.
2.1.5. IBIS-AMI Wrapper
- Provide enhanced feature on top of the IBIS-AMI models such
as:
- Joint transmitter and receiver link optimization
- Reference clock modeling
- Transmitter PLL modeling
- Incremental accuracy improvement
- Improve user experiences
- Integrate IBIS-AMI settings with Advanced Link Analyzer Control Module’s graphical user interface
- Single click to select and configure Intel® ’s IBIS-AMI models
- Automatically configure the device according to link settings
- Plug-and-Play device models
- Allow post-installation model updates
- Close Advanced Link Analyzer.
- Acquire the IBIS-AMI model from My Intel® support.
- Create a new folder in C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\Database\ with the folder name instructed. For example, for the Intel® Stratix® 10 L-tile transceiver, the folder name is S10L. For the Intel® Stratix® 10 H-tile transceiver, the folder name is S10H. For the Intel® Stratix® 10 E-tile, the folder name is S10E. For the Intel® Stratix® 10 P-tile, the folder name is S10P. For the Intel® Agilex™ E-tile, the folder name is AG_E. For the Intel® Agilex™ P-tile, the folder name is AG_P.
- Copy all files associated with IBIS-AMI model into the folder created in step 3.
- Copy all package models into the folder created in step 3.
- Optionally, additional files to be copied into the database folder.
After installing the Intel® IBIS-AMI model and restarting the Advanced Link Analyzer, the new device appears in the device selection menu and is ready for use.
- IBIS-AMI GUI integration
- Package model encapsulation
- Joint transmitter (for supported transmitter models) and receiver link optimization
2.1.6. Channel Setting
The channel connects the transmitter and the receiver. It contains transmission media such as PCB traces, connectors, backplanes, cables, and device packages. A channel is a combination of numerous components described by channel models. Advanced Link Analyzer’s channel processing engine first interprets the channel models and then connects and cascades channels to construct one channel component for link simulations.
Advanced Link Analyzer supports single-ended Touchstone 1.0 and selected types of Touchstone 2.0 S-parameter channel models. It can access and process n-port S-parameters and extract transmission responses and crosstalk responses. After successfully extracting the channel characteristics, it performs differential-pair channel cascading for subsequent link simulation.
Advanced Link Analyzer supports key Touchstone 2.0 features for high-speed serial link simulations. Highlights of Touchstone 2.0 support in the current version include:
- Touchstone 2.0 headers.
- Matrix format is supported.
- Mixed-mode S-parameter is partially supported. Advanced Link Analyzer currently requires the whole mixed-mode S-parameter or only the differential-input-differential-output response to be present. This means that either all sections, which include differential-differential, differential-common, common-differential, and common-common sections of all ports and differential pairs are present, or only the differential-differential section is present. Partial mixed-mode S-parameters are not allowed.
- S-parameter files with an odd number of ports or odd number of differential pairs are not supported.
- Noise data and associated data formats can be included in the file but are not processed.
- Arbitrary port reference is not supported.
Advanced Link Analyzer supports Channel Designer components such as stripline, microstrip, coax, RLGC, ideal transmission line, coupled stripline, and coupled microstrip. When you select a Channel Designer component, you can choose different configurations in the associated channel designer GUI. PCB stackup is also supported, in which you can enter PCB substrate and stackup information. Supported channel models, which include stripline, microstrip, coupled stripline, and coupled microstrip, can utilize any available PCB stackup dataset in the design. Multiple PCB stackup dataset is supported in Advanced Link Analyzer. Refer to the Advanced Link Analyzer Channel Designer section for detailed information about the usage of channel designer components.
Advanced Link Analyzer implements the Link Designer, which allows you to graphically construct the communication link. In the following figure, the Channel List shows a channel construction example with one transmission channel (such as a loss channel or a victim channel) and two crosstalk channels.

An S-parameter channel component such as a connector, cable, or backplane can be described by the following parameters or information:
-
ID—Sequence or location of the channel component. The top
channel is connected to the transmitter and the bottom channel is connected to
the receiver. Note: Embedded package models (such as Package models for Intel devices and PCI Express* Gen3 devices) are not shown in the channel list or Link Designer.
- Channel Name—An S-parameter file that describes the channel component. The S-parameter can be 4-port, 8-port, 12-port, 16-port, and so forth. When your cursor hovers on a channel list, a tooltip shows the S-parameter file location. This information is useful if you share Advanced Link Analyzer configuration files.
- Type—Specify the type of channel characteristics to be used in the link simulation. The type of channel characteristics can be insertion loss (Loss), far-end crosstalk (FEXT), or near-end crosstalk (NEXT). You can change the channel (or channel type) by selecting the channel from the Link Designer using the Channel Wizard.
- Port Configuration—Depending on the S-parameter measurement condition, the port configuration can be one of the following types. Use the Channel Wizard to change the port configuration of an S-parameter.




If the S-parameter file is not Type 1, Type 2, or Type 3, you can use the Custom option in the Channel Wizard’s Port Config pull-down menu, as shown in the following figure. When a Custom port configuration is selected in the Channel Wizard, a text box named Port Map appears below the port configuration figure (one of the configurations in the above figure). Enter the port numbers in the sequence [P1, P2, P3, …Pn], where n is the number of ports, as illustrated in the figure above that matches the selected S-parameter model. In the figure below, the Port Map sequence 1 3 2 4 corresponds to a 4-port (n=4) S-parameter model with port configuration Type 2 where P1=1, P3=Pn/2+1=2, P2=3, and P4=Pn/2+2=4. When a custom port configuration is assigned to an S-parameter model, it is displayed as port configuration Type 4 in the channel table.

- Lane—This field lists the channel lane ID number. For channel lane S-parameters that are 8-port and above, a channel lane must be chosen for link simulations. For example, the above figures show a 12-port 3-lane S-parameter. After loading the channel file, Advanced Link Analyzer assigns the center lane as the default simulating channel (or victim channel for crosstalk simulations). Use the Channel Wizard to change the lane ID. For 2-port or 4-port S-parameter models, the lane ID is ignored.
- Reverse—This field indicates whether the channel signal flow direction is to be reversed. This is generally used for the device package model when you want to make sure transmitter and receiver devices are connected to the die side of the package S-parameter model. Refer to the S-parameter comment section for S-parameter signal flow configuration.
- Swap P/N—This field indicates whether P-port and N-port of the S-parameter are swapped.
- AC Cap—This field records AC coupling capacitor value in nF (nano-Farad, 10-9 F).
- Shunt Cap—This field records shunt capacitance value in pF (pico-Farad, 10-12 F).
A crosstalk aggressor has the following parameters:
-
Source—Each crosstalk aggressor can be of Inline, Transmitter, or Aggressor type.
- With an inline aggressor, the input to the crosstalk channel is the input waveform at the last transmission/victim channel segment.
- With a transmitter aggressor, the aggressor waveform is the same as the victim transmitter with the above aggressor effects, such as frequency offset, delay, and relative amplitude, applied.
- If the aggressor type is “Aggressor X”, the aggressor is modeled by the Xth aggressor type as shown in the Aggressor Transmitter tab (refer to the Crosstalk Aggressor Transmitter Setting section).
The following figure shows the three crosstalk aggressor transmitter types. Inline aggressor means the signal feeding into the crosstalk channel comes from the immediate victim channel in parallel with the XTLK channel (as shown in the red dotted arrow line). TX Aggressor means that, regardless of where the XTLK channel is located, this XTLK always uses the VICTIM TX output as its signal source (shown in the green dotted line). The Individual Aggressor TX is similar to the Victim TX Aggressor, but it can be generated separately.
Figure 58. Crosstalk Aggressor Types
-
Location—For multiple channel/lane S-parameters simulating
crosstalk effects, you must specify the aggressor location. For example, the
above figures show four possible crosstalk configurations from a 12-port
S-parameter model. Use the
Aggressor Location menu in the
Channel Wizard to change the aggressor location. The Aggressor
ID field is ignored for a victim channel (Loss type).
Note: The Aggressor ID index excludes victim lanes. For example, in a 12-port S-parameter, there are three lanes. If the middle lane (Lane ID 2) is a victim lane, the two aggressor channels have Aggressor ID 1 and 2, not 1 and 3.
- Relative Amplitude—Each crosstalk aggressor can have different aggressor amplitude relative to its original amplitude. The default value for aggressor is 1.0, which indicates the aggressor has its original amplitude. The Aggressor ID field is ignored for a victim channel (Loss type).
- Delay—Each crosstalk aggressor can have individual delay or time offset. The delay is input in picoseconds (ps, 10-12 second). Positive values in aggressor delay indicate the aggressor is lagging behind the victim waveform. Negative values indicate the aggressor is ahead of the victim signal waveform. The Aggressor ID field is ignored for a victim channel (Loss type).
- Frequency Offset—Each crosstalk aggressor can run on an offset frequency compared to the victim channel’s transmitter. The frequency offset is given in negative ppm (parts per million). The maximum frequency is –950,000 ppm.
The Channel Viewer button is a convenient way of observing channel characteristics in the current channel list. Click Channel Viewer to transfer the channels to a new Channel Viewer window. You can then observe various parts of channel characteristics in either frequency- or time-domain. Use the Advanced Link Analyzer Channel Viewer to view cascaded channel characteristics if multiple channel components are used in the victim signal path. The following figure illustrates the Channel Viewer plot of the channel construct shown in Figure 59.

Refer to the Tutorial: PCI Express* 8GT chapter for step-by-step channel setup instructions.
Automatic S-parameter Configuration Check (ASCC)
Advanced Link Analyzer uses a proprietary Automatic S-parameter Configuration Checker (ASCC) to help you set and connect the S-parameter in the channel chain. With ASCC, Advanced Link Analyzer inspects the S-parameter model and determines the port number and port configuration. ASCC also selects the middle lane as the victim channel (insertion loss channel) and sets the Lane and Aggressor pull-down menus for user configuration. Channel configuration information is saved individually for each channel. Therefore, S-parameters with different port numbers, port configurations, or both can be mixed and cascaded in Advanced Link Analyzer.
2.1.7. Batch Channel Simulation Configuration
Advanced Link Analyzer provides a convenient way to set up batch channel simulations. Batch channel simulation generation can be accomplished when the following conditions are met:
- A complete link is
graphically configured. This requires that:
- The link contains a transmitter, receiver, and at least one transmission channel.
- In the Link Designer, the connection lines from the transmitter to the receiver are bold black lines.
- The link configuration is complete and ready for simulating with a variety of channels. Link configurations such as data rate, test pattern, BER target, reference clock setting, transmitter and receiver operation mode, and link optimization method are set and ready for simulations.

- Choose a connected channel from the
Link Designer work space. Right-click on the channel to bring up a context menu.
Figure 61. Batch Channel Simulation Configuration Selection
The Advanced Link Analyzer Batch Simulation Channel Selection window appears.
Figure 62. Batch Simulation Channel Selection Window - Click Add
Channel to select channel files. A file browser helps you select the
channel files you want. You can select multiple channels within the file
browser. You can also click Add Channel repeatedly to add
more channels. The added channel is listed in the Channel list box with channel
type, port configuration, lane (if the channel is 8-port or more), and aggressor
identification (if the channel is a crosstalk channel within a multiple-lane
S-parameter).
- Advanced Link Analyzer uses the Automatic S-parameter Configuration Check (ASCC) algorithm to automatically detect S-parameter models’ port configuration and designate default transmission lane.
- To observe a
channel’s characteristics or change a channel’s configuration, you can:
- Select the channel and then click View using Channel Wizard. The Advanced Link Analyzer Channel Wizard helps you configure the channel.
- To see all channels' characteristics, click View All using Channel Viewer to start the Channel Viewer (refer to the Advanced Link Analyzer Channel Viewer Module sections for details).
- Use the pull-down menus or buttons below the channel list boxes to change individual channel configuration.
- Optionally, you can edit the batch simulation file name header in the pull-down menu or the text box below the channel list boxes. By default, Advanced Link Analyzer uses the Date-Time string as the file name header. You can also type the desired header name in this box.
Figure 63. Example of Batch Channel Selections - When channel selection is
complete, click Generate Simulation Configuration to
generate Advanced Link Analyzer simulation
configuration files with the selected channels. Note: In the current implementation of Advanced Link Analyzer, all simulation configuration files generated from step 3 are saved in the Advanced Link Analyzer installation directory.
After completing these steps, a series of Advanced Link Analyzer simulation configuration files are generated. For example, by using the Date-Time header option, four sets of Advanced Link Analyzer simulation configuration files are generated.

Launch Advanced Link Analyzer Batch Simulation Controller to run the generated link simulations (refer to the Advanced Link Analyzer Batch Simulation Controller section for details). The following figure shows the generated batch channel simulations added in the Advanced Link Analyzer Batch Simulation Controller and ready for batch simulations.

2.1.8. Crosstalk Aggressor Transmitter Setting
Aggressor transmitter configurations allow you to configure crosstalk aggressors individually with different transmitter types, pre-emphasis settings, amplitudes, data rates, and so forth. The following figure shows a 2-aggressor link with three different aggressor transmitters.

Follow the steps described in the previous section to set up a link with crosstalk channels. In the Channel Wizard window, in the Signal Source menu of the Crosstalk Aggressor panel, select the Inline, Transmitter, or one of the eight available Aggressor types.

Advanced Link Analyzer supports up to eight individual crosstalk aggressor transmitters. However, a crosstalk aggressor transmitter can be shared among crosstalk channels. By combining the aggressor relative amplitude, frequency offset, and delay setting, Advanced Link Analyzer can generate a variety of crosstalk aggressor signal sources.
After completing the configuration in the Channel Wizard, go to the Advanced Link Analyzer GUI and select the Aggressor Transmitter tab.

Within the Aggressor Transmitter tab, there are eight aggressor types associated with the aggressor types in the Channel Wizard’s Signal Source menu. Each aggressor can be configured as follows:
- Data Rate—Data rate of the selected aggressor transmitter in Gbps.
-
Test Pattern—Aggressor transmitter’s test pattern. Advanced Link Analyzer
supports the following test patterns:
- Same as victim TX
- PRBS-7, PRBS-9, PRBS-11, PRBS-15, PRBS-23, PRBS-31
- VOD—Differential output voltage of the aggressor transmitter in volts.
-
Transmitter Type—Aggressor transmitter can be one of the
following transmitter types:
- Same as victim TX
- Stratix® V GX
- Arria® V GZ
- Stratix® V GT
- Custom
-
Pre-emphasis / FIR—Pre-emphasis or FIR setting of the
aggressor transmitter. You can set it to be the same as the victim TX or you
can type in the setting.
Note:
- In manual pre-emphasis/FIR input mode, the pre-emphasis/FIR setting must be in the same format as used in the Transmitter tab. This does not mean that the aggressor transmitter must be the same type as the victim transmitter, but that the pre-emphasis setting format must be in the format as if it is a victim transmitter. For example, if the aggressor transmitter type is Intel Stratix® V GX, the pre-emphasis/FIR setting is in a list of TX-FIR levels such as -1, 0, 20, 3, where -1 is the pre-tap 1 value, 20 is the post-tap 1 value, and 3 is the post-tap 2 value. The main tap can be any value, because Advanced Link Analyzer determines the main tap's value based on the values of other FIR taps.
- If you input TX pre-emphasis /FIR, which is invalid for the selected transmitter type, then pre-emphasis/FIR is disabled.
If the transmitter type is Custom, the following parameters are also used:
- Edge Rate—Advanced Link Analyzer generates a transmitter output waveform with the specified edge rate. Edge rate is in the format of ps/Volt.
- TX-FIR Length—Length of TX-FIR for custom aggressor transmitter.
- Main-Tap Location—Location of main tap of aggressor transmitter.
The example shown in Figure 68 indicates an aggressor transmitter, which is a custom transmitter type, running at 6.5 Gbps with the PRBS-23 test pattern and a VOD of 1.2 V. The TX FIR coefficients are [-0.1, 0.8, -0.1] with a TX-FIR length of 3 and the main tap is at 2nd tap. According to the link configuration shown in Figure 66, this aggressor transmitter is associated with Crosstalk (FEXT) channel ID = 2.
2.1.9. Repeater and Retimer Configurations
Advanced Link Analyzer supports repeater and retimer simulations. A repeater is a device that can be placed within a link where it can provide additional equalization capabilities. It is typically constructed with two major stages: an equalizer stage and a driver stage. The equalizer stage usually contains continuous-time linear equalizer (CTLE) circuitry that compensates the channel before and, possibly, after the repeater depending on the design of the driver stage. The driver stage usually amplifies the equalized signal and may contain an emphasis function so that it may compensate the channel after the repeater. Depending on the driver stage design, a repeater can be a linear repeater, where the driver maintains linear characteristics within the majority of the signal amplitude range, or a non-linear repeater, where a limiting amplifier between the equalizer stage and driver stage can sharpen the waveform’s transition time. Both linear and non-linear repeater simulations are supported in Advanced Link Analyzer.
Similar to a repeater, a retimer is a device that can be placed within a link where it provides additional equalization and jitter/noise cleaning capabilities. A retimer is constructed with two major stages: an equalizer stage, which is equipped with the clock data recovery (CDR) circuitry, and a driver stage. The equalizer with a CDR stage first compensates the channel effects for the link before the retimer, and then the CDR recovers the bit time and data for its output. During this process, it not only compensates for channel effects, but also resets or reduces jitter and noises that may come from the reference clock, transmitter, or other channel components. Also, with the presence of a CDR, more advanced equalization schemes, such as decision feedback equalizer (DFE), can be incorporated in a retimer. The driver stage is similar to that of a repeater. A retimer is non-linear by nature as both the bit time and amplitude are re-generated.
- Simulation mode: Hybrid mode or Full Waveform mode. Repeater/Retimer simulations in Statistical simulation mode are not supported.
- Repeater and retimer model format: The repeater and retimer models must be in IBIS-AMI format. IBIS version 6.0 (and later) officially supports repeater and retimer simulations and models are available from vendors. The only exception is that, for certain linear repeaters, vendors may provide their models in S-parameter format. If this is the case, users can just treat the repeater S-parameter as a regular channel component and place/connect it in the schematic editor.
A repeater/retimer IBIS-AMI model consists of two internal models: an IBIS-AMI receiver model, i.e., the equalizer/CDR stage, and an IBIS-AMI transmitter model, i.e., the driver stage. In Advanced Link Analyzer, you explicitly place a pair of a receiver link component (Repeater/Retimer RX) plus a transmitter link component (Repeater/Retimer TX) in the schematic editor for a repeater/retimer model. Figure 69 shows the repeater/retimer GUI entries and Figure 70 shows a typical repeater/retimer link configuration. Note that while Advanced Link Analyzer does enforce or limit how the link components are connected within a link, you have to ensure the repeater/retimer RX and repeater/retimer TX model are connected in the correct signal flow order and no other link or channel component is placed between the repeater/retimer RX and TX models.
Note that the repeater and retimer IBIS-AMI model may be provided in various formats. The equalizer/CDR stage model, which is with IBIS receiver component type, and the driver stage, which is with IBIS transmitter component type, may belong to the same IBIS model or may be provided in two separate IBIS models. Please consult the vendors for the usage.


2.1.9.1. Repeater/Retimer RX Configuration
-
IBIS Files: Click the file open button
next to the IBIS File text box to select an IBIS model file. Advanced Link Analyzer scans through the IBIS file
and allocates all available receiver components and models. If Advanced Link Analyzer encounters any of the
following issues in opening or interpreting the IBIS-AMI model, a warning
message
is
shown.
- No receiver component or model can be located.
- The DLL for the computer platform cannot be located. Note that the IBIS-AMI model is platform dependent. For example, a 32-bit DLL is required to simulate in a 32-bit link simulator. A 64-bit DLL is required to simulate in a 64-bit simulator. A 32-bit DLL cannot simulate with a 64-bit DLL in the same simulation.
- The DLL occupies so much memory that Advanced Link Analyzer was not able to load it. However, Advanced Link Analyzer might be able to run the simulation with such a DLL because of memory allocation differences in the Advanced Link Analyzer GUI and the simulation engine.
- Component: Select an IBIS component from the IBIS model.
-
IBIS tab
- Model: Select a device model within a component of an IBIS model.
- Model Selector: Select a model from the model selector list.
- Corner: Select the corner type of a device model. The choices are Typ, Min, and Max.
-
AMI File: Shows the AMI file specified in the
IBIS model.Note: Advanced Link Analyzer currently only supports device models with AMI modeling components.
- DLL File: Shows the DLL file specified in the IBIS model.
-
Use External Termination:
Indicates that an external termination is used in the simulation.
The external termination (single-ended) is specified in the text box
on the right. The default setting is not using external termination
and the default external termination (if applicable) is 50 ohms
(single-ended).Note: Advanced Link Analyzer automatically enables the external termination option when it detects that the IBIS-AMI model is using [series pin mapping] with [R series] configuration.
-
Automatic Jitter/Noise Update :
Allows automatic jitter/noise updates from the IBIS-AMI model
(available for models which are compliant with IBIS-AMI 6.0 and
later).Note: If you noticed very slow GUI response with certain IBIS-AMI models, turn off Automatic Jitter/Noise Update to see if the condition improves. You can import jitter/noise number using Manual Jitter/Noise Update.
- Manual Jitter/Noise Update: When the Automatic Jitter/Noise Update option is disabled, turning on this option allows you to manually update the jitter/noise figures from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later).
- DLL Path: Specify a folder or path name where the supporting files of an IBIS-AMI model are stored. Refer to the IBIS standards for details.
- User Rising/Falling Waveform: Internal testing feature. Do not use and left as is.
- Receiver Mode: Used to select the function or behavior of the receiver model. Select Auto Detect to let Advanced Link Analyzer determine the operating mode based on the model’s capabilities. Select Repeater to force Advanced Link Analyzer to use this model as a repeater’s equalization stage. Select Retimer to ask Advanced Link Analyzer to treat, if possible, this model as the equalizer/CDR stage of a retimer. The default setting is Auto Detect.
- CDR Retime Modeling Options / Retime Method: Select Precision to tell Advanced Link Analyzer to assume the return clock ticks are precise sufficiently that accumulated clock time equal the simulation time line. Select Speed to ask the simulation engine to process the returned clock times with a limited window of time frame. Select Default is the same as the Speed option.
- AMI tab: Refer to IBIS-AMI Receiver in the Receiver Options section for details.
- Jitter/Noise: Refer to IBIS-AMI Receiver in the Receiver Options section for details.
- Status tab: Refer to IBIS-AMI Receiver in the Receiver Options section for details.
- Jitter/Noise Options: Internal use only. Do not use and let it remain in its default state.



2.1.9.2. Repeater/Retimer TX Configuration
-
IBIS Files: Click the file open button
(see Figure 74) next to
the IBIS File text box to select an IBIS model file. Advanced Link Analyzer scans through the
IBIS file and allocates all available transmitter components and models. If
Advanced Link Analyzer encounters the following issues in opening or interpreting the
IBIS-AMI model, a warning message is displayed.
- No transmitter component or model can be located.
- The DLL for the computer platform cannot be located. The IBIS-AMI model is platform dependent. For example, a 32-bit DLL is required to simulate in a 32-bit link simulator and a 64-bit DLL is required to simulate in a 64-bit simulator. A 32-bit DLL cannot simulate in a 64-bit DLL simulator.
- The DLL occupies too much memory and Advanced Link Analyzer was not able to load it. However, Advanced Link Analyzer might be able to run the simulation with such a DLL because of memory allocation differences in the Advanced Link Analyzer GUI and the simulation engine.
- Component: Select an IBIS component from the IBIS model
-
IBIS tab
- Model: Select a device model within a component of an IBIS model.
- Model Selector: Select a model from the model selector list.
- Corner: Select the corner type of a device model. The choices are Typ, Min, and Max.
-
AMI File: Shows the AMI file specified in the
IBIS model.Note: Advanced Link Analyzer currently only supports device models with AMI modeling components.
- DLL File: Shows the DLL file specified in the IBIS model.
- Use External Termination: Indicates that an external termination is used in the simulation. The external termination (single-ended) is specified in the text box on the right. The default setting is not using external termination and the default external termination (if applicable) is 50 ohms (single-ended).
- Use Rising/Falling Waveform: If rising/falling waveforms are available in the IBIS model, the rising/falling waveforms are used to model the transmitter by default. If you turn off this option, ramp data (in the IBIS model) is used in the simulation.
-
Automatic Jitter/Noise Update:
Allows automatic jitter/noise updates from the IBIS-AMI model
(available for models which are compliant with IBIS-AMI 6.0 and
later).Note: If you noticed very slow GUI response with certain IBIS-AMI models, turn off Automatic Jitter/Noise Update to see if the condition improves. You can import jitter/noise number using Manual Jitter/Noise Update.
- Manual Jitter/Noise Update: When the Automatic Jitter/Noise Update option is disabled, turning on this option allows you to manually update the jitter/noise figures from the IBIS-AMI model (available for models which are compliant with IBIS-AMI 6.0 and later).
- DLL_Path: Specify a folder or path name where the supporting files of an IBIS-AMI model are stored. Refer to the IBIS standards for details.
- Model Option: Choose Default.
- Ideal Front-end Limiting Amplifier: If on, Advanced Link Analyzer inserts an ideal limiting amplifier before the repeater/retimer driver stage with a waveform differential amplitude of 1 V.
- AMI tab: Refer to IBIS-AMI Transmitter in the Characterization Data Access section for details.
- Jitter/Noise: Refer to IBIS-AMI Transmitter in the Characterization Data Access section for details.
- Status tab: Refer to IBIS-AMI Transmitter in the Characterization Data Access section for details.
- Jitter/Noise Options: Internal use only. Do not use and let it remain in its default state.



2.1.10. Noise Source Link Component
Advanced Link Analyzer supports noise source generation and simulation in the link level. While most high-speed serial links’ noise are generated by the transmitter and receivers (and their supporting networks and components like power supplies, reference clock, and crosstalk), many industrial standards use external noise sources, which are applied on pre-defined test points within a link, for channel or device compliance tests. Notable industrial standards such as PCISIG and IEEE 802.3 use such external noise injection schemes. With the support of noise source generation and simulation capabilities, we can accurately model such compliance test conditions in Advanced Link Analyzer.

Figure 77 shows the GUI entry for noise source generator. Turning Noise Source w/ Channel on makes the Advanced Link Analyzer Channel Wizard appear (see Figure 78). By default, an ideal channel (no loss with ideal impedance) is chosen. If there is a channel between the noise generator and the test point, you can click the Change Channel button and select a different channel file. Note that the Signal Source pull-down menu is set to NoiseSouce1 by default. You can also configure or modify the noise source’s relative amplitude, delay, or frequency offset in the same way as setting a crosstalk aggressor. After click OK button, the noise source can be placed in the schematic design space. A typical link topology with a noise source is shown in Figure 79.


- DN: Deterministic noise in mV. DN can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. The default DN method is uniform.
- BUN: Bound uncorrelated noise in mV. The noise characteristics selection is same as DN. The default method is Truncated Gaussian method with a Peak-to-RMS ratio of 14.
- SN: Sinusoidal noise with peak-peak amplitude in mV with specified frequency in GHz.
- RN: Random noise in mV-rms. You can further limit the RN bandwidth to the frequency you specify in GHz.
- Noise PDF: Not supported.

2.1.11. System Options
Use the System Option windows to set the simulation setting.
System tab

- Output Directory—Specify an output directory for the simulation results according to the Output Directory Mode setting.
-
Output Directory Mode
- Sync with .jne file location—Automatically sets the output directory to the directory location when you create .jne/.jneschm with the Save or Save as command.
- As specified in the Output Directory—Sets the output directory to the location specified in the Output Directory text box.
- Work Directory—Specify a work directory for the simulator according to the Work Directory Mode setting. By default, sets the work directory location as the output directory.
-
Work Directory Mode
- Sync with .jne file location—Automatically sets the work directory to the directory location when you create .jne/.jneschm with the Save or Save as command.
- As specified in the Work Directory—Sets the work directory to the location specified in the Work Directory text box.
Note: Advanced Link Analyzer can generate temporary data files during simulations. You can reduce the access time by using local storage space for storing temporary files. If you have a remote default data storage such as a network attached storage, set the working directory to local storage space to reduce simulation time. - Default Output Image Format—Set the default output image format to PNG, JPG, or GIF.
-
Generate Plots Measured with Ideal
Clock
- Yes—Always generate plots that are measured with the ideal clock.
- Do not plot when RX CDR is enabled—Skip ideal clock-based plots in RX outputs. (default value)
- Do not plot when TX scope is enabled—Skip ideal clock-based plots in TX outputs.
- Do not plot when the TX scope, RX CDR, or both are enabled—Skip ideal clock-based plots when the TX scope, RX CDR, or both are enabled.
- Jitter Sensing Sensitivity—Select the sensitivity of jitter detection when Advanced Link Analyzer performs jitter analysis (Beta feature in the current version). The selections are: Default, Ideal, Low, Medium, and High. The Default setting is equivalent to the Ideal setting.
- Jitter User Input Check—If enabled, Advanced Link Analyzer checks if the specified jitter is valid. The checker can usually be used to catch mistakes such as incorrect jitter amplitude unit. The default is Enable.
-
Default Noise
Bandwidth—Advanced Link Analyzer
uses this parameter to automatically scale the bandwidth of noise sources, when
the bandwidth setting is Auto, according
to the simulation baud rate. The default value is 0.775 of link baud rate. The
default noise bandwidth factor can be modified by editing
JNEye_Config.dat
via the NoiseBWScalar parameter. For instance, if you want to change the noise
bandwidth scaler to 2.5 times the link baud rate, the following two line text
can be specified:
%% NoiseBWScalar 2.50
- Jnu/Jrms Measurement—Enable or Disable PAM4 Jnu/Jrms measurement within a simulation. The default is Disable.
- Jnu/Jrms Measurement Option—Specify PAM4 Jnu/Jrms measurement option. The default is IEEE 802.3 120D.
- Link Optimization Option— The choices are Accuracy or Speed. The default is Accuracy. By selecting Speed, the link optimization process runs faster at the cost of possibly less optimal solutions.
Simulation tab

- Default Eye Diagram Plot Length—This parameter controls the waveform length used to construct the eye diagram when the Build Eye Diagram w/ Whole Waveform option is disabled. You can increase the length as long as the length is less than the simulation length. The default value is 4096 bits.
- Build Eye Diagram w/ Whole Waveform—If Enable is selected, Advanced Link Analyzer uses the whole simulated waveform to build the eye diagrams. If the simulation length is large, this takes more time. The default setting is Enable.
- Channel Generation Max Frequency—Sets the default maximum frequency of the channel models generated in Advanced Link Analyzer. The default value is 35 GHz.
- Channel Generation Frequency Step—Sets the default frequency step of the channel models generated in Advanced Link Analyzer. The default value is 10 MHz.
- S-parameter Caching—If Enable is selected, the last read S-parameter file is cached in memory for faster access and processing. Doing this greatly improves GUI performance when reading a multiple-lane S-parameter file with large file size. You can disable this feature.
- Sampling Rate—Specify simulation sampling rate. The default selection is 32.
-
Simulation Options—You can selectively enable or disable certain analysis features in a simulation:
- BER Contour
- Tie Interval Error (TIE): If TIE analysis is disabled, jitter decomposition is also disabled.
- Spectrum
- Waveform Output
- Transmitter Scope
Channel Model tab

-
S-Parameter Extrapolation
Options
-
Extrapolation Usage
Method—This menu selects the method used in the
extrapolation S-parameter channel model.
- Default—The S-parameter is extrapolated but capped with the amplitude value at the end (the highest frequency) of the S-parameter data.
- Always Apply—The S-parameter is extrapolated without restriction.
-
Extrapolation
Method—This menu selects the extrapolation method.
- Default—Linear extrapolation.
- IL Fitting Extrapolation—Extrapolation is done by insertion loss fitting.
-
Extrapolation Usage
Method—This menu selects the method used in the
extrapolation S-parameter channel model.
-
Crosstalk Simulation
Options
-
Crosstalk Simulation
Mode
- Default—Crosstalk is simulated using waveforms.
-
ICN—Crosstalk is simulated using the Integrated
Crosstalk Noise (ICN) method.
- ICN modeling method—ICN can be simulated using Truncated Gaussian or Gaussian method. The default is Truncated Gaussian.
- Truncated Gaussian BER crest factor—The crest factor of the truncated Gaussian distribution, calculated based on the bit error rate (BER) target value. The default BER target value is 10-6.
Numerous studies show that the ICN method more accurately reflects crosstalk's impact in high-speed serial links. For example, use the ICN method if the crosstalk sources are uncorrelated to the victim channel. If the crosstalk is correlated to the victim channel, use the waveform-based crosstalk method instead.
When simulating crosstalk using the ICN method, Intel recommends using the Truncated Gaussian method because noises are usually bounded in real systems.
-
Crosstalk Simulation
Mode
- Channel Integrity Options—Enable or disable channel integrity checking in Advanced Link Analyzer. The default setting is Enable. Choose Disable if Advanced Link Analyzer has issues opening or accessing certain S-parameter models.
-
Integrity Enforcement—
Select how the integrity enforcement is applied in the simulation. An integrity
enforcement example is causality.
- Type 1: Enforce integrity on individual channel components
- Type 2: Enforce integrity on overall channel after cascading
- Type 3: Enforce integrity both on individual channel component and after channel cascading
- Disable: Disable integrity enforcement. Default setting is Disable.
-
S-parameter Causality Check
Extrapolation Options
- Extrapolation Usage Method—Same as the same name entry in the S-Parameter Extrapolation Options. This entry only applies during S-parameter causality checking.
-
Extrapolation
Method—This menu selects the extrapolation method during
S-parameter causality checking.
- Default—Insertion loss fitting based extrapolation method.
- Last Amplitude Value—Linear extrapolation is used, but the amplitude is capped by the last amplitude value.
-
S-parameter Touchstone
Option—Touchstone 2.0 Support.
- Enable—Enable Touchstone 2.0 support. (default value)
- Disable—Disable Touchstone 2.0 support.
IBIS-AMI tab

- TX Impulse Length Limit—Selects options for controlling the length of the impulse response sent into the transmitter IBIS-AMI model. Choose Auto to let Advanced Link Analyzer determine the length. Choose Custom to set the impulse response length in the text box below the pull-down menu. The default value for custom impulse response length is 250000 samples. The default setting is Custom.
- GetWave Stimulus Options—Selects the IBIS-AMI GetWave input stimulus type. Choose Logic for the simulator to feed the GetWave input with a pre-determined logic amplitude level between +1 and -1. Choose Analog so that the input waveform can have a varying amplitude. The default setting is Logic.
- RX Impulse Length Limit—Selects options for controlling the length of the impulse response sent into the receiver IBIS-AMI model. Choose Auto to let Advanced Link Analyzer determine the length. Choose Custom to set the impulse response length in the text box below the pull-down menu. The default value for custom impulse response length is 250000 samples. The default setting is Custom.
- Storage Access Option—Selects options for how the RX IBIS-AMI model handles its output location. Choose Redirect to project output directory so that the RX IBIS-AMI output data is written to the project’s output folder. Choose No change so that there is no output redirection. Choose Custom location to specify a folder location of your choice through the directory browser. The default setting is Redirect to project output directory.
2.1.12. Project Management Functions
- Load: Loads the previously saved Advanced Link Analyzer project.
- Save: Saves the current Advanced Link Analyzer settings to the current project.
- Save as: Saves the current Advanced Link Analyzer settings to a new project.
- Reset: Resets the Advanced Link Analyzer settings.
- Archive Project: Archives the current project for archiving or sharing. See Archiving and Unarchiving Projects.
- Unarchive Project: Unarchives a previously archived project. See Archiving and Unarchiving Projects.
- Import Intel® Device Model: Imports or modifies Intel® device models. See Device Model Importer.
- System Options: See System Options.
- Exit: Exits and closes Advanced Link Analyzer.
2.1.13. Archiving and Unarchiving Projects
- All channel files
- Device and link settings
- IBIS-AMI device models

To archive a project, go to File > Archive Project. If the current project has not been saved, you are asked if you want to save the project. Project Archiver cannot proceed with an unsaved project. A file browser opens. Select where you want to save the archived project.

To unarchive a project, go to File > Unarchive Project. A file browser opens. Select where you want the archived project to be restored. If the selected folder is not empty, files with the same file names are overwritten. The unarchiver first unpacks and then makes adjustments to the simulation configurations so that the newly unarchived project can be used locally in a new computer environment.
Intel recommends comparing and checking the transceiver device models availability between the Advanced Link Analyzer installations before and after sharing. Advanced Link Analyzer’s Project Archiver does not archive transceiver model files that are supported by wrapper technology. Advanced Link Analyzer does not open or simulate a shared project if the wrapper-supported device models are not available locally.
2.1.14. Device Model Importer
With the Device Model Importer, you can add or modify device models in an Advanced Link Analyzer installation. Transceiver device models, in IBIS-AMI format, and package models, in Touchstone* S-parameter format, can be acquired by contacting My Intel support. You can then add the models to a newly installed or existing Advanced Link Analyzer. Or you can update your existing device or package models when a newer version becomes available or when your applications need to use other package models (other than the generic package models shipped with the device model).


To initiate the Device Model Importer, go to File > Import Intel® Device Model. The options when importing or modifying an Intel device model:
- Device Name: Selects a device from the Device Name menu.
- Device Type: Selects device type from the Device Type menu.
- IBIS-AMI Model File Directory: Selects where the IBIS-AMI model is stored. The Device Model Importer verifies that the device models exist.
- Package File Directory: Selects where the new package models are stored. If valid S-parameter package model files exist, the Device Model Importer populates and configures the Package Model Configuration.
- Package Model Configuration: For each package model entry (TX Minimum, TX Typical, TX Maximum, RX Minimum, RX Typical, and RX Maximum), selects an S-parameter file from the list. Click Check to verify the S-parameter configuration using the Channel Wizard GUI. When a package model is fully configured, Verified is turned on.

To import or modify a device model, all IBIS-AMI model files and all package models must be present and verified, (Verified is turned on for all configurations). Then you can click Import Model to import the device model to your Advanced Link Analyzer installation. You must restart your Advanced Link Analyzer for the new or modified models to become available and be used in analysis.
Load, Save, and Save as allow you to save or load your device import configurations for future use. For example, you can import an Intel® transceiver IBIS-AMI model with the default package models and save the Device Model Importer configuration. When your application needs a different package, you can load and modify the Device Model Importer settings to update the device models in a more convenient way.
2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists
The Analysis menu contains the following link/channel analysis functions:
- Simulate: Performs link simulation and link analysis.
- COM Analysis: Performs COM analysis on the current link or channel configuration. See COM Analysis for details.
- SNDR Analysis: Performs transmitter or channel output waveform SNDR analysis. See SNDR Analysis for details.
- Pulse Fitting Analysis: Performs transmitter or channel output waveform FIR and pulse fitting analysis. See Pulse Fitting Analysis for details.
- Jnu/Jrms Analysis: Performs transmitter or channel output waveform PAM4 Jnu/Jrms/Jeo analysis. See Jnu/Jrms/Jeo Analysis for details.
Pre-simulation and pre-analysis checklists allow you to review and update important or significant settings before launching the simulation or analysis. The changes that you apply to pre-simulation and pre-analysis checklists are applied to your link settings, unless noted otherwise in each checklist. Finally, the checklists allow you to proceed or cancel the simulation or analysis.
Pre-Simulation Checklist
Pressing the simulate icon or selecting Simulate from the Analysis pull-down menu brings up the pre-simulation checklist. This checklist allows you to change the simulation mode, output option, test point location, probe type, and jitter analysis options. It also allows changes to simulation options, where you can select certain analysis features to be performed within a simulation. Press Full Analysis Simulation to check and include all selectable analysis options in the simulation. Press Express Simulation to uncheck and exclude all selectable analysis options in the simulation.

SNDR Pre-Analysis Checklist
Clicking SNDR Calc or selecting SNDR Analysis from the Analysis pull-down menu brings up the SNDR pre-analysis checklist. This checklist allows you to change SNDR analysis methods and associated parameters.

Pulse Fitting Pre-Analysis Checklist
Clicking Pulse Fitting Calc or selecting Pulse Fitting Analysis from the Analysis pull-down menu brings up the pulse fitting pre-analysis checklist. This checklist allows you to change the FIR and pulse fitting analysis methods and associated parameters.

Jnu/Jrms Pre-Analysis Checklist
Clicking Jnu/Jrms Calc or selecting Jnu/Jrms Analysis from the Analysis pull-down menu brings up the Jnu/Jrms pre-analysis checklist. This checklist allows you to change the PAM4 Jnu/Jrms analysis method and associated parameters.

2.1.16. COM Analysis


- Set up or configure a link in the Link Designer.
- Click COM Configuration.
- Select your COM configuration from the COM Configuration menu.
- Click COM Analysis, or select Analysis > COM Analysis to perform a COM computation.
As COM is a standards driven analysis, the parameters are specified and fixed for each COM configuration. To perform a custom COM analysis, follow the process below.

- Set up or configure a link in the Link Designer.
- Click COM Configuration.
- Select COM Analysis from the COM Configuration menu.
- Select a COM configuration using the Analysis
Template menu that is closest to the your target link configuration
Example: If you want to compute COM for an OIF CEI 4.0 long reach link at 50 Gbps (PAM4), choose COM OIF-CEI-56G-LR, and then use it as a starting point for your customization.
- Edit COM parameters to suit your link configuration.
Example: Click on the fb parameter, and enter 25 for 50 Gbps OIF-CEI 4.0 long reach COM analysis. Click on the CTLE_Auto_Scale parameter, and enter 1 for automatic CTLE model scaling.
- Click the COM Analysis or select COM Analysis in the Analysis menu to perform a COM computation.
Use Save or Save as to save your customized COM configuration for future use. To load a previously saved custom COM configuration, select COM Configuration > Load from file.
The COM Analysis function shares the same COM computation engine within the Advanced Link Analyzer’s Channel View (see Advanced Link Analyzer Channel Viewer Module). The main difference is that the COM Analysis function reads channel configurations from the Link Designer and then performs channel manipulations, for example, channel model generation and channel cascading, for the COM computation. In the Channel Viewer, you have to pre-process the channels before adding them to the Channel Viewer and computing the COM.
2.2. Advanced Link Analyzer Data Viewer Module
The Advanced Link Analyzer Data Viewer displays simulation and analysis results. The Data Viewer can be started in the following ways:
- Automatically start after the completion of a simulation
- Click Data View in Advanced Link Analyzer’s main GUI
- Double-click adv_link_analyzer_data_viewer.exe
Advanced Link Analyzer uses the Data Viewer to show various types of simulation and analysis results. It can show multiple plots. Use the list box in the left panel to select the plots.

The following GUI capabilities are provided in the Data Viewer:
-
Zoom control
- In an eye diagram plot—Click Zoom In or click and drag a rectangle box to show the details of a plot. Click Zoom Out to restore the plot scale.
- Others—Right-click to bring up a menu with Zoom Out, Select, Zoom, Pan, and waveform commands.
-
Data Cursor—Select
Data Cursor to show the data cursor
boxes. You can select and drag a data cursor box with the data values shown in
the box. The data values are colored according to the data lines. Note: The Data Cursor button may not be present in certain types of plots such as waveform plots. If you move the cursor over a data point, a pop-up window shows the data value.


- Legends—Plot legends are shown when plots are generated. Use the Page-Up, Page-Down, Home, and End keys on the keyboard to move the legend box. Turn the Legends on or off to show or hide the legend box.
Within the Data Viewer, you can modify the link’s BER target using the BER Target menu. The Advanced Link Analyzer Data Viewer recalculates the jitter and the eye-opening height and width dynamically, because the Advanced Link Analyzer Simulation Engine has pre-calculated the results at different BER targets in the simulation range.
Use the Colormap menu to change the color map of eye diagrams within the Data Viewer. Advanced Link Analyzer provides eight different color maps that you can choose from, depending on your analysis purpose and visual preferences. The color maps can be divided into two groups:
- Logarithmic Color Scale—Default, Blue, Heat, and Bone
- Linear Color Scale—Default Linear, Blue Linear, Heat Linear, and Bone Linear
The logarithmic color scale provides good visual performance in displaying low probability data points such as the low BER portion of an eye diagram. The linear color scale is more suitable for showing minor differences in close-range data values. The Blue/Blue Default Linear is good for showing deterministic simulation results when no jitter or noise is present. Advanced Link Analyzer automatically chooses the most suitable color map based on the type or configuration of a simulation. The default color map is either Default or Blue.
- When Save Selected Plot is selected, the image of the currently selected plot is generated and saved. An image file of the currently selected plot is saved in the format specified in the Image Output (in the Options window).
- When Save All Plots is selected, the images of all plots are generated and saved to the folder you specify. Image files of all plots are saved in the format specified in the Image Output (in the Options window).
- When Save Waveform is selected, you specify the file name and location to save the waveform data. Note that you must first select a waveform plot to save the waveform data.
- When Save Simulation Report is selected, a simulation report in XML format is generated and saved to the folder you specify. To share the simulation report, you must include the generated XML file (for example, Your_Sim.xml) as well as the folder (for example, Your_Sim_SimResults) for the simulation report to display correctly.
- When View Simulation Report is selected, a media-rich simulation report in XML format is generated and displayed in an XML viewer. You can use any XML viewer to view the simulation report.

The Advanced Link Analyzer Data Viewer Module shows the following types of simulation results:
Probability Density Function (PDF) Eye Diagram
This scope shows the PDF eye diagram (with probability color map), horizontal histogram at slicer voltage level (fixed at 0 V in the Advanced Link Analyzer), vertical histogram at Ideal Clock or CDR sampling phase, and eye diagram opening width and height information. Device settings such as transmitter pre-emphasis/FIR setting and receiver equalization settings are shown in the text display area below the plots.

Cumulative Distribution Function (CDF) Eye Diagram
This scope shows the CDF eye diagram (with probability color map), horizontal BER bathtub curve (fixed at 0 V in Advanced Link Analyzer), vertical BER bathtub curve (at ideal clock or CDR sampling phase), and eye diagram opening width and height. The eye diagram compliance mask is plotted when it is enabled and applicable.

BER Contour
The Data Viewer shows the BER contour and eye diagram opening width and height. The eye diagram compliance mask is plotted when it is enabled and applicable.

Q-Factor Curve
A different view of the BER bathtub curve using Q-factor.


Transmitter Reference Clock Phase Noise Analysis and Plots
Advanced Link Analyzer plots the phase noise power spectrum through the link. The transmitter reference clock’s phase noise travels through the transmitter PLL, emulated scope, channel, and the RX CDR. In this process, phase noise is shaped by the TX PLL, scope (pass through only), and RX CDR. At the same time, the transmitter and receiver also generate their own intrinsic jitter which is mixed with the jitter caused by the shaped phase noise. The Advanced Link Analyzer simulation engine processes and records the phase noise characteristics transition and the amount of random jitter the device contributed internally.


TX pre-emphasis, de-emphasis, or FIR coefficients are displayed with the transmitter output.
The CTLE setting is displayed for the test point after CTLE.
DFE coefficients are displayed for the test point after DFE.
Time Interval Error (TIE) Plots
TIE plots capture the time differences between the waveform transition time (across data sensing threshold) and ideal/reference waveform transition time. If Jitter Analysis is enabled and the simulation mode is Hybrid, jitter analysis results are displayed under the TIE plot.

Time Interval Error (TIE) Histogram Plots
This plot shows the histogram of TIE records. Five histograms are displayed:
- All transitions
- Rising edge transitions
- Falling edge transitions
- Even-bit edge transitions
- Odd-bit edge transitions
If Jitter Analysis is enabled and the simulation mode is Hybrid, jitter analysis results are displayed under the TIE plot.

Waveform Spectrum Plots
The frequency spectrum of the waveform is plotted.

Rise/Fall Time Histogram Plots
Advanced Link Analyzer calculates the rise/fall time across the bit time boundary.

Waveform
For Hybrid mode or Full Waveform mode simulations, a waveform of each test point is plotted. The Data Viewer, by default, displays the final 4096 bits of the waveform. Use the following settings to specify the location of the waveform:
-
Plot—The Plot menu specifies the reference location of
the simulated waveform. It has the following choices:
- Beginning—plots the waveform from the beginning of the simulation.
- End—displays the last part of simulated waveform.
- Custom—you specify the starting and ending bit locations.
- Length—If the Plot selection is Beginning or End, the length of waveform (in bits) to be plotted is specified.
- From/to—If the Plot selection is Custom, these two entries specify the start and end points of waveform (in bits) to be plotted.
Simulation Report
A simulation report is shown in the last page of the output windows. The simulation report is organized as follows:
- Simulation Log—If link optimization is performed, the link optimization FOM (figure of merit) transition is reported here.
- User-Defined Link
Configuration—Link configuration is listed in this section which includes:
- Transmitter Reference clock configuration
- Transmitter configuration
- Receiver configuration
- Channel configuration
- Simulation Record—Report the simulation results at each test points
- Simulation Result
Summary
- TX-FIR/Pre-emphasis, RX CTLE, and DFE Settings
- Eye Diagram Widths, Heights, and Margins to the eye diagram mask
---------------------------------------------------------------
Simulation Log
<current date>
Link Optimization Mode: TX = Manual, RX = Manual
Link Optimization FOM: Area
Advanced Link Analyzer Simulation Report
Simulation Engine Version: <current version>
**************************** User-Defined Link Configuration ********************************
Project Name: Demo
Simulation Mode: Hybrid
Data Rate: 8 Gbps
Simulation Length: 65536 bits
Test Pattern: PRBS-23
BER Target: 1e-012
FEC Method: Off
Compliance Mask:
Compliance Mask Type: PCI-Express 8GT
Transmitter Reference Clock:
Frequency: 100 MHz
Configuration Method: Option 2
Phase Noise Profile [Freq (Hz), Amplitude (dBc)]:
[10, -68.5508]
[10.2723, -68.7007]
[10.552, -69.0572]
[10.8393, -69.5463]
[11.1344, -69.8799]
[11.4376, -70.1791]
...
[8.98118e+007, -141.908]
[9.22571e+007, -141.914]
[9.47691e+007, -141.916]
[9.73494e+007, -141.9]
[1e+008, -142.145]
Phase Noise Fmin: 1 Hz
Phase Noise Fmax: 1e+008 Hz
Spur Profile [Freq (Hz), Amplitude (dBc)]:
[100000, -80]
[1e+006, -90]
[1e+007, -96]
Periodic Jitter:
Method: Triangle
Frequency: 0 Hz
Amplitude: 0 ps
Hershey Key: 0.05
Sharkfin Key: 0.5
Transmitter: Stratix V GX
Package: Stratix V GX
Supply Voltage: Default
Vcm: Default
PLL Type: Enable
PLL Bandwidth: SVGX_TXPLL_Low
Divider Setting: L = 1, M = 40, N = 1
VOD: 0.8 V
TX EQ/FIR Mode: Manual
Initial TX FIR Coefficients = [-4, Main Tap, 2, 0]
PVT Condition:
PVT: Typical
Jitter & Noise Configuration:
Jitter/Noise Input Method: Jitter/Noise Component Method
ISI = 0 ps
DCD = 1.5 ps
BUJ = 4 ps
RJ = 1 ps-rms
SJ = 0 ps at 0 MHz
DN = 0 mV
BUN = 0 mV
RN = 0 mV-rms
Receiver: PCI-Express 8GT
Package: PCI-Express 8GT
Supply Voltage: Default
CTLE Mode: 10dB
CDR Type: Alexander
CDR Bandwidth: Generic_CDR_Medium_BW
DFE Enable: Enable
DFE Mode: Auto
PVT Condition:
PVT: Typical
Jitter & Noise Configuration:
Jitter/Noise Input Method: Jitter/Noise Component Method
DJ = 7 ps
BUJ = 0 ps
RJ = 1.55 ps-rms
DN = 0 mV
BUN = 0 mV
RN = 0 mV-rms
Channel Configuration:
[1] File Name: Demo.s12p
Channel Type: Loss
Port Configuration: 2
Lane Number: 2
Port Number: 12
Aggressor ID: 1
Aggressor Relative Amplitude: 1
Aggressor Delay: 0
Aggressor Frequency Offset: 0 ppm
Aggressor Signal Source Type: Inline
Causality Enforcement: No
Passivity Enforcement: No
[2] File Name: Demo.s12p
Channel Type: FEXT
Port Configuration: 2
Lane Number: 2
Port Number: 12
Aggressor ID: 1
Aggressor Relative Amplitude: 1
Aggressor Delay: 0
Aggressor Frequency Offset: 0 ppm
Aggressor Signal Source Type: Inline
Causality Enforcement: No
Passivity Enforcement: No
[3] File Name: Demo.s12p
Channel Type: FEXT
Port Configuration: 2
Lane Number: 2
Port Number: 12
Aggressor ID: 2
Aggressor Relative Amplitude: 1
Aggressor Delay: 0
Aggressor Frequency Offset: 300 ppm
Aggressor Signal Source Type: Inline
Causality Enforcement: No
Passivity Enforcement: No
****************************************************************************************************************
******************************************* Simulation Record **************************************************
Transmitter Reference Clock Random Jitter = 6.37602 ps-RMS (up to Reference Clock Frequency)
TX with Ideal Clock
Stratix V GX VOD: 40 TX EQ: Pre-Tap 1 = -4 Post-Tap 1 = 2 Post-Tap 2 = 0
Eye Width=0.17UI(21.240ps), Eye Height= 363.49mV, Jitter(p-p)=0.83UI (103.760ps) at BER<10^-12
BER Eye Width (UI) Eye Height (V)
10^-3 0.622 0.632
10^-4 0.545 0.62
10^-5 0.48 0.607
10^-6 0.424 0.593
10^-7 0.373 0.574
10^-8 0.326 0.552
10^-9 0.284 0.524
10^-10 0.243 0.486
10^-11 0.205 0.431
10^-12 0.17 0.363
10^-13 0.136 0.288
10^-14 0.103 0.21
10^-15 0.0713 0.132
10^-16 0.041 0.0529
10^-17 0.00977 0
10^-18 0 0
10^-19 0 0
10^-20 0 0
10^-21 0 0
Random Jitter= 6.29 ps-RMS
Random Noise= 0 mV-RMS
TX Scope with Recovered Clock
Stratix V GX VOD: 40 TX EQ: Pre-Tap 1 = -4 Post-Tap 1 = 2 Post-Tap 2 = 0
Eye Width=0.83UI(104.126ps), Eye Height= 636.61mV, Jitter(p-p)=0.17UI (20.874ps) at BER<10^-12
BER Eye Width (UI) Eye Height (V)
10^-3 0.915 0.642
10^-4 0.899 0.64
10^-5 0.888 0.639
10^-6 0.877 0.638
10^-7 0.868 0.638
10^-8 0.86 0.638
10^-9 0.853 0.638
10^-10 0.845 0.638
10^-11 0.839 0.637
10^-12 0.833 0.637
10^-13 0.827 0.637
10^-14 0.821 0.637
10^-15 0.816 0.637
10^-16 0.812 0.637
10^-17 0.807 0.637
10^-18 0.802 0.637
10^-19 0.798 0.636
10^-20 0.794 0.636
10^-21 0.788 0.636
Random Jitter= 0.985 ps-RMS
Random Noise= 0 mV-RMS
CH
Eye Width=0.00UI( 0.000ps), Eye Height= 0.00mV, Jitter(p-p)=1.00UI (125.000ps) at BER<10^-12
BER Eye Width (UI) Eye Height (V)
10^-3 0 0
10^-4 0 0
10^-5 0 0
10^-6 0 0
10^-7 0 0
10^-8 0 0
10^-9 0 0
10^-10 0 0
10^-11 0 0
10^-12 0 0
10^-13 0 0
10^-14 0 0
10^-15 0 0
10^-16 0 0
10^-17 0 0
10^-18 0 0
10^-19 0 0
10^-20 0 0
10^-21 0 0
Random Jitter= 6.29 ps-RMS
Random Noise= 0 mV-RMS
CTLE CDR with Recovered Clock
CTLE Setting: 10dB
Eye Width=0.44UI(55.298ps), Eye Height= 41.99mV, Jitter(p-p)=0.56UI (69.702ps) at BER<10^-12
BER Eye Width (UI) Eye Height (V)
10^-3 0.689 0.0562
10^-4 0.637 0.0512
10^-5 0.586 0.0485
10^-6 0.547 0.047
10^-7 0.521 0.0459
10^-8 0.502 0.045
10^-9 0.484 0.0444
10^-10 0.47 0.0437
10^-11 0.455 0.0426
10^-12 0.442 0.042
10^-13 0.431 0.0411
10^-14 0.42 0.0405
10^-15 0.409 0.0398
10^-16 0.399 0.0389
10^-17 0.391 0.0385
10^-18 0.381 0.0376
10^-19 0.372 0.037
10^-20 0.363 0.0363
10^-21 0.355 0.0356
Random Jitter= 1.84 ps-RMS
Random Noise= 0 mV-RMS
DFE CDR with Recovered Clock
DFE Coefficients = [ -19.73,] mV
Eye Width=0.41UI(51.392ps), Eye Height= 60.06mV, Jitter(p-p)=0.59UI (73.608ps) at BER<10^-12
BER Eye Width (UI) Eye Height (V)
10^-3 0.616 0.0881
10^-4 0.567 0.0812
10^-5 0.532 0.0763
10^-6 0.507 0.0726
10^-7 0.485 0.0697
10^-8 0.467 0.0672
10^-9 0.451 0.065
10^-10 0.438 0.063
10^-11 0.424 0.061
10^-12 0.411 0.0601
10^-13 0.4 0.0581
10^-14 0.39 0.0571
10^-15 0.379 0.0554
10^-16 0.369 0.0542
10^-17 0.36 0.0529
10^-18 0.351 0.0517
10^-19 0.343 0.0505
10^-20 0.333 0.049
10^-21 0.325 0.0485
Random Jitter= 1.84 ps-RMS
Random Noise= 0 mV-RMS
*******************************************************************************************************
Simulation Result Summary
**************************** TX-FIR/Pre-emphasis, RX CTLE and DFE Settings ****************************
Pre-emphasis : Pre-tap1 main-tap Post-tap1 Post-tap2
Levels : -4.000 0.000 2.000 0.000
Coeff : -0.087 0.962 -0.041 0.000
RX Setting : CTLE Setting: 10dB
DFE : tap1
****************************************************************************************************************
******************************** Eyediagram Width and Eyediagram Height ****************************************
Eye Width Eye Height Eye Opening
[UI] [V] Area [UI*V]
TX Output (Scope) : 0.833 0.637 0.530
TX Output : 0.170 0.363 0.062
Channel Output : 0.000 0.000 0.000
CTLE Output (Retimed) : 0.442 0.042 0.019
DFE Output (Retimed) : 0.411 0.060 0.025
Eye Mask Margin : 0.111 0.035
****************************************************************************************************************
Simulation Time: 0:04:27.70
Simulation Time: 0:04:34.55
--------------------------------------------------------------------
Use the Data Viewer to see previous Advanced Link Analyzer simulation results by clicking Load. A file browser opens and helps you find the master Advanced Link Analyzer output data file (JNEye_Sim_Result.jneomlist) for individual simulations. Advanced Link Analyzer simulation output data is usually located in a file directory that has the same name as the saved project name. For example, if the saved Advanced Link Analyzer configuration file is Demo1.jne, the previous simulation results are stored a directory named “Demo1”. Navigate to the directory, select the JNEye_Sim_Result.jneomlist file, and open it to load the simulation data.

CSV Eye Diagram Import and Analysis
Eye diagram data generated from other simulation tools or measurement instruments can be imported and analyzed in Advanced Link Analyzer’s Data Viewer. After valid eye diagram data is imported, the Data Viewer performs BER bathtub and eye height/width analysis. The Data Viewer is equipped with options to repair or enforce the integrity of the imported CSV data.
Two CSV eye diagram data formats are supported:
CSV Eye Diagram Data Format 1: Format 1 includes a predefined header section which is followed by a 2-dimension data array.
Required headers for the CSV eye diagram data:
- Datarate: Datarate of the measured eye diagram
- Optimum phase: Phase where the eye height opening is optimal
- Eye measured at vertical step: Amplitude where the eye width is measured
- Header text: Name of the measurement data
- Dimension X-axis: X-axis dimension of the measured data
- Dimension Y-axis: Y-axis dimension of the measured data
- START: Starting point of eye diagram data
Example of Format 1 eye diagram data:
====================================================================== >>>>,Datarate Ch 0 phy 0 : ,24576,Mbps >>>>,Horizontal Eye Opening Ch 0 phy 0 : ,35,phases >>>>,Horizontal Eye Opening Ch 0 phy 0 : ,0.55,UI >>>>,Optimum Phase Ch 0 phy 0 : ,85 >>>>,Eye measured at vertical step : , 2 >>>>,Vertical Eye Opening Ch 0 phy 0 : ,45,steps >>>>,Area Eye Opening Ch 0 phy 0 : ,1139 >>>>,Header Text,Phy 0 Ch 0 >>>>,Dimension X-axis,64 >>>>,Dimension Y-axis,127 >>>>,============================================================================================= >>>>, >>>>,START, >>>>,Phase ,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116, >>>>,63 ,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00, >>>>,62 ,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1 … … >>>>,-62 ,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00, >>>>,-63 ,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00, ======================================================================
Multiple CSV eye diagram data points can be included in a single CSV file, and the Data Viewer displays and analyzes each individually.

CSV Eye Diagram Data Format 2: Format 2 includes a predefined header section which is followed by a 2-dimension data array.
Required headers for the CSV eye diagram data:
- Device revision: Name of the device or tool
- Data Rate Mbps: Data rate in Mbps
- Eye Center Phase: Eye diagram center phase setting
- PAM4 Eye: PAM4 eye diagram data (only false is supported in this version)
- Pre-emphasis 1st post-tap: Transmitter equalization setting
- Pre-emphasis pre-tap: Transmitter equalization setting
- Pre-emphasis 2nd post-tap: Transmitter equalization setting
- Pre-emphasis 2nd pre-tap: Transmitter equalization setting
- CTLE EQ gain: Receiver CTLE setting
- Equalization mode: Operating mode of the device
- CTLE AC gain: Receiver CTLE setting
- VGA DC gain: Receiver VGA setting
- DFE nth tap: Receiver DFE setting
Example of Format 2 eye diagram data:
====================================================================== Device Revision,demo Data Rate Mbps,25800 Eye Width / Eye Height,48/71 Eye Center Phase,110 Phase Interval,1 Vertical Interval,1 PAM4 Eye,false VOD Control,28 Pre-emphasis 1st Post-Tap,0 Pre-emphasis Pre-Tap,0 Pre-emphasis 2nd Post-Tap,N/A Pre-emphasis 2nd Pre-Tap,N/A CTLE EQ Gain,0 Equalization Mode,Continuous adaptation CTLE AC Gain,0 VGA DC Gain,4 DFE 1st Tap,Off DFE 2nd Tap,0 DFE 3rd Tap,0 … Phase Step,Vertical Step,Tested Bits,Error Bits,BER 24,-1,40000000,4477278,0.11193 24,0,40000000,3557605,0.08894 24,2,80000000,10165154,0.12706 … … 81,1,80000000,4553509,0.056919 82,-1,80000000,9133868,0.11417 82,0,40000000,3539527,0.088488 82,1,80000000,9213139,0.11516 83,-1,40000000,6962613,0.17407 83,0,40000000,5590098,0.13975 ======================================================================

FEC
The Forward Error Correction (FEC) Designer window lets you select one of the supported FEC schemes to be simulated on the CSV eye diagram data. Examples: FireCode, RS(528, 514), and RS(544, 514)
Options
The Options window lets you configure the Data Viewer. There are two option tabs.
CSV Eye Options tab
- BER/CDF Eye Enforcement: When importing CSV eye diagram data generated from simulation tools or extracted from measurement instruments, you may need to correct measurement errors or unwanted noises. The Data Viewer provides three options: Strong, Eye Center, and Disable. In Strong mode, the eye diagram data is pre-processed to enforce a monotonic BER (bit error rate) trend from the eye diagram center for the whole eye diagram. In Eye Center mode, monotonic BER enforcement is performed only on the vertical and horizontal slices associated with the eye diagram center point. In Disable mode, no enforcement is applied. The default selection is Disable.
- CSV Eye Floor (unit: –log10): This sets the lowest BER of the imported CSV eye diagram data when the probability is 0. Because most eye diagram data is captured in a limited amount of time, the lowest probability when a bit error is detected and recorded in the eye diagram data is usually large. By setting BER floor to a small value, you allow BER extrapolation and analysis. The BER floor can be set from 10-1 to 10-20 in –log10 scale. The default BER floor is 10-13.
- x-axis Display Mode: The x-axis of the eye diagram can be set to either Auto Reset or Data Phase. In Auto Detect mode, the x-axis starts at 0 and ends at twice the UI sampling rate. In Data Phase mode, the x-axis is the phase information coming from the VCS data file. The default setting is Data Phase mode.
System Options tab
Image Output Type: This selects the image output format. The selections include: PNG, JPG, GIF, and Disable. The default setting is PNG.
Load, Save, Save as
These buttons load or save the Data Viewer settings. Note that only settings in the Options windows (not simulation data and CSV eye diagram data) are saved.
2.3. Advanced Link Analyzer Channel Viewer Module
The Advanced Link Analyzer Channel Viewer provides a convenient way of observing and comparing channel characteristics. The following types of channel characteristics, which are represented by Touchstone S-parameter format, can be displayed in the Channel Viewer:
- Standard-mode / Single-ended S-parameter—for example, S11, S12, S21
- Mixed-mode / Differential S-parameters—for example: Sdd11, Sdd21, Scd21
- Frequency Domain Plots: Amplitude and propagation/group delay plots
- Time Domain Plots: Impulse responses and single-bit responses
Channel Viewer also provides channel compliance checks and channel analysis. Use these features to observe a channel's characteristics and its associated signal integrity matrices.

There are four ways to start Advanced Link Analyzer Channel Viewer:
- Double-click the adv_link_analyzer_channel_viewer.exe icon in Windows Explorer.
- Click Channel Viewer in the Advanced Link Analyzer Control Module's Tool menu to start a new Channel Viewer.
- Click Channel Viewer in the Advanced Link Analyzer Control Module’s Channel tab. When you start Advanced Link Analyzer Channel Viewer from the Channel tab, the channel information from the link configuration is transferred to the Channel View and is ready for viewing.
- Select a channel in Advanced Link Analyzer Control Module’s Link Designer, right-click, and select View in Channel Viewer.
The following figure shows the Advanced Link Analyzer Channel Viewer user interface. The viewer has six panels that allow you to select and control the channel plot options.

The following figure shows the Channel Viewer GUI panel partitions.

2.3.1. Channel Plot Panel
This panel contains the Channel Viewer and Plot Selector. The Advanced Link Analyzer Channel Viewer shows the characteristics of the channels in the channel list with the plot options specified. Use the Channel Viewer to plot channels with different options and browse the plots. Use the Plot Selector to choose one of the existing plots.
The Channel Viewer provides the following GUI capabilities:
- Zoom In, Zoom Out, Pan, Data Select—Right-click on the Channel Plot panel to select one of these functions. To zoom in on the plot, select Zoom In and then click and drag a rectangle box to show the details of the plot. To zoom out, select Zoom Out. Up to ten previous scalings are saved, so you can restore older versions by clicking Zoom Out more than once. To pan over the plot, select Pan and then click and drag the plot.
- Data Cursor—Turn on Data Cursor to show the data cursor boxes. You can select and drag a data cursor box with the data values shown in the box. The data values are colored according to the data lines.
- Legends—Plot legends are shown when plots are generated. Use the Page-Up, Page-Down, Home, and End keys on the keyboard to move the legend box. You can also turn Legends on or off to show or hide the legend box.
2.3.2. Channel List Panel
This panel maintains the channels of interest. Channels can be either transferred from the Advanced Link Analyzer Control Module or added within the Channel Viewer. The channel list in the Channel Viewer is independent from the list in Advanced Link Analyzer Control Module. Therefore, you can add and delete channels in the Channel Viewer without affecting the simulation configuration in the Advanced Link Analyzer Control Module.
An S-parameter channel component, such as a connector, cable, or backplane, can be described by the following parameters or information as shown in the Channel List:
- ID—Sequence or location of the channel component.
- Channel Name—An S-parameter file that describes the channel component. The S-parameter file can be 4-port, 8-port, 12-port, 16-port, and so forth.
- Type—Specify the type of channel characteristics in the link simulation. The type of channel characteristics can be insertion loss (Loss), far-end crosstalk (FEXT), or near-end crosstalk (NEXT). Change the channel type by selecting the channel from the channel list and then selecting the appropriate channel type from the Type menu.
- Port Configuration (Port Cfg)—Depending on the S-parameter measurement condition, the port configuration can be one of the types shown in the following figures. You can change the port configuration of an S-parameter by using the menu below the Port Configuration list box.




- Lane ID (Lane)—For multiple channel/lane S-parameters (8-port and above) a channel/lane must be chosen for link simulations. For example, the above figures show a 12-port 3-lane S-parameter. After loading the channel file, Advanced Link Analyzer assigns the middle lane as the default simulating channel (or victim channel for crosstalk simulations). You can change the Lane ID by using the menu below the Lane ID list box. For 2-port or 4-port S-parameter models, the Lane ID is ignored.
-
Aggressor ID (Agg ID)—For multiple channel/lane
S-parameters simulating crosstalk effects, you must specify the aggressor
location. For example, the above figures show four possible crosstalk
configurations from a 12-port S-parameter model. Use the menu below the
Aggressor ID list box to change the aggressor location. For Victim channel (Loss
type), the Aggressor ID field is ignored. Note: The Aggressor ID is indexed in a way that excludes the victim lane. For example, in a 12-port S parameter, there are three lanes. The middle lane (Lane ID 2) is the victim lane. The two aggressor channels have Aggressor IDs 1 and 2, not 1 and 3.
- Relative Amplitude (Rel Amp)—You can manually adjust the amplitude of crosstalk (NEXT/FEXT) channel components. The amplitude adjustment is reflected in the channel plots and the channel compliance results. The amplitude adjustment is in a linear scale.
The Channel List Panel contains the following command buttons:
- Add Transmission/NEXT/FEXT/2-port Return Loss—Open a file browser and locate the specified channel model files.
- Edit—Open the Channel Wizard where you can change the selected channel or edit its properties, for example, port configuration, crosstalk aggressor, and so on.
- Delete—Delete the selected channel.
- Clear—Delete all channel components.
-
Import Channel List—Import channels listed in a
.csv file into the channel list for batch channel
compliance tests. The .csv file must be in the following
format:
- Each line specifies a channel file.
- Each channel file is specified with the following information separated
by a comma (,):
- Full file name (include path)
- Channel type
- Port configuration
- Lane
- Crosstalk aggressor
- Crosstalk aggressor amplitude scale
- For compliance tests with crosstalk components, the list must start with the victim channel followed by the crosstalk components.
- For batch compliance tests with multiple groups of victim and crosstalk channel components, each group must start with the victim channel and end by either the end-of-list or a victim channel.
The following is an example of a channel list that contains three groups of victim and crosstalk channels:
D:\Ci_2\Cable_BKP_28dB_0p575m_more_isi_thru1.s4p,Loss,2,1,1,1 D:\Ci_2\Cable_BKP_28dB_0p575m_more_isi_f1.s4p,FEXT,2,1,1,1 D:\Ci_2\Cable_BKP_28dB_0p575m_more_isi_f2.s4p,FEXT,2,1,1,1 D:\Ci_2\Cable_BKP_28dB_0p575m_more_isi_f3.s4p,FEXT,2,1,1,1 D:\Ci_2\Cable_BKP_16dB_0p575m_more_isi_t.s4p,Loss,2,1,1,1 D:\Ci_2\Cable_BKP_16dB_0p575m_more_isi_f1.s4p,FEXT,2,1,1,1 D:\Ci_2\Cable_BKP_16dB_0p575m_more_isi_f2.s4p,FEXT,2,1,1,1 D:\Ci_2\Cable_BKP_16dB_0p575m_more_isi_f3.s4p,FEXT,2,1,1,1 D:\C2\CaBP_BGAVia_Opt2_28dB_THRU.s4p,Loss,2,1,1,1 D:\C2\CaBP_BGAVia_Opt2_28dB_FEXT2.s4p,FEXT,2,1,1,1 D:\C2\CaBP_BGAVia_Opt2_28dB_FEXT3.s4p,FEXT,2,1,1,1 D:\C2\CaBP_BGAVia_Opt2_28dB_FEXT4.s4p,FEXT,2,1,1,1 D:\C2\CaBP_BGAVia_Opt2_28dB_FEXT5.s4p,FEXT,2,1,1,1 D:\tg7_Thru_B56.s4p,Loss,2,1,1,1 D:\tg7_FEXT_B23.s4p,FEXT,2,1,1,1 D:\tg7_FEXT_B89.s4p,FEXT,2,1,1,1 D:\tg7_FEXT_C23.s4p,FEXT,2,1,1,1 D:\tg7_FEXT_C56.s4p,FEXT,2,1,1,1 D:\tg7_FEXT_C89.s4p,FEXT,2,1,1,1
- Export Channel List—Export the channels in the channel list to a .csv file.
- Move Up (/\)—Move the selected channel component or test point up toward the transmitter side.
- Move Down (\/)—Move the selected channel component or test point down toward the receiver side.
2.3.3. Plot Option Panel
The Plot Option panel has the following buttons:
- Load—Loads the channel list and channel viewer configuration.
- Save—Saves the current channel list and channel viewer configuration.
- Save as—Saves the current channel list and channel viewer configuration in a new configuration file.
- Save Plot as Image—Saves the selected plot as an image file.
- Options—Opens the Channel Viewer Options window.
- Plot—Plots the channel characteristics or performs the selected analysis.
2.3.3.1. S-parameter Mode Panel

- Mixed-Mode Selector Panel—This panel allows you to select and plot an S-parameter’s mixed-mode characteristics. The Advanced Link Analyzer Channel Viewer can convert standard-mode (that is, single-ended) frequency responses into its differential–pair format (mixed-mode) frequency responses. For high-speed serial links with differential signaling scheme, Intel recommends you observe channel characteristics and performance in mixed-mode.
- Standard-Mode Selector Panel—This panel allows you to select and plot an S-parameter’s standard-mode characteristics. An open 4-port single-ended S-parameter is supported in this plot mode.
2.3.3.2. Plot Configuration Panel
The Channel Analysis and Compliance Module menu controls the channel characteristics plotting modes:
- Off—Channel Viewer plots channel characteristics as directed by your configuration. In the mode, you can plot frequency responses, impulse responses, and single bit responses. This is the default Channel Viewer plotting mode.
-
Channel Analysis—Channel Viewer performs a sequence
of operations to calculate and show channel performance in terms of ILD (Insertion Loss
Deviation), RL (Return Loss), ICR (Insertion Loss to Crosstalk Ratio), and Crosstalk Noise
calculations. This allows you to determine the wellness of the channels.
Channel Analysis supports customizable compliance masks for IL, ILD, RL, ICN, and ICR. This feature can be used to perform custom channel compliance checks for proprietary links. When Custom is selected, you can enter channel compliance mask definition in each text box with the format: frequency (Hz) and amplitude (dB). You can also load a predefined custom channel compliance mask definition from a file.
- 10GBASE-KR Channel Compliance—Channel Viewer performs channel compliance checks per 10 Gbps Ethernet over backplane (IEEE 802.3ap, 10GBASE-KR) standards.
- OIF CEI-28G-SR 3.0 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-28G-SR 3.0 standards.
- OIF CEI-25G-LR 3.0 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-25G-LR standards.
- OIF CEI-28G-MR 3.1 Channel Compliance—Channel Viewer performs channel compliance checks per OIF CEI-28G-MR standards.
- COM 802.3 100GBASE-CR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-CR4 standards.
- COM 802.3 CAUI-4 C2C Channel Compliance Channel viewer performs channel compliance checks per IEEE 802.3 CAUI-4 C2C standards.
- COM 802.3 100GBASE-KP4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KP4 standards.
- COM 802.3 100GBASE-KR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KR4 standards.
- COM Analysis—Channel Viewer performs a sequence of operations to calculate and show channel performance based on COM (Channel Operating margin) methodology. Channel Viewer allows you to customize parameters that configure COM calculation.
- COM 802.3 CAUI-4 C2C Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 CAUI-4 C2C standards.
- COM 802.3 200GAUI-4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GAUI-4 standards.
- COM 802.3 400GAUI-8 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 400GAUI-8 standards.
- COM 802.3 200GAUI-4 C2M Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GAUI-4 C2M standards.
- COM 802.3 400GAUI-8 C2M Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 400GAUI-8 C2M standards.
- COM 802.3 200GBASE-CR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GBASE-CR4 standards.
- COM 802.3 100GBASE-CR2 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-CR2 standards.
- COM 802.3 50GBASE-CR Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 50GBASE-CR standards.
- COM 802.3 200GBASE-KR4 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 200GBASE-KR4 standards.
- COM 802.3 100GBASE-KR2 Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 100GBASE-KR2 standards.
- COM 802.3 50GBASE-KR Channel Compliance—Channel viewer performs channel compliance checks per IEEE 802.3 50GBASE-KR standards.
- COM OIF-CEI-56G-LR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-56G-LR standards.
- COM OIF-CEI-56G-MR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-56G-MR standards.
- ERL-CH 802.3 50GBASE-KR Effective Return Loss (ERL) Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 50GBASE-KR standards.
- ERL-CH 802.3 100GBASE-KR2 ERL Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 100GBASE-KR2 standards.
- ERL-CH 802.3 200GBASE-KR4 ERL Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 200GBASE-KR4 standards.
- ERL-CH 802.3 50GBASE-CR ERL Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 50GBASE-CR standards.
- ERL-CH 802.3 100GBASE-CR2 ERL Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 100GBASE-CR2 standards.
- ERL-CH 802.3 200GBASE-CR4 ERL Compliance—Channel viewer performs channel return loss compliance checks per IEEE 802.3 200GBASE-CR4 standards.
- ERL-SI 802.3 50GBASE-KR ERL Compliance—Channel viewer performs transmitter and receiver return loss compliance checks per IEEE 802.3 50GBASE-KR standards.
- ERL-SI 802.3 100GBASE-KR2 ERL Compliance—Channel viewer performs transmitter and receiver return loss compliance checks per IEEE 802.3 100GBASE-KR2 standards.
- ERL-SI 802.3 200GBASE-KR4 ERL Compliance—Channel viewer performs transmitter and receiver return loss compliance checks per IEEE 802.3 200GBASE-KR4 standards.
- ERL-SI-RX 802.3 50GBASE-CR ERL Compliance—Channel viewer performs receiver return loss compliance checks per IEEE 802.3 50GBASE-CR standards.
- ERL-SI-RX 802.3 100GBASE-CR2 ERL Compliance—Channel viewer performs receiver return loss compliance checks per IEEE 802.3 100GBASE-CR2 standards.
- ERL-SI-RX 802.3 200GBASE-CR4 ERL Compliance—Channel viewer performs receiver return loss compliance checks per IEEE 802.3 200GBASE-CR4 standards.
- COM 802.3 100GBASE-KR1 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 100GBASE-KR1 standards draft.
- COM 802.3 200GBASE-KR2 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 200GBASE-KR2 standards draft.
- COM 802.3 200GBASE-KR2 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 200GBASE-KR2 standards draft.
- COM 802.3 400GBASE-KR4 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 400GBASE-KR4 standards draft.
- COM 802.3 100GBASE-CR1 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 100GBASE-CR1 standards draft.
- COM 802.3 200GBASE-CR2 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 200GBASE-CR2 standards draft.
- COM 802.3 400GBASE-CR4 Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 400GBASE-CR4 standards draft.
- COM 802.3 100GAUI-1 C2C Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 100GAUI-1 C2C standards draft.
- COM 802.3 200GAUI-2 C2C Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 200GAUI-2 C2C standards draft.
- COM 802.3 400GAUI-4 C2C Channel Compliance—Channel viewer performs channel compliance checks per current trending IEEE 802.3 100GAUI-4 C2C standards draft.
- ERL-CH 802.3 100GBASE-KR1 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 100GBASE-KR1 standards draft.
- ERL-CH 802.3 200GBASE-KR2 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 200GBASE-KR2 standards draft.
- ERL-CH 802.3 400GBASE-KR4 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 400GBASE-KR4 standards draft.
- ERL-SI 802.3 100GBASE-KR1 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 100GBASE-KR1 standards draft.
- ERL-SI 802.3 200GBASE-KR2 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 200GBASE-KR2 standards draft.
- ERL-SI 802.3 400GBASE-KR4 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 400GBASE-KR4 standards draft.
- ERL-CH 802.3 100GBASE-CR1 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 100GBASE-CR1 standards draft.
- ERL-CH 802.3 200GBASE-CR2 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 200GBASE-CR2 standards draft.
- ERL-CH 802.3 400GBASE-CR4 ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 400GBASE-CR4 standards draft.
- ERL-SI 802.3 100GBASE-CR1 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 100GBASE-CR1 standards draft.
- ERL-SI 802.3 200GBASE-CR2 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 200GBASE-CR2 standards draft.
- ERL-SI 802.3 400GBASE-CR4 ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 400GBASE-CR4 standards draft.
- ERL-CH 802.3 100GAUI-1 C2C ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 100GAUI-1 C2C standards draft.
- ERL-CH 802.3 200GAUI-2 C2C ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 1200GAUI-2 C2C standards draft.
- ERL-CH 802.3 400GAUI-4 C2C ERL Compliance—Channel viewer performs channel return loss compliance checks per current trending IEEE 802.3 400GAUI-4 C2C standards draft.
- ERL-SI 802.3 100GAUI-1 C2C ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 100GAUI-1 C2C standards draft.
- ERL-SI 802.3 200GAUI-2 C2C ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 200GAUI-2 C2C standards draft.
- ERL-SI 802.3 400GAUI-4 C2C ERL Compliance—Channel viewer performs device return loss compliance checks per current trending IEEE 802.3 400GAUI-4 C2C standards draft.
- COM OIF-CEI-112G-LR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-112G-LR standards.
- COM OIF-CEI-112G-MR Channel Compliance—Channel viewer performs channel compliance checks per OIF-CEI-112G-MR standards.
- ERL-CH OIF-CEI-112G-LR ERL Compliance—Channel viewer performs channel return loss compliance checks per OIF-CEI-112G-LR standards.
- ERL-CH OIF-CEI-112G-MR ERL Compliance—Channel viewer performs channel compliance checks per OIF-CEI-112G-MR standards.
- ERL-SI OIF-CEI-112G-LR ERL Compliance—Channel viewer performs device return loss compliance checks per OIF-CEI-112G-LR standards.
- ERL-SI OIF-CEI-112G-MR ERL Compliance—Channel viewer performs device compliance checks per OIF-CEI-112G-MR standards.
- COM JESD204C.01 Class R Channel Compliance—Channel viewer performs channel compliance checks per JESD204C.1 Class R standards.
- COM JESD204C.01 Class M Channel Compliance—Channel viewer performs channel compliance checks per JESD204C.1 Class M standards.
- COM JESD204C.01 Class S Channel Compliance—Channel viewer performs channel compliance checks per JESD204C.1 Class S standards.


This panel allows you to select and configure the channel plotting. The Advanced Link Analyzer Channel Viewer can plot channel characteristics in either frequency domain or time domain. Typical frequency domain amplitude and group delay plots are shown in the following figure.

The Advanced Link Analyzer Channel Viewer plots the channels’ amplitude and group delay frequency responses in a linear or logarithmic frequency scale. It also allows you to limit the plot frequency range. When multiple transmission channels (such as loss or victim) are in the Channel List, you can plot the cascaded channel response by turning on the Plot Combined Channel Response option in the Systems Options panel. An example of a combined channel response is shown in the following figure, in which a lossy backplane channel is cascaded with a 5” microstrip PCB trace.

The Advanced Link Analyzer Channel Viewer can also plot channel responses in the time-domain. It can compute the impulse response (IR) and single-bit response (SBR) of a channel or a combined response of channels. When performing a time-domain plot, you must specify the maximum frequency and plot length of the time-domain response. The following figure shows examples of impulse response and single-bit response of a 5” microstrip PCB trace.

Combined time-domain channel responses can also be done in the Advanced Link Analyzer Channel Viewer. The following figure shows examples of combined time-domain channel response of a lossy backplane channel and a 5” microstrip PCB trace.

By turning on the Remove Propagation Delay option, the Advanced Link Analyzer Channel Viewer can mathematically remove the delay of channels so that more direct comparison among channels can be seen. The following figure shows an example of “Remove Propagation Delay” channel response of the same channels used in the previous figure.

Modulation Type – Select the modulation type that the channels operate and are checked against.
Channel Analysis
The following figure shows the Channel Analysis GUI.

In the Channel Analysis Configuration panel, the following parameters can be configured to your link configuration or preferences:
- Max. Freq.—Maximum frequency where channel analysis is performed
- 20%-80% Tr/Tf—20%-80% rise/fall time of the input signal to the victim or transmission channel(s)
-
Nom max IL at Nyquist—Nominal
maximum insertion loss at Nyquist frequency. This parameter specifies the maximum allowed
insertion loss at Nyquist frequency, which is defined as half of the maximum frequency
specified above. This frequency is used to safe guard the correctness of the fitted
insertion curves so that the results meet fundamental transmission line
characteristics.Note: Please enter the nominal maximal IL value which approximates to the selected channel at the Nyquist frequency. This value does not need to be precise as the fitting algorithm usually have enough tolerance margins in computing the fitted curves. If the channel's insertion loss at Nyquist frequency is less than 15dB, please enter 15 for best performance. If multiple channel are selected for the channel analysis, please enter the insertion loss value of the most lossy channel.
- NEXT Amplitude—Near-end crosstalk aggressor signal amplitude
- FEXT Amplitude—Far-end crosstalk aggressor signal amplitude
- NEXT Tr/Tf—Near-end crosstalk aggressor 20%-80% rise/fall time
- FEXT Tr/Tf—Far-end crosstalk aggressor 20%-80% rise/fall time
- Crosstalk dB Factor—This parameter, Y, defines how dB is calculated where dB = Y*log10(amplitude)
- Modulation Type—Select the modulation type that the channels operate and are checked against. The supported modulation types are NRZ (default) and PAM4.
-
Compliance Mask—Select the
channel compliance mask for channel analysis. The Compliance
Mask menu contains the following selections:
- 10GBASE-KR—Use the 10GBASE-KR channel compliance mask.
- OIF CEI-28G-SR 3.0—Use the OIF CEI-28G-SR channel compliance mask.
- OIF CEI-25G-LR 3.0—Use the OIF CEI-25G-LR channel compliance mask.
- Custom—Refer to Figure 130. Several text boxes for each channel compliance check item are shown. You can copy or manually input the mask definitions. The format for each mask definition data point is “Frequency (in Hz)", followed by "Amplitude (in dB)”. The number of data points is limited to the maximum text length allowed by the text box (the maximum size is 32767 bytes). The frequency grid of a mask must be monotonic increasing.
-
Load from file—Allows you
to load a predefined custom channel compliance. Each mask definition starts with a
keyword, followed by a pair of numbers that represent the data points for “Frequency
(Hz)" and "Amplitude (dB)”. Following is a sample of a custom channel compliance mask
file:
IL Mask Min 1 0 1e9 -1 10e9 -2.5 IL Mask Max 1 0 1e9 1 10e9 2.5 ILD Mask Min 1 0 1e9 -4 10e9 -4 ILD Mask Max 1 0 1e9 4 10e9 4 RL Mask 1 -10 1e9 -10 10e9 -4 ICR Mask 1e9 55 25e9 25 ICN Mask 1 10 5 10 25 0
When you click Plot, the Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list
- Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, crosstalk channels’ amplitude, and power sum of all crosstalk channels is shown. An example is illustrated in the above figure.
- Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation is shown, as in the following figure.

- Return Loss Plot—This plot is labeled CP: RL. In this plot, the return loss characteristics (both ends, i.e., Sdd11 and Sdd22) of channels are shown, as in the following figure.

- Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels is plotted. ICR is calculated as the distance between the insertion loss and combined crosstalk channels, as in the following figure. When the Crosstalk Limit plot is not enabled, the Channel Viewer also calculates and displays integrated crosstalk noise (ICN or XTLKrms) in mV-RMS units.

- Crosstalk Limit Plot—This plot is labeled CP: XTLK Limit. In this plot, a crosstalk noise figure, integrated crosstalk noise (ICN), or XTLKrms in mV-RMS units, is calculated based on your configurations, as in the following figure.

10GBASE-KR Channel Compliance
The following figure shows the 10GBASE-KR channel compliance check GUI.

All parameters are predefined as described in the IEEE 802.3ap/10GBASE-KR standards, so there is no user input. Click Plot to proceed. Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list.
- Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, maximum insertion loss limits, crosstalk channels’ amplitude, and power sum of all crosstalk channels is shown. An example is illustrated in the above figure.
- Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation and ILD masks are shown, as in the following figure.

- Return Loss Plot—This plot is labeled CP: RL. In this plot, return loss (RL) characteristics of channels and the RL mask are shown, as in the following figure.

- Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels and the ICR mask are plotted, as in the following figure.

OIF CEI-28G-SR 3.0 and OIF CEI-25G-LR Channel Compliances
The following figure shows the OIF CEI-28G-SR 3.0 channel compliance check GUI.

OIF CEI-25G-LR, OIF CEI-28G-MR, and OIF-CEI-28G-SR channel compliances are similar in configuration and usage. Both cases are covered in this section. All parameters are predefined as described in the OIF CEI-25G-LR, OIF CEI-28G-MR, and OIF-CEI-28G-SR standards, so there is no user input. Click Plot to proceed. Channel Viewer computes and generates a sequence of plots that show the performance of the channels in the channel list.
- Insertion Loss Plot—This plot is labeled CP: IL. In this plot, the insertion loss of channels, fitted curve of transmission channels’ insertion loss, insertion loss masks, crosstalk channels’ amplitude, and power sum of all crosstalk channels are shown. An example is illustrated in the above figure.
- Insertion Loss Deviation Plot—This plot is labeled CP: ILD. In this plot, the insertion loss deviation and ILD masks are shown, as in the following figure.

- Return Loss Plot—This plot is labeled CP: RL. In this plot, return loss (RL) characteristics of channels and RL mask are shown, as in the following figure.

- Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this plot, the Insertion Loss to Crosstalk Ratio (ICR) of channels and the ICR mask are plotted, as in the following figure.

- Crosstalk Limit Plot—This plot is labeled CP: XTLK Limit. In this plot, a crosstalk noise figure, XTLKrms in mV at Nyquist frequency, is calculated based on your configurations, as in the following figure

Channel Operating Margin (COM) Channel Compliance and Analysis
Advanced Link Analyzer Channel Viewer is equipped COM computation engine that can compute COM values for selected channels. Users can select and import channels, via Add Transmission/FEXT/NEXT pull down menu or click Channel Viewer button within Advanced Link Analyzer main GUI, select the intended standards or COM Analysis, and then followed by clicking the Plot button. Channel Viewer performs a sequence of computation and present the results.
- 100GBASE-CR4
- 100GBASE-KP4
- 100GBASE-KR4
- CAUI-4 C2C
- 200GAUI-4
- 400GAUI-8
- 200GAUI-4 C2M
- 400GAUI-8 C2M
- 200GBASE-CR4
- 100GBASE-CR2
- 50GBASE-CR
- 200GBASE-KR4
- 100GBASE-KR2
- 50GBASE-KR
- OIF-CEI-56G-LR
- OIF-CEI-56G-MR
- 100GBASE-KR1
- 200GBASE-KR2*
- 400GBASE-KR4*
- 100GBASE-CR1*
- 200GBASE-CR2**
- 400GBASE-CR4*
- 100GAUI-1 C2C*
- 200GAUI-2 C2C*
- 400GAUI-4 C2C*
- OIF-CEI-112G-LR*
- OIF-CEI-112G-MR*
- JESD204C.1 Class R
- JESD204C.1 Class M
- JESD204C.1 Class S








The COM result message box displays the COM analysis results and COM equalization settings. You can also copy the results to the clipboard by clicking Copy to clipboard or save the results to a text file by clicking Save to a file.
Effective Return Loss (ERL) Compliance and Analysis
Advanced Link Analyzer Channel Viewer is equipped with an ERL computation engine that can calculate ERL values for selected channel and device return loss data. You can select and import the channel's or device's return loss characteristics data file via the Add Transmission menu. To perform ERL analysis, use the Channel Analysis and Compliance Module menu, select the intended ERL analysis type, and then press Plot. The Channel Viewer performs a sequence of computations and presents the results.
- 50GBASE-KR: channel, transmitter, and receiver
- 100GBASE-KR2: channel, transmitter, and receiver
- 200GBASE-KR4: channel, transmitter, and receiver
- 50GBASE-CR: channel and receiver
- 100GBASE-CR2: channel and receiver
- 200GBASE-CR4: channel and receiver
- 100GBASE-KR1*: channel and device
- 200GBASE-KR2*: channel and device
- 400GBASE-KR4*: channel and device
- 100GBASE-CR1*: channel and device
- 200GBASE-CR2*: channel and device
- 400GBASE-CR4*: channel and device
- 100GAUI-1 C2C*: channel and device
- 200GAUI-2 C2C*: channel and device
- 400GAUI-4 C2C*: channel and device
- OIF-CEI-112G-LR*: channel and device
- OIF-CEI-112G-MR*: channel and device


ERL computation engine that can calculate ERL values for selected channel and device return loss data. You can select and import the channel's or device's return loss characteristics data file via the Add Transmission menu. To perform ERL analysis, use the Channel Analysis and Compliance Module menu, select the intended ERL analysis type, and then press Plot. The Channel Viewer performs a sequence of computations and presents the results.
COM Analysis
The COM Analysis module allows you to perform customizable COM and ERL analysis. In the COM Analysis mode, the COM or ERL parameters can be edited.
You can use the Template (Temp in the GUI) menu below the COM parameter table to select a COM or ERL standard and use it as a starting point for customizations. You can also save and load customized COM parameters from the Template menu.
The original COM calculations assume certain scaling among the data rate (fb) and parameters, such as receiver continuous time linear equalizer’s (CTLE) pole and zero locations. When you want to compute COM at non-standard data rates or variable data rates (for OIF CEI standards for example), various COM parameters may need to be manually calculated and input into the table. The Channel Viewer’s COM analysis engine implements automatic scaling feature, for example, for receiver CTLE, TX rise/fall time, and so on, which allows the automatic frequency scaling of, for example, four CTLE parameters when CTLE_Auto_Scale is set to 1 in the COM configuration table. The CTLE scaling usage in the COM analysis is as follows:
- CTLE_f_p1_div_factor: f_p1 is equal to fb/CTLE_f_p1_div_factor
- CTLE_f_p2_div_factor: f_p2 is equal to fb/CTLE_f_p2_div_factor
- CTLE_fz_div_factor: fz is equal to fb/CTLE_fz_div_factor
- CTLE_f_HP_PZ_div_factor: f_HP_PZ is equal to fb/CTLE_f_HP_PZ_div_factor
CTLE scaling also covers CTLE with listed pole/zero sets (as in JESD204C.1).
You can enable the transmitter rise or fall time (T_r) automatic scaling factor by setting T_r_Auto_Scale to 1 and then specifying the scaling factor T_r_fb_custom_factor. The T_r is equal to 1/fb*T_r_fb_custom_factor. Similarly, you can configure the rise or fall time of TDR stimulus by setting TR_TDR_Auto_Scale to 1 and TR_TDR_fb_custom_factor where TR_TDR is 1/fb*TR_TDR_fb_custom_factor.
COM Analysis Wizard can assist you setting up custom COM analysis configurations as illustrated in Figure 154.
In COM Analysis Wizard, you can specify custom link baud rate (fb), target BER rate (DER), CTLE scaling factors, and transmitter rise/fall time scaling factor. Channel Viewer then configures the COM (or ERL) parameters in the background before computing the COM or ERL.

ITOL Random Noise Calibration
Advanced Link Analyzer Channel Viewer is equipped with an ITOL (Interference Tolerance Test) Random Noise (RN) Calibration engine that computes the noise amplitude to stress the receiver-under-test (to COM threshold, commonly 3dB) per instructions/procedures from IEEE 802.3 standards. To use this feature, you start with selecting the COM RN Calibration entry under Channel Analysis and Compliance Module pull-down menu, and then select a COM compliance template (using Temp pull-down menu). The COM Random Noise Calibration Wizard shows how to guide the RN calibration configurations and analysis. Figure 155 shows the COM Random Noise Calibration Wizard GUI.
To perform RN calibration, two channel model files are required: Data Path S(tc), which represents the victim data path’s channel characteristics, and Noise Path S(nc), which represents the signal path connecting the noise source to the receiver-under-test, as illustrated in Figure 155. Inside the Channel Viewer, S(tc) is represented by the victim transmission path and S(nc) is represented by the first far-end crosstalk (FEXT) channel component, respectively. You can configure these two channels before initiating the COM RN Calibration Wizard or specify S(tc) and S(nc) within the Wizard.
There are five ITOL RN calibration parameters to be configured before conducting the calibration process. Note that specifying these parameters are optional which depends on your test bench, device, and/or instrument conditions. When custom parameters are not enabled or specified, the COM/ERL parameters from the COM table or template are used.
Apply Measured Jitter: when enabled (i.e. check the Apply Measured Jitter check box in the GUI), users can input PAM4 jitter values Jnu, where n is determined by the DER target for this RN calibration process, and Jrms in UI unit. Per IEEE 802.3 standards, the Jnu and Jrms are the measured TX jitter numbers. The wizard also shows the converted COM parameter A_DD and sigma_RJ for references.
Apply Measured SNDR: when enabled (i.e. check the Apply Measured TX SNDR check box), you can input the measured TX SNDR value per IEEE 802.3 specifications.
Apply Measured TX Rise/Fall Time (T_rm or T_r, only one can be applied): when enabled (i.e. either Apply Measured TX Rise/Fall Time (T_rm) or Apply Measured TX Rise/Fall Time (T_r) check box), you can input either T_rm or T_r in the associated text box with the unit of ps. While T_r is directly used in the COM process, T_rm is converted to T_r per IEEE 802.3 standards.
Exclude TX Package: when enabled (i.e. check the Exclude TX Package check box), TX package is excluded from the COM analysis. Per IEEE 802.3 specifications, TX package is excluded because RN calibration is usually performed using a signal or pattern generator.
Apply Custom RN Calibration Pass Threshold: when enabled (i.e. check the Apply Custom RN Calibration Pass Threshold check box), the RN calibration process uses the input value (in dB unit) as the stoppage criteria to terminate the RN calibration process. That is, if the threshold is 0.1dB, the RN calibration process stops when the resultant COM value is within the range between 2.9dB and 3.1dB assuming that the COM threshold is 3dB.

After configuring the RN calibration, you have three options:
Proceed to RN Calibration: start the RN calibration process. Upon completion of the calibration, a message box displays and reports the found RN value, i.e. sigma_bn in COM, and various COM results. Figure 156 illustrates an example of RN calibration output.

Apply Changes and Exit Wizard: clicking this button allows Channel Viewer to save your input to the COM/ERL table/template but without performing the RN calibration process.
Cancel and Discard Change: click this button to exit the wizard and all inputs are discarded.
2.3.3.3. Options
In this panel, you can manage the Channel Viewer’s projects and settings.
- Load: Loads previously saved Channel Viewer settings (including the channel list).
- Save and Save as: Saves the current Channel Viewer configurations and channel list.
- Save plot as image: Saves the current plot as an image file.
- Options: Opens the Channel Viewer’s Options window. The Options window is described below.

Use this panel to select the following plot options:
- Enable Instant Plot—Enable and disable instant channel plotting when a new channel is added to the channel list. When you disable this option, you must click Plot to plot the channel response.
- Plot Combined Channel Response—When you enable this option, the Channel Observer cascades the channels with Loss type and plots it along with other channel characteristics. The crosstalk channels (NEXT and FEXT) are not cascaded.
- Auto. S-parameter Configuration Checker (ASCC)—Enable and disable the ASCC function. The Channel Viewer uses the ASCC function to determine the port configuration of S-parameters. When you disable ASCC, you must manually select the port configuration of each S-parameter channel model.
- Enable Channel Wizard—If checked, when you select a channel file, Channel Wizard helps configure the channel configuration. If unchecked, you must manually configure the channel configuration.
- S-parameter Integrity Check—If enabled, Channel Wizard checks the channel integrity (the passivity and causality). If Advanced Link Analyzer has problems with opening or accessing an S-parameter, you can disable the S-parameter Integrity Check.
- Touchstone 2.0 Support—Enable or disable Touchstone 2.0 S-parameter file support.
- Plot Axis Precision—You can set the number of decimal points in the x- and y-axis of all plots.
- Time Domain Plot—Channel Views can automatically choose the common channel characteristics for time-domain analysis. For example, when Auto is selected, Channel Viewer chooses Sdd21 for impulse response, single bit response, and step response plots, and chooses Sdd11 for the TDR plot. If Auto Skip is selected, Channel Viewer chooses the likely matched channel types (if you selected any) for time domain analysis. For example, if you choose Sdd11, Sdd12, Sdd21, and Sdd22 and want to plot single bit responses, Sdd12 and Sdd21 are used for the plots, and Sdd11 and Sdd22 are skipped. When "Plot as is" is selected, Channel Viewer plots all time domain results for all selected S-parameter items.
- Impulse Response / Single Bit Response Options—You can specify stimulus amplitude for impulse response and single-bit response calculations. The default value is 0.5 V (single-ended).


Use this panel to select the following configuration options:
-
S-parameter Options
-
Extrap Method
- Default—Linear extrapolation.
- IL Fitting Extrapolation—Extrapolation is done by the insertion loss fitting method.
-
Extrap Usage—This
menu selects the method used in the extrapolation S-parameter channel
model.
- Default—The S-parameter is extrapolated but is capped at the final amplitude value.
- Always Apply—The S-parameter is extrapolated without restriction.
-
Extrap Method
-
Causality Check
Options
-
SP Extrap
Method—This menu selects the S-parameter extrapolation
method.
- Default—Insertion loss fitting extrapolation method.
- Last Amplitude Value—Linear extrapolation capped by the last amplitude value.
- Extrap Usage—This menu selects the method used in the extrapolation S-parameter channel model. This entry only applies during S-parameter causality checking.
-
SP Extrap
Method—This menu selects the S-parameter extrapolation
method.
2.4. Advanced Link Analyzer Batch Simulation Controller
The Advanced Link Analyzer Batch Simulation Controller allows you to run multiple simulations by not invoking the Advanced Link Analyzer Control Module. This capability allows you to run multiple link simulations and then review the results offline.

The Advanced Link Analyzer Batch Simulation Controller accepts Advanced Link Analyzer simulation configuration (.jne) files. You can set up and save their link simulation configurations using the Advanced Link Analyzer Control Module. You can then add each individual Advanced Link Analyzer job to the batch job list and execute all the jobs.
The Advanced Link Analyzer Batch Simulation Controller has a built-in timer and house-keeping routine that constantly monitors the status of simulating tasks. It can also launch more than one simulation job at a time to better utilize the multi-core/multi-processor computing environment. Check whether your Advanced Link Analyzer license or license server supports multiple simulations at the same time.
After adding jobs, some key job information is shown in the job list, including simulation data rate, test pattern, simulation length, and initial job status of “Not Run”. After simulation, key simulation results, such as the final eye diagram height and weight, are displayed in the job list along with the simulation time.
The following options are available in the Advanced Link Analyzer Batch Simulation Controller user interface:
- Add—Add a Advanced Link Analyzer simulation job to the job list. Use the file browser to locate .jne configuration files.
- Delete—Delete the highlighted job in the job list.
- Enable/Disable—Enable or disable the highlighted job in the job list.
- Reset Select Jobs—Reset the status of highlighted jobs to “Not Run”
- Reset All Jobs—Reset all jobs in the job list to “Not Run”
- Clear All Jobs—Clear and delete all jobs in the job list
- View Job Configuration—Open and load Advanced Link Analyzer Control Module with the highlighted job
- Run Selected Job—Execute the highlighted job
- View Select Sim Result—Open and load simulation result (if available) of the selected job
- Move Up (/\)—Move the highlighted job forward in the job list
- Move Down (\/)—Move the highlighted job toward to back of the job list
- Load— Load Advanced Link Analyzer Batch Simulation Controller configuration file
- Save/Save as—Save or save new Advanced Link Analyzer Batch Simulation Controller configuration file
- Exit—Exit the Advanced Link Analyzer Batch Simulation Controller
- Stop—Stop batch simulation of jobs
- Start Batch Simulation—Start batch simulation of all not-executed jobs in the job list
- Maximum Concurrent Simulation Session—Set the number of concurrent simulations. Advanced Link Analyzer Batch Simulation Controller monitors the number of executing jobs. It starts a new simulation job when the computing resource is available.
-
Simulation Result Display Option—This menu controls the
simulation result display option. There are three options:
- Display Result—When each simulation is completed, a new Data Viewer window shows the result.
- Ask to Display Result—When each simulation is completed, a message box asks if you want to see the simulation results.
- Manually Select Job & Display Result—This is the default option. When a job is finished, no result is shown. You must manually select the job and click View Selected Sim Result to see the simulation results.
- Simulation Window Close Time—When a simulation is completed, the Advanced Link Analyzer Simulation Engine window remains open for the specified time before closing.
- Output Directory—Specify the output directory in which to save all batch simulation results. This output location overrides the output directory option specified in each individual simulation job.
- The Advanced Link Analyzer Batch Simulation Controller launches each job in an individual process. Make sure there are no file read/write access conflicts. The most common issue is that several jobs might want to open or modify the same file (for example, log file from IBIS-AMI models). This causes the job process to fail.
- When a job fails to complete, it may occupy one simulation resource, such as the CPU, indefinitely. If this occurs, manually close the failing simulation engine to free the computing resource.
- Check your Advanced Link Analyzer license type or license server configuration to see if simultaneous multiple simulations are supported. Some license servers do not allow you to check out multiple license at the same time.
- Intel recommends you run batch simulation with two or more concurrent sessions, if supported by the computation environment. This avoids blocking the batch simulation queue.
- Intel recommends you run batch simulations with the Manual Select Job & Display Result option because viewing all simulation results may take a large amount of computing resources.
2.5. Advanced Link Analyzer Channel Designer
The Advanced Link Analyzer Channel Designer contains the following channel components:
- Stripline
- Coupled stripline
- Microstrip
- Coupled microstrip
- Coax
- RLGC transmission line
- Ideal transmission line
- Via model based on composite transmission line blocks
- Shunt and series capacitance
- Series inductance
- S-parameter model
- Near-end crosstalk extractions from a multiple-lane S-parameter
- Far-end crosstalk extractions from a multiple-lane S-parameter
- PCB stackup
A channel design can include one or multiple channel components. Advanced Link Analyzer Channel Designer can combine and generate Touchstone S-parameter models that can be used in link simulations. Advanced Link Analyzer Channel Designer provides user-friendly and integrated interfaces. The channel components and resulting channel models can be observed and analyzed using embedded plot functions or the Advanced Link Analyzer Channel Viewer.
In Advanced Link Analyzer, a 2-port single-ended channel model is generated internally for the following components:
- Stripline
- Microstrip
- Coax
- RLGC transmission line
- Ideal transmission line
- Via model based on composite transmission line blocks
- Shunt and series capacitance
- Series inductance
After the single-ended model is generated, Advanced Link Analyzer Channel Designer converts it into a 4-port differential-pair format by assuming that these two single-ended channels are uncoupled.
A full 4-port single-ended channel model is generated for the following components:
- Coupled stripline
- Coupled microstrip
- S-parameter model
Advanced Link Analyzer supports PCB stackup dataset entries in the design space. You can specify multiple PCB stackup datasets within a channel designer project. Stripline, microstrip, coupled stripline, and coupled microstrip models can be generated from substrate parameters within each individual channel designer or using one of the PCB stack datasets in the design space.
- n-port Single-ended S-parameter (Touchstone 1 and 2)
- n-port Mixed-mode S-parameter (Touchstone 2 only)
Channel cascading of all channel components, which include coupled stripline, coupled microstrip, and S-parameter channel components, are done in the 4-port level.
Starting the Advanced Link Analyzer Channel Designer
You can start Advanced Link Analyzer Channel Designer in two ways:
- Double-click adv_link_analyzer_channel_designer.exe
- Click Channel Designer in the Advanced Link Analyzer Control Module
The Advanced Link Analyzer Channel Designer’s graphical user interface is shown in the following figure.

- Connect—Use the straight line or right-angled line to connect channel components
- Edit—Delete, copy, or paste channel components
- Component—Individual channel components to be added to the channel. See sessions below for details
- Design Space
-
Parameters—Set up
system level parameters
- S-parameter Max Frequency—Set the maximum frequency of the resulting channel model
- S-parameter Frequency Step—Set the frequency step of the resulting channel model
- Reference Impedance—Set the reference impedance of the resulting channel model
-
System
Options
- S-parameter Integrity Check—Select if checking channel integrity, such as passivity and causality, on the input S-parameter model. If Advanced Link Analyzer Channel Designer has issues opening or accessing certain S-parameter files, disable the channel integrity check to see if the issue is resolved.
- Channel Caching—Advanced Link Analyzer stores the recent read S-parameter model in memory for quicker accesses. Select Enable to enable the caching capability. Select Disable to disable the caching capability. Channel caching is enabled by default.
- Touchstone 2.0 Support—Use this menu to enable or disable Touchstone 2.0 S-parameter support.
-
Causality Check
Options
- SP Extrap Method—Use this menu to select S-parameter extrapolation method during causality checking. The default method is insertion loss fitting extrapolation method. The Last Amplitude Value option uses linear extrapolation and caps the amplitude at the last amplitude value from the S-parameter file.
- Extrap Usage—The default is to cap the amplitude of the extrapolation at the last amplitude value in the S-parameter file. The Always Apply option uses the values from the extrapolation without any restrictions.
-
Project management and
Commands
- Load—Load previously saved Channel Designer project
- Save/Save as—Save current project
- Reset—Clear all channel components
- Plot All Components—Plot all individual channel components in the Design Space using Advanced Link Analyzer Channel Viewer
- Plot Result Channel—Generate the result channel and plot its characteristics using Advanced Link Analyzer Channel Viewer
- Generate s4p File—Generate the result channel and save it in a 4-port Touchstone S-parameter file
- Quit—Exit Advanced Link Analyzer Channel Designer
Constructing a Channel in Channel Designer
Similar to the Link Designer operations in Advanced Link Analyzer’s Control Module, a channel consists of one or more channel components between the input port (Port 1) and the output port (Port 2). After the channel components are placed into the workspace, click Connect to connect the components. In Connect mode, one or two connectors are shown on each component. Connect the channel components by dragging the line from one connector to another. Two types of connections are provided in Channel Designer: Right Angled Line and Straight Line.
The following rules of channel construction apply to the Channel Designer:
- The Input port (Port 1) has one output port or connector
- The Output port (Port 2) has one input port or connector
- A channel component has one input and one output port
- A connection between two components can be established from an output port to an input port
- An Input port cannot be connected directly to an Output port
A channel establishment checking algorithm runs constantly in the background, checking whether a channel is established for channel generation. When a channel is established between an input port and an output port, the link lines become bold. The User Interface figure above shows an established channel link.
Channel Components
The Channel Designer contains the following components:
- Port 1—Port 1 is the input port of the channel under construction.
- Port 2—Port 2 is the output port of the channel under construction.
- S-parameter channel component—Use an S-parameter channel model file as part of the channel under construction. When you click the S-parameter icon, the Channel Wizard appears to help you configure the S-parameter file. Refer to the Advanced Link Analyzer Control Module’s Channel Wizard section for detailed usage. The following figure shows an example of the Channel Wizard.

Capacitance and Inductance Model Components
You can insert the following capacitance and inductance components as part of the channel:
- Shunt capacitance
- Series capacitance—Listed in the Channel Wizard under the AC Coupling Capacitor
- Series Inductance
Advanced Link Analyzer Channel Designer uses the Channel Wizard to configure these capacitance and inductance components so you can input the capacitance and inductance values there. The following figure shows an example.

Stripline Component
A stripline uses a flat strip of metal that is sandwiched between two parallel ground planes. The insulating material of the substrate forms a dielectric. The width of the strip, the thickness of the substrate, and the relative permittivity of the substrate determine the characteristic impedance of the strip which is a transmission line. A typical stripline structure is shown in the following figure with these parameters:
- Input parameters
- W—Signal trace width (in various units)
- L—Signal trace length (in various units)
- Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The stripline cannot be placed on the top and bottom layers.
- T—Signal trace thickness (in various units)
- H—Separation between ground planes (in various units)
- Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
- TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
- Cond—Conductor conductivity (S/m)
- Rough—Surface roughness (in various units)
- Mur—Relative permeability (no unit)
- Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
- Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
- View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
- Output parameters
- Z0—Impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
Microstrip Component
Microstrip is a type of electrical transmission line. It consists of a conducting strip separated from a ground plane by a dielectric layer known as the substrate. A typical microstrip structure is shown in the following figure with these parameters:
- Input parameters
- W—Signal trace width (in various units)
- L—Signal trace length (in various units)
- Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The microstrip can only be placed on the top and bottom layers.
- T—Signal trace thickness (in various units)
- H—Separation between ground planes (in various units)
- Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
- TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
- Cond—Conductor conductivity (S/m)
- Rough—Surface roughness (in various units)
- Mur—Relative permeability (no unit)
- Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
- Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
- View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
- Output parameters
- Z0—Impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
Coax Component
A coax transmission line consists of two round conductors in which one completely surrounds the other. The two conductors are separated by a continuous solid dielectric. A typical coax structure is shown in the following figure with these parameters:
- Input parameters
- a—Diameter of inner conductor (in various units)
- b—Diameter of outer conductor (in various units)
- t—Thickness of outer conductor (in various units)
- Length—Length of the coax (in various units)
- Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
- TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
- Cond (a)—Conductor conductivity of inner conductor (S/m)
- Cond (b)—Conductor conductivity of outer conductor (S/m)
- Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
- Output parameters
- Z0—Impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
RLGC Transmission Line Component
The channel is constructed with unit length RLGC models. A typical RLGC transmission line structure is shown in the following figure with these parameters:
- Input parameters
- L—Unit Length inductance (in various units)
- Rdc—Unit length DC resistance (in various units)
- Rac—Unit length skin-effect resistance (in various units)
- C—Unit length capacitance (in various units)
- Gdc—Unit length DC conductance (in various units)
- Gac—Unit length AC conductance (in various units)
- Length—Length of the coax (in various units)
- Freq—Frequency where the Z0 (Impedance) and E-Eff (electrical length) are reported (in various units)
- Output parameters
- Z0—Impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
Ideal Transmission Line Component
- Input parameters
- Z0—Target impedance (Ohm)
- Electrical length (in various units)

The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
Via Component
In printed circuit board design, a via consists of two pads in corresponding positions on different layers of the board. The pads are electrically connected by a hole through the board. In Advanced Link Analyzer Channel Designer, an analytical PCB Via model is constructed. A typical PCB via structure is shown in the following figure and the analytical via model structure is shown in the figure after that. The via is configured with the following parameters:
- Input parameters
-
Via
- Impedance (Z3) (Ohm)
- Electrical Length (td3) (in various units)
-
Pad 1
- Capacitance (C1) (in various units)
-
Pad 2
- Capacitance (C2) (in various units)
-
Via Stub 1
- Impedance (Z1) (Ohm)
- Electrical Length (td1) (in various units)
- Termination (R1) (in various units)
-
Via Stub 2
- Impedance (Z2) (Ohm)
- Electrical Length (td2) (in various units)
- Termination (R2) (in various units)
-
Via


The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
CHDE Component
Advanced Link Analyzer Channel Design can use an existing Advanced Link Analyzer Channel Designer project as a channel component. When you click the CHDE icon, a file browser opens and lets you select an existing Channel Designer configuration file.
Coupled Stripline Component
A coupled stripline uses a pair of flat strip of metal that is sandwiched between two parallel ground planes. The insulating material of the substrate forms a dielectric. The width of the strip, the separation/space between the strips, the thickness of the substrate, and the relative permittivity of the substrate determine the characteristic impedance of the strip which is a transmission line. A typical coupled stripline structure is shown in the following figure with these parameters:
Input parameters:
- W—Signal trace width (in various units)
- L—Signal trace length (in various units)
- Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The coupled stripline cannot be placed on the top and bottom layers.
- S—Signal trace separation distance (in various units)
- T—Signal trace thickness (in various units)
- H—Separation between ground planes (in various units)
- Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
- TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
- Cond—Conductor conductivity (S/m)
- Rough—Surface roughness (in various units)
- Mur—Relative permeability (no unit)
- Freq— Frequency where the Z0 (Impedance), K (coupling coefficient), Z0even (even mode impedance), Z0odd (odd mode impedance), and E-Eff (electrical length) are reported (in various units)
- Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
- View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
Output parameters:
- Z0—Impedance at specified frequency Freq (Ohm)
- K— Coupling coefficient
- Z0even— Even mode impedance at specified frequency Freq (Ohm)
- Z0odd— Odd mode impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)
The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

Coupled Microstrip Component
Coupled Microstrip is a type of electrical transmission line. It consists of a pair of conducting strips separated from a ground plane by a dielectric layer known as the substrate. A typical coupled microstrip structure is shown in the following figure with these parameters.
Input parameters:
- W—Signal trace width (in various units)
- L—Signal trace length (in various units)
- Layer—PCB layer number where the signal trace is placed. This is only valid when PCB stackup dataset is used. The coupled microstrip can only be placed on the top and bottom layers.
- S—Signal trace separation distance (in various units)
- T—Signal trace thickness (in various units)
- H—Separation between ground planes (in various units)
- Er (Dk)—Relative dielectric constant. Advanced Link Analyzer Channel Designer supports frequency dependent dielectric constant mapping.
- TanD (Df)—Dielectric loss tangent. Advanced Link Analyzer Channel Designer supports frequency dependent dissipation factor mapping.
- Cond—Conductor conductivity (S/m)
- Rough—Surface roughness (in various units)
- Mur—Relative permeability (no unit)
- Freq— Frequency where the Z0 (Impedance), K (coupling coefficient), Z0even (even mode impedance), Z0odd (odd mode impedance), and E-Eff (electrical length) are reported (in various units)
- Type—Substrate type. If "Current" is selected, the substrate characteristics are as specified in the GUI. If "SubstrateN" is selected, where N is associated with one of the PCB stackup datasets in the design space, the channel model is generated using the selected PCB stackup data.
- View PCB Stackup Table—Click this button to view the selected PCB stackup dataset. The PCB stackup is read-only.
Output parameters:
- Z0—Impedance at specified frequency Freq (Ohm)
- K— Coupling coefficient
- Z0even— Even mode impedance at specified frequency Freq (Ohm)
- Z0odd— Odd mode impedance at specified frequency Freq (Ohm)
- E-Eff—Electrical length (in various units)
The channel component designer GUI can perform parameter unit conversion interactively. For example, you can change the length unit from mil to mm, and the GUI automatically computes the length value with the new unit.
After entering the model parameters, click Analyze, and Channel Designer computes the frequency response of the current design. The integrated plotting engine can display the insertion loss or return loss characteristics. When you alter the model parameters, the GUI displays a message that indicates the channel characteristics may have changed. Click Analyze to redraw the channel characteristics. You can also load or save the component design for reuse in the future.
If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.

PCB Stackup Component
A printed circuit board (PCB) stackup describes the basic construction of a PCB. Specifically, the stackup defines the total number of PCB layers and the type and characteristics of each of these layers.
The PCB stackup structure is shown in the following figure.

Input parameters:
- Number of Layers—Specify the number of PCB layers.
-
Material Type—Select the
type of PCB material. This sets the default relative dielectric constant (Er or
Dk) and dielectric loss tangent (TanD or Df) associated with the selected PCB
material. Each layer can have its own Er and TanD values. You can manually
update the Er and TanD of each layer. The supported material types are:
- FR4—Default: Dk/Er = 3.8 and TanD/Df = 0.011
- Rogers—Default: Dk/Er = 3.4 and TanD/Df = 0.0027
- Nelco—Default: Dk/Er = 3.7 and TanD/Df = 0.009
- Megtron4—Default: Dk/Er = 3.8 and TanD/Df = 0.005
- Megtron6—Default: Dk/Er = 3.63 and TanD/Df = 0.004
- Material Option 1—When selected, the Dk/Er and TanD/Df values are specified in the Material Option 1 tab page. This material option supports frequency-dependent Er/Dk and TanD/Df. See Figure 174 for an example.
- Material Option 2—When selected, the Dk/Er and TanD/Df values are specified in the Material Option 2 tab page. With this option, you can specify the Dk/Er and TanD/Df values for top/bottom and middle layers separately. This material option also supports frequency-dependent Er/Dk and TanD/Df. See Figure 175 for an example.
- Top/Bottom Substrate Height—This is the default substrate layer height value for the top and bottom layers when the PCB stackup table is initiated. You can select the appropriate length unit that suits their use.
- Middle Substrate Height—This is the default substrate layer height value for the middle PCB layers when the PCB stackup table is initiated. You can select the appropriate length unit that suits their use.
- Top/Bottom Metal Thickness—This is the default metal layer thickness for the top and bottom PCB layers. You can select the appropriate length unit that suits their use.
- Middle Metal Thickness—This is the default metal layer thickness for the middle PCB layers. You can select the appropriate length unit that suits their use.
- Conductivity—The default conductor conductivity (S/m) when the PCB stackup is initiated.
- Surface Roughness—The default surface roughness (in various units) when the PCB stackup is initiated.
- Copper mils/oz—The conversion factor when the metal thickness is specified in copper weight (oz)
- Enforce Symmetry—Choose to enforce the symmetry of the to-be-generated PCB stackup. If enabled, only the top half of the PCB stackup can be edited or modified; the lower-half PCB layers are automatically matched to the top layers. The default setting is Enable.
- Generate—Click Generate to generate the PCB stackup using the default values mentioned above.


If you are satisfied with your design, click OK to save and close the component design GUI. If you click Exit or the window X button, you discard the design.
Crosstalk Extraction Components
With multiple-lane S-parameters, in which the port number is greater than four, crosstalk characteristics can be embedded in the S-parameter data. While Advanced Link Analyzer can fully support and utilize the crosstalk data (both near-end and far-end crosstalk types), occasionally there is a need to extract the individual crosstalk characteristics for analysis or for other platforms' usage.
Advanced Link Analyzer Channel Designer uses the Channel Wizard GUI to guide the crosstalk data extraction with the following steps:
- Click NEXT for near-end crosstalk, or FEXT for far-end crosstalk.
- A file browser opens. Browse and open a multiple-lane S-parameter file.
- Advanced Link Analyzer Channel Wizard opens. Select crosstalk configurations such as port configuration, aggressor location, and victim lane.
- Click OK to place the crosstalk component into Channel Designer's design area.
The Channel Designer allows you to design your own crosstalk channel components by cascading the crosstalk component with other channel components. This feature can be useful in early design stages where the full link system is not fully developed for crosstalk extractions.

3. Tutorial: PCI Express 8GT
This tutorial uses Advanced Link Analyzer to run a link simulation. This example and its associated channel models are provided with the Advanced Link Analyzer distribution. The configuration file Demo.jne (included in the software distribution) contains the same link topology and a majority of the link settings discussed in this tutorial.
In this tutorial, a link that approximates a typical PCI Express* 8GT system with an Intel Stratix® V GX transmitter and a generic PCI Express* 8GT receiver is built and simulated in Advanced Link Analyzer. The following figure shows the link topology.

3.1. Methodology
This simulation emulates an Intel Stratix® V GX transmitter (with embedded package model), a PCI Express* 8GT receiver (with embedded package model), and a ~18-inch backplane channel. Per PCI Express* 8GT specifications, the link operates at 8 Gbps with a bit error rate (BER) < 10–12. The transmitter must have a minimum differential output voltage of 800 mV and a rise/fall time of ~35 ps (at 0.8 V VOD). In this simulation, the Stratix® V GX transmitter is set to 800 mV VOD (VOD level = 40). Additionally, the Stratix® V GX transmitter has a 4-tap FIR to compensate for channel effects. The PCI Express* 8G receiver has CTLE and a 1-Tap DFE per PCI-SIG definition.
To accomplish these goals, set up a transmitter model, a receiver model, and a link with the following parameters:
- Data rate: 8 Gbps
- Test pattern: PRBS-23
- BER target: BER < 10–12
-
Stratix® V GX
transmitter
- VOD: 800 mV (VOD Level = 40)
- Edge rate: Per Stratix® V GX characteristics
- 4-Tap TX FIR (1 pre-tap and 2 post-taps)
- Stratix® V GX package model (embedded)
- PLL: ATX (LC) set to low bandwidth
- Output Jitter: Retrieved from the
Intel Characterization
Database (embedded in Advanced Link Analyzer; contact My Intel support to enable this function)
- DCD = ~0.012 UI
- BUJ = ~0.032 UI
- RJ = ~1.00 psRMS (8 Gbps, BER < 10–12)
- Receiver
- CTLE:
- Programmable with 6 dB~12 dB boost at 4 GHz
- Per PCI-SIG specifications
- 1-tap DFE
- PCI-SIG receiver package model (12-port S-parameter model from PCI-SIG)
- CDR: Generic binary CDR with high loop bandwidth ~26 MHz
- Receiver Jitter:
- DJ = ~7 ps
- RJ = ~1.55 psRMS (at BER < 10–12)
- CTLE:
The ~18-inch backplane channel is described by a 12-port S-parameter model. The S-parameter is measured (or generated) with port configuration type 2, as shown in the following figure:


The Advanced Link Analyzer Channel Viewer shows that the backplane channel has approximately 17.15 dB loss at 4 GHz. The PCI-SIG RX package has 3.5 dB insertion loss at 4 GHz. The overall link has about 21 dB of loss (as shown in the Combined Channel black curve, not including Stratix® V GX transmitter package) at 4 GHz, which requires heavy TX and RX equalizations to achieve the required BER target.
For comparative purposes, the following table and figure show a typical external 100 MHz transmitter reference clock with measured phase noise characteristics and spurs at three different frequencies.
Phase Noise |
Spurs |
||
---|---|---|---|
Frequency |
Phase Noise (dBc) |
Frequency |
Amplitude (dBc) |
10 Hz |
–68 |
100 kHz |
–80 |
100 Hz |
–82 |
1 MHz |
–90 |
1 kHz |
–84 |
10 MHz |
–96 |
1 MHz and above |
–140 |

The PLL in the Stratix® V GX transmitter is enabled using ATX (LC) with low bandwidth configuration. The PLL effectively reduces the noise effects from the external reference clock.
Use the Advanced Link Analyzer’s link optimization algorithm to find the optimal equalization settings for both the transmitter and receiver. In this demonstration, you use the CTLE=>FIR+DFE link optimization method.
3.2. Setup and Initialization
First, start Advanced Link Analyzer. Input the following settings in the control module.
3.2.1. Setting Up the Control Module
Link and Simulation Setting Tab

Set the following parameters in the Link and Simulation Setting tab:
- Data Rate: 8 (Gbps)
- Simulation Length: 65536 (Bits)
- Target BER: 10^ -12
- Test Pattern: PRBS-23
- Reference Clock: 100 (MHz)
- Link Optimization Method: CTLE=>FIR+DFE
- FOM of Link Optimization: Area
- Compliance Mask: PCI Express* 8GT
- FEC: Off. This disables forward error correction (FEC) modeling since the transmitter and receiver do not support FEC.
- Project Name: Demo
- Simulation Mode: Hybrid
- Output Options: Data Viewer with Image Output. This option tells Advanced Link Analyzer to generate image files (.png) for all output plots.
- Jitter Analysis Options: Disable. This selection disables the jitter analysis function during the link simulation.
Click Reference Clock Option.

- Turn off the Ideal Reference Clock option
- Click the Option 2: Phase Noise tab
- Turn on the Select TX Reference Clock Option 2 option
- Type or copy the phase noise and spur data in the text boxes as shown in the above figure. The reference clock phase noise data can be found in the example configuration file Demo.jne.
Transmitter Tab

Set the following parameters in the Transmitter tab:
- Transmitter: Stratix® V GX
- Package: Stratix® V GX
- VOD Selection: 40 (~800 mV)
- Pre-emphasis: Auto
- PLL Type: ATX (LC)
- PLL Bandwidth: Low
- Jitter/Noise Component:
- If the Intel Device Characterization Data Access function is enabled, click Characterization Data Access. (A message box appears. Read and close the message box.) Transmitter jitter figures are populated automatically and the jitter/noise modeling mode is selected.
- If Intel Device Characterization Data Access is not available, manually type in the jitter numbers shown in the above figure. Note that the simulation results might differ slightly if the jitter data is from manual input.
Receiver Tab

Set the following parameters in the Receiver tab:
- Receiver: PCI Express* 8GT
- Package: PCI Express* 8GT
- CTLE Setting: Auto
- DFE Mode: Auto
- CDR Type: Bang-Bang
- CDR Bandwidth: Medium
- PVT Process: Typical
- PVT Voltage: Typical
- PVT Temperature: 25 deg C
- DJ: 0.056 (UI, 7 ps)
- RJ: 1.55 ps (RMS) (key-in and then use pull-down menu to set RJ unit)
Click Receiver Options. In the Receiver Configuration window, click the Equalization tab. Set DFE Tap Length to 1 and Step Size to 0.0078125.

3.2.2. Constructing the Channel
Next, construct the channel between the transmitter and receiver. In Advanced Link Analyzer, the package models for the Stratix® V GX transmitter and PCI Express* 8GT receiver are embedded. The transmitter and receiver packages are automatically included in the simulation.
Advanced Link Analyzer supports crosstalk modeling capabilities. The channel engine and simulation engine can extract and interpret crosstalk characteristics from a single or a multi-lane S-parameter file and compute the crosstalk effects. In the channel list, crosstalk channels are assumed to run in parallel with the victim channel and the crosstalk noises are superimposed. This section describes how to set up crosstalk simulation in Advanced Link Analyzer.
The backplane model is provided as a 12-port S-parameter. It consists of both insertion loss and crosstalk characteristics. However, Advanced Link Analyzer requires you to add them one at a time (even if the loss and crosstalk characteristics are from the same multiple-lane S-parameter file). Therefore, you are going to insert three channel components during channel setup: one backplane victim channel and two backplane aggressor channels.
Perform the following steps to add a victim channel:
- Click Channel in the Link Designer and select Transmission.
- Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as victim.
- The Advanced Link Analyzer Channel Wizard displays the Sdd21 characteristics of the middle lane (lane 2) in the 12-port S-parameter.
- Click OK to close the Channel Wizard.
- Place the channel icon in the Link Designer.

Perform the following steps to add the first crosstalk channel:
- Click Channel in the Link Designer panel and select Far-end Crosstalk (FEXT).
- Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as FEXT.
- The Advanced Link Analyzer Channel Wizard displays the FEXT #1 characteristic. Note that the Crosstalk Aggressor Location 1 is selected in for this channel.
- Click OK to close the Channel Wizard.
- Place the channel icon in the Link Designer.

Perform the following steps to add the second crosstalk channel:
- Click Channel in the Link Designer panel and select Far-end Crosstalk (FEXT).
- Use the file browser to locate the channel model file Demo.s12p and add it to the channel list as second FEXT.
- The Advanced Link Analyzer Channel Wizard displays the first FEXT channel characteristic by default.
- Change the Crosstalk Aggressor Location to 2. This tells Advanced Link Analyzer to select the second FEXT in the12-port S-parameter.
- Set the aggressor frequency offset to 300 ppm to emulate the phase shifting effect for this crosstalk noise source. This setting indicates the 2nd crosstalk is not frequency synchronous to the victim channel.
- Click OK to close the Channel Wizard.
- Place the channel icon in the Link Designer.

3.2.3. Completing the System
All the link components are now chosen and placed in the Link Designer. Click Connect in the Link Designer to begin connecting the components. Refer to the Link and Simulation Setting section for link construction in the Link Designer. The following figure shows the completed link system.

The link configuration is complete. Use the Save/Save as buttons to save the configuration for later use.
3.3. Analysis
Use the Channel Viewer to observe and analyze the channel characteristics. The Channel Viewer button is located on the right side of the Channel tab. This example shows the Sdd21 of the three channels you selected as well as the channel responses at test points and the overall channel. You can leave the Channel Viewer module open or close it by clicking OK or Exit.

Start the channel simulation by clicking Simulate in the lower right corner of the Advanced Link Analyzer Control Module. The Advanced Link Analyzer Simulation Engine simulates all the models and generates eye diagrams at test points and inside the receiver (after CTLE and DFE).
A goal of this tutorial was for Advanced Link Analyzer to automatically find the optimal link setting for both transmitter and receiver. In the simulation time, the progress bar flashes, indicating the Advanced Link Analyzer Simulation Engine is exploring the solution space. The link performance and result of the final setting is shown in a Advanced Link Analyzer Data View.
At TX output, which is located after the Intel Stratix® V GX transmitter output pin (after the TX package model), the results are shown in the following figure. Advanced Link Analyzer found the optimal TX-FIR setting: Pre-tap 1 = –4, Post-tap 1 = 2, and Post-tap 2 = 0. The configured transmitter generates ~0.83 UI of jitter at BER = 10-12. This set of TX outputs is measured with an ideal clock. In addition to the transmitter’s intrinsic jitter, the reference clock’s jitter and noise (recall that external reference clock phase noise and spurs in this simulation are filtered by the Stratix® V GX ’s PLL) are seen here.
- The first figure is a hybrid eye diagram that includes deterministic jitter and probability density function (PDF) because of unbounded jitter and noise sources.
- The second figure (top right) contains the cumulative distribution (CDF) eye diagram with BER bathtub curves (for both width and height in the eye diagram opening).
- The third plot (lower left) is a BER contour plot that shows the eye diagram opening area at various BER targets.
- The fourth plot shows Q-Factor curves, which are another representation of BER bathtub curve using Q-factor by assuming the noise/jitter is Gaussian.
With the Gaussian random jitter injected into the link, the BER bathtub and Q-Factor plots clearly show the effects where this unbounded jitter narrows the eye diagram width as the BER target reduces.

The second set of TX outputs are measured with the golden CDR, which has a loop bandwidth of 1/1667 of the data rate. This set of outputs reflects the common lab scope measurement. With the golden CDR in place, the low frequency jitter and noise, which are included in phase noise and spurs, are tracked.
The following figure shows the Time Interval Error (TIE) plots before and after the golden CDR. With reference to the ideal clock (that is, before the golden CDR), the low frequency sinusoidal jitter from the reference clock characteristics can be clearly observed in the plot on the left. After the golden CDR, those low frequency sinusoidal jitters are tracked as shown in the plot on the right. The figure also shows the jitter components results that reflect the effects of the golden CDR (Beta feature).

In the following figure, the transmitter output jitter, which includes transmitter intrinsic jitter and PLL filtered reference clock jitter, is about 0.17 UI at BER 10-12.

When you enable a PLL in a transmitter, the reference clock’s phase noise is shaped and filtered with the PLL’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after the transmitter PLL (green), after the transmitter PLL plus the transmitter’s intrinsic jitter (red), after the Golden CDR (most likely in a scope, cyan), and after the Golden CDR with transmitter’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages are calculated and displayed in the text below the plot.

At the channel output, which is located at the end of backplane channel with crosstalk, the eye diagram is largely closed because of the large channel loss from the TX package and the backplane.

The CTLE is a PCI Express* 8GT CTLE behavior model output stage. The Advanced Link Analyzer's link optimization algorithm has identified the optimal gain setting at 10 dB level. Similar to the TX output case, when the receiver CDR is enabled or included in the simulation, two sets of CTLE outputs can be shown but, by default, Advanced Link Analyzer only outputs CDR retimed output when the receiver CDR is enabled. The first set of outputs is with the ideal clock and the second one is with the CDR recovered clock. The total jitter is ~0.94 UI (at BER < 10-12, with ideal clock, result not shown by default because receiver CDR is enabled) or ~0.56 UI (with CDR recovered clock). The eye diagram opening height is ~7 mV (with ideal clock, result not shown by default because receiver CDR is enabled) and ~42 mV (with recovered clock). The eye diagram opening is marginal to PCI Express* 8GT requirements. Therefore, further equalization of the signal with DFE is needed.

When you enable CDR in a receiver, the reference clock’s phase noise is shaped and filtered with the CDR’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after the transmitter PLL (red), after the transmitter PLL plus the transmitter’s intrinsic jitter (red), after the RX CDR (cyan), and after the RX CDR with transmitter and receiver’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages was calculated and displayed in the text below the plot.

At the output of the PCI Express* 8G receiver’s 1-Tap DFE, the following figures show that the DFE has further opened the eye diagram with a total jitter of ~0.96 UI (at BER < 10-12, with ideal clock and sinusoidal jitter from the transmitter reference clock, result not shown by default because receiver CDR is enabled) and ~0.59 UI (with CDR recovered clock) and eye diagram opening height of ~3 mV (with ideal clock, result not shown by default because receiver CDR is enabled) and ~60 mV (with recovered clock). The BER bathtub curve and contour show good behavior and successfully meet the PCI Express* 8GT RX requirements (TJ < 0.7 UI and eye diagram height > 25 mV; refer to PCI Express* Base Specification 4.3).
The PCI Express* 8GT eye diagram mask is shown in the following figure to see the margins to the specification limits.

When you enable a CDR in a receiver, the reference clock’s phase noise is shaped and filtered with the CDR’s response. The following figure shows the characteristics of phase noise at the output of the reference clock (blue), after transmitter PLL (red), after transmitter PLL plus transmitter’s intrinsic jitter (red), after RX CDR (cyan), and after RX CDR with transmitter and receiver’s intrinsic jitter (black). The associated random jitter from the phase noise power spectrum at each of the above stages are calculated and displayed in the text below the plot.

These examples demonstrated how to use Advanced Link Analyzer to set up a serial link and evaluate its link performance. Advanced Link Analyzer allows you to:
- Configure a link
- Configure an external reference clock
- Configure a transmitter and receiver
- Configure a channel
- Configure and model jitter and noise sources
- Derive accurate jitter figures for Intel devices from the Intel JBE database
- Load and save a link configuration
- Observe the channel characteristics
- Set up test points within the link
- Compute and observe an eye diagram
- Perform BER analysis
4. Document Revision History for Advanced Link Analyzer User Guide
Document Version | Changes |
---|---|
2021.04.13 |
|
2020.12.16 |
|
2020.05.05 |
|
2019.11.04 |
|
2019.05.31 |
|
2018.10.29 |
|
2018.05.07 |
|
2017.11.06 |
|
2017.05.08 |
|
2016.10.31 |
|
2016.05.03 |
|
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.06.30 |
|
2013.12.09 | Initial release. |