V-Series Transceiver PHY IP Core User Guide

RSS

UG-01080 | 2017.07.06

Introduction to the Protocol-Specific and Native Transceiver PHYs

The Arria V, Cyclone V, and Stratix V support three types of transceiver PHY implementations or customization.

The three types of transceiver PHY implementations are the following:

Protocol-specific PHY
Non-protocol-specific PHY
Native transceiver PHY

The protocol-specific transceiver PHYs configure the PMA and PCS to implement a specific protocol. In contrast, the native PHY provides broad access to the low-level hardware, allowing you to configure the transceiver to meet your design requirements. Examples of protocol-specific PHYs include XAUI and Interlaken.

You must also include the reconfiguration and reset controllers when you implement a transceiver PHY in your design.

Protocol-Specific Transceiver PHYs

The protocol-specific transceiver PHYs configure many PCS to meet the requirements of a specific protocol, leaving fewer parameters for you to specify.

Altera offers the following protocol-specific transceiver PHYS:

1G/10 Gbps Ethernet
10GBASE-R
Backplane Ethernet 10GBASE-KR PHY
Interlaken
PHY IP Core for PCI Express (PIPE)
XAUI

These transceiver PHYs include an Avalon^® Memory-Mapped (Avalon-MM) interface to access control and status registers and an Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer.

The following figure illustrates the top level modules that comprise the protocol-specific transceiver PHY IP cores. As illustrated, the Altera Transceiver Reconfiguration Controller IP Core is instantiated separately.

Figure 1. Transceiver PHY Top-Level Modules

Native Transceiver PHYs

Each device family, beginning with Series V devices offers a separate Native PHY IP core to provide low-level access to the hardware. There are separate IP Cores for Arria V, Arria V GZ, Cyclone V, and Stratix V devices.

The Native PHYs allow you to customize the transceiver settings to meet your requirements. You can also use the Native PHYs to dynamically reconfigure the PCS datapath. Depending on protocol mode selected, built-in rules validate the options you specify. The following figure illustrates the Stratix V Native PHY.

Figure 2. Stratix V Transceiver Native PHY IP Core

As shown, the Stratix V Native PHY connects to the separately instantiated Transceiver Reconfiguration Controller and Transceiver PHY Reset Controller.

Table 1. Native Transceiver PHY Datapaths
Datapaths	Stratix V	Arria V	Arria V GZ	Cyclone V
PMA Direct: This datapath connects the FPGA fabric directly to the PMA, minimizing latency. You must implement any required PCS functions in the FPGA fabric. ¹	Yes	Yes	Yes	-
Standard: This datapath provides a complete PCS and PMA for the TX and RX channels. You can customize the Standard datapath by enabling or disabling individual modules and specifying data widths.	Yes	Yes	Yes	Yes
10G: This is a high performance datapath. It provides a complete PCS and PMA for the TX and RX channels. You can customize the 10G datapath by enabling or disabling individual modules and specifying data widths.	Yes	-	Yes	-

¹ PMA Direct mode is supported for Arria V GT, ST, and GZ devices, and for Stratix V GT devices only.

Non-Protocol-Specific Transceiver PHYs

Non-protocol specific transceiver PHYs provide more flexible settings than the protocol-specific transceiver PHYs. They include the Custom PHY, Low Latency PHY, and Deterministic Latency PHY IP Cores.

These PHYs include an Avalon® Memory-Mapped (Avalon-MM) interface to access control and status registers and an Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer.

Transceiver PHY Modules

The following sections provide a brief introduction to the modules included in the transceiver PHYs.

PCS

The PCS implements part of the physical layer specification for networking protocols. Depending upon the protocol that you choose, the PCS may include many different functions. Some of the most commonly included functions are: 8B/10B, 64B/66B, or 64B/67B encoding and decoding, rate matching and clock compensation, scrambling and descrambling, word alignment, phase compensation, error monitoring, and gearbox.

PMA

The PMA receives and transmits differential serial data on the device external pins. The transmit (TX) channel supports programmable pre-emphasis and programmable output differential voltage (VOD). It converts parallel input data streams to serial data. The receive (RX) channel supports offset cancellation to correct for process variation and programmable equalization. It converts serial data to parallel data for processing in the PCS. The PMA also includes a clock data recovery (CDR) module with separate CDR logic for each RX channel.

Avalon-MM PHY Management Interface

You can use the Avalon-MM PHY Management module to read and write the control and status registers in the PCS and PMA for the protocol-specific transceiver PHY. The Avalon-MM PHY Management module includes both Avalon-MM master and slave ports and acts as a bridge. It transfers commands received from an embedded controller on its slave port to its master port. The Avalon-MM PHY management master interface connects the Avalon-MM slave ports of PCS and PMA registers and the Transceiver Reconfiguration module, allowing you to manage these Avalon-MM slave components through a simple, standard interface. (Refer to Transceiver PHY Top-Level Modules.)

Transceiver Reconfiguration Controller

Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V, Cyclone V, and Stratix V devices.

Reconfiguration allows you to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. It is required for Arria V, Cyclone V, and Stratix V devices that include transceivers. For more information about the Transceiver Reconfiguration Controller, refer to Transceiver Reconfiguration Controller IP Core. The reset controller may be included in the transceiver PHY or may be a separately instantiated component as described in Transceiver PHY Reset Controller.

Resetting the Transceiver PHY

This section provides an overview of the embedded reset controller and the separately instantiated Transceiver PHY Reset Controller IP Core.

The embedded reset controller ensures reliable transceiver link initialization. The reset controller initializes both the TX and RX channels. You can disable the automatic reset controller in the Custom, Low Latency Transceiver, and Deterministic Latency PHYs. If you disable the embedded reset controller, the powerdown, analog and digital reset signals for both the TX and RX channels are top-level ports of the transceiver PHY. You can use these ports to design a custom reset sequence, or you can use the Altera-provided Transceiver Reset Controller IP Core.

The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the transceiver to enable successful operation. Because the Transceiver PHY Reset Controller IP is available in clear text, you can also modify it to meet your requirements. For more information about the Transceiver PHY Reset Controller, refer to Transceiver Reconfiguration Controller IP Core.

To accommodate different reset requirements for different transceivers in your design, instantiate multiple instances of a PHY IP core. For example, if your design includes 20 channels of the Custom PHY IP core with 12 channels running a custom protocol using the automatic reset controller and 8 channels requiring manual control of RX reset, instantiate 2 instances of the Custom PHY IP core and customize one to use automatic mode and the other to use your own reset logic. For more information, refer to “Enable embedded reset control” in Custom PHY General Options.

For more information about reset control in Stratix V devices, refer to Transceiver Reset Control in Stratix V Devices in volume 3 of the Stratix V Device Handbook. For Stratix IV devices, refer to Reset Control and Power Down in volume 4 of the Stratix IV Device Handbook. For Arria V devices, refer to Transceiver Reset Control and Power-Down in Arria V Devices. For Cyclone V devices refer to Transceiver Reset Control and Power Down in Cyclone V Devices.

Running a Simulation Testbench

When you generate your transceiver PHY IP core, the Quartus^® Prime software generates the HDL files that define your parameterized IP core. In addition, the Quartus^® Prime software generates an example Tcl script to compile and simulate your design in ModelSim.

Figure 3. Directory Structure for Generated Files

The following table describes the key files and directories for the parameterized transceiver PHY IP core and the simulation environment which are in clear text.

Table 2. Transceiver PHY Files and Directories
File Name	Description
<project_dir>	The top-level project directory.
<instance_name> .v or .vhd	The top-level design file.
<instance_name> .qip	A list of all files necessary for Quartus^® Prime compilation.
<instance_name> .bsf	A Block Symbol File (.bsf) for your transceiver PHY.
<project_dir>/<instance_name>/	The directory that stores the HDL files that define the protocol-specific PHY IP core. These files are used for synthesis.
sv_xcvr_native.sv	Defines the transceiver. It includes instantiations of the PCS and PMA modules and Avalon-MM PHY management interface.
stratixv_hssi_ <module_name> _rbc. sv	These files perform rule based checking for the module specified. For example, if the PLL type, data rate, and FPGA fabric transceiver interface width are not compatible, the checker reports an error.
altera_wait_generate.v	Generates waitrequest for protocol-specific transceiver PHY IP core that includes backpressure.
alt_reset_ctrl_tgx_cdrauto.sv	Includes the reset controller logic.
<instance_name> _phy_assignments.qip	Includes an example of the PLL_TYPE assignment statement required to specify the PLL type for each PLL in the design. The available types are clock multiplier unit (CMU) and auxiliary transmit (ATX).
<project_dir>/<instance_name> _sim/ altera_xcvr_ <PHY_IP_name>/	The simulation directory.
<project_dir>/<instance_name>_sim/ aldec	Simulation files for Riviera-PRO simulation tools.
<project_dir>/<instance_name>_sim/ cadence	Simulation files for Cadence simulation tools.
<project_dir>/<instance_name>_sim/ mentor	Simulation files for Mentor simulation tools.
<project_dir>/<instance_name>_sim/ synopsys	Simulation files for Synopsys simulation tools.

The Verilog and VHDL transceiver PHY IP cores have been tested with the following simulators:

ModelSim SE
Synopsys VCS MX
Cadence NCSim

If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus^® Prime software is in VHDL. All the underlying files are written in Verilog or System Verilog.

For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim and QuestaSim Support chapter of the Quartus^® Prime Handbook.

The transceiver PHY IP cores do not support the NativeLink feature in the Quartus^® Prime software.

Generating Custom Simulation Scripts for Multiple Transceiver PHYs with ip-make-simscript

Use the ip-make-simscript utility to generate simulation command scripts for multiple transceiver PHYs or Qsys systems. Specify all Simulation Package Descriptor files (.spd). The .spd files list the required simulation files for the corresponding IP core. The MegaWizard Plug-In Manager and Qsys generate the .spd files.

When you specify multiple .spd files, the ip-make-simscript utility generates a single simulation script containing all required simulation information. The default value of TOP_LEVEL_NAME is the TOP_LEVEL_NAME defined in the IP core or Qsys .spd file. If this is not the top-level instance in your design, specify the top-level instance of your testbench or design.

You can set appropriate variables in the script or edit the variable assignments directly in the script. If the simulation script is a Tcl file that can be sourced in the simulator, set the variables before sourcing the script. If the simulation script is a shell script, pass in the variables as command-line arguments to shell script.

To run ip-make-simscript , type the following at the command prompt:

<ACDS installation path>\quartus\sopc_builder\bin\ip-make-simscript

The following tables lists some of the options available with this utility.

Table 3. Options for the `ip-make-simscript` Utility
Option	Description	Status
`--spd=<file>`	Describes the list of compiled files and memory model hierarchy. If your design includes multiple IP cores or Qsys systems that include .spd files, use this option for each file. For example: `ip-make-simscript --spd=ip1.spd --spd=ip2.spd`	Required
`--output-directory=<directory>`	Directory path specifying the location of output files. If unspecified, the default setting is the directory from which `ip-make-simscript` is run.	Optional
`--compile-to-work`	Compiles all design files to the default work library. Use this option only if you encounter problems managing your simulation with multiple libraries.	Optional
`--use-relative-paths`	Uses relative paths whenever possible	Optional

To learn about all options for the ip-make-simscript , type the following at the command prompt:

<ACDS installation path>\quartus\sopc_builder\bin\ip-make-simscript --help

Unsupported Features

The protocol-specific and native transceiver PHYs are not supported in Qsys in the current release.

Getting Started Overview

This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core.

The Altera IP Library is installed as part of the Quartus^® Prime installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports. The following sections describe the general design flow and use of Altera IP cores.

Installation and Licensing of IP Cores

The Altera IP Library is distributed with the Quartus^® Prime software and downloadable from the Altera website.

The following figure shows the directory structure after you install an Altera IP core, where <path> is the installation directory. The default installation directory on Windows is C:\altera\<version number>; on Linux it is /opt/altera<version number>.

Figure 4. IP Core Directory Structure

You can evaluate an IP core in simulation and in hardware until you are satisfied with its functionality and performance. Some IP cores require that you purchase a license for the IP core when you want to take your design to production. After you purchase a license for an Altera IP core, you can request a license file from the Altera Licensing page of the Altera website and install the license on your computer. For additional information, refer to Altera Software Installation and Licensing.

Design Flows

This section describes how to parameterize Altera IP cores.

You can use the following flow(s) to parameterize Altera IP cores:

Figure 5. Design Flows

The MegaWizard Plug-In Manager flow offers the following advantages:

Allows you to parameterize an IP core variant and instantiate into an existing design
For some IP cores, this flow generates a complete example design and testbench

² Altera IP cores may or may not support the Qsys and SOPC Builder design flows.

MegaWizard Plug-In Manager Flow

This section describes how to specify parameters and simulate your IP core with the MegaWizard Plug-In Manager.

The MegaWizard™ Plug-In Manager flow allows you to customize your IP core and manually integrate the function into your design.

Specifying Parameters

To specify IP core parameters, follow these steps:

Create a Quartus^® Prime project using the New Project Wizard available from the File menu.
In the Quartus^® Prime software, launch the IP Catalog.
You can select the IP core for your protocol implementation from the IP Catalog.
Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the "Parameter Settings" chapter in this document or the "Documentation" button in the MegaWizard parameter editor.

Note: Some IP cores provide preset parameters for specific applications. If you wish to use preset parameters, click the arrow to expand the Presets list, select the desired preset, and then click Apply. To modify preset settings, in a text editor modify the <installation directory>/ip/altera/ alt_mem_if_interfaces/alt_mem_if_<memory_protocol>_emif/ alt_mem_if_<memory_protocol>_mem_model.qprs file.
If the IP core provides a simulation model, specify appropriate options in the wizard to generate a simulation model.
Note:
- Altera IP supports a variety of simulation models, including simulation‑specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle‑accurate models. The models allow for fast functional simulation of your IP core instance using industry‑standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model.
- For more information about functional simulation models for Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Quartus^® Prime Handbook.
CAUTION:

Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.
If the parameter editor includes EDA and Summary tabs, follow these steps:
1. Some third-party synthesis tools can use a netlist that contains the structure of an IP core but no detailed logic to optimize timing and performance of the design containing it. To use this feature if your synthesis tool and IP core support it, turn on Generate netlist.
2. On the Summary tab, if available, select the files you want to generate. A gray checkmark indicates a file that is automatically generated. All other files are optional.
  
  Note: If file selection is supported for your IP core, after you generate the core, a generation report (<variation name>.html)appears in your project directory. This file contains information about the generated files.
Click the Finish button, the parameter editor generates the top-level HDL code for your IP core, and a simulation directory which includes files for simulation.

Note: The Finish button may be unavailable until all parameterization errors listed in the messages window are corrected.
Click Yes if you are prompted to add the Quartus^® Prime IP File (.qip) to the current Quartus^® Prime project. You can also turn on Automatically add Quartus^® Prime IP Files to all projects.

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

For some IP cores, the generation process also creates complete example designs. An example design for hardware testing is located in the < variation_name > _example_design/example_project/ directory. An example design for RTL simulation is located in the < variation_name > _example_design/simulation/ directory.

Note: For information about the Quartus^® Prime software, including virtual pins, refer to Quartus^® Prime Help.

Simulate the IP Core

This section describes how to simulate your IP core.

You can simulate your IP core variation with the functional simulation model and the testbench or example design generated with your IP core. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench.

For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench.

For more information about simulating Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Quartus^® Prime Handbook.

10GBASE-R PHY IP Core

The Altera 10GBASE-R PHY IP Core implements the functionality described in IEEE Standard 802.3 Clause 45.

It delivers serialized data to an optical module that drives optical fiber at a line rate of 10.3125 gigabits per second (Gbps). In a multi-channel implementation of 10GBASE-R, each channel of the 10GBASE-R PHY IP Core operates independently. Both the PCS and PMA of the 10GBASE-R PHY are implemented as hard IP blocks in Stratix V devices, saving FPGA resources.

Figure 6. 10GBASE-R PHY with Hard PCS with PMA in Stratix V Devices

Note: For a 10-Gbps Ethernet solution that includes both the Ethernet MAC and the 10GBASE-R PHY, refer to the 10-Gbps Ethernet MAC MegaCore Function User Guide.

Note: For more detailed information about the 10GBASE-R transceiver channel datapath, clocking, and channel placement, refer to the “10GBASE-R” section in the Transceiver Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.

The following figure illustrates a multiple 10 GbE channel IP core in a Stratix IV GT device. To achieve higher bandwidths, you can instantiate multiple channels. The PCS is available in soft logic for Stratix IV GT devices; it connects to a separately instantiated hard PMA. The PCS connects to an Ethernet MAC via single data rate (SDR) XGMII running at 156.25 megabits per second (Mbps) and transmits data to a 10 Gbps transceiver PMA running at 10.3125 Gbps in a Stratix IV GT device.

To make the most effective use of this soft PCS and PMA configuration for Stratix IV GT devices, you can group up to four channels in a single quad and control their functionality using one Avalon-MM PHY management bridge, transceiver reconfiguration module, and low controller. As this figure illustrates, the Avalon-MM bridge Avalon-MM master port connects to the Avalon-MM slave port of the transceiver reconfiguration and low latency controller modules so that you can update analog settings using the standard Avalon-MM interface.

Note: This configuration does not require that all four channels in a quad run the 10GBASE-R protocol.

Figure 7. Complete 10GBASE-R PHY Design in Stratix IV GT Device

The following figures illustrate the 10GBASE-R in Arria V GT, Arria V GZ, and Stratix V GX devices.

Figure 8. 10GBASE-R PHY IP Core In Arria V GT Devices

Figure 9. 10GBASE-R PHY IP Core In Arria V GZ Devices

Figure 10. 10GBASE-R PHY IP Core In Stratix V Devices

The following table lists the latency through the PCS and PMA for Arria V GT devices with a 66-bit PMA. The FPGA fabric to PCS interface is 64 bits wide. The frequency of the parallel clock is 156.25 MHz which is line rate (10.3125 Gpbs)/interface width (64).

Table 4. Latency for TX and RX PCS and PMA Arria V Devices
	PCS (Parallel Clock Cycles	PMA (UI)
TX	28	131
RX	33	99

The following table lists the latency through the PCS and PMA for Stratix V devices with a 40-bit PMA. The FPGA fabric to PCS interface is 64 bits wide. The frequency of the parallel clock is 156.25 MHz which is line rate (10.3125 Gbps)/interface width (64).

Table 5. Latency for TX and RX PCS and PMA Stratix V Devices
	PCS (Parallel Clock Cycles)				PMA (UI)
	32-bit PMA Width		40-bit PMA Width
	Minimum	Maximum	Minimum	Maximum
TX	7	12	8	12	124
RX	14	33	15	34	43

10GBASE-R PHY Release Information

Release information for the IP core.

Table 6. 10GBASE-R Release Information
Item	Description
Version	13.1
Release Date	November 2013
Ordering Codes³	IP-10GBASERPCS (primary) IPR-10GBASERPCS (renewal)
Product ID	00D2
Vendor ID	6AF7

³ No ordering codes or license files are required for Stratix V devices.

10GBASE-R PHY Device Family Support

Device support for the IP core.

IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions:

Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.

Table 7. Device Family Support
Device Family	Support
Arria V GT devices–Soft PCS and Hard PMA	Final
Arria V ST devices-Soft PCS and Hard PMA	Final
Arria V GZ	Final
Stratix IV GT devices–Soft PCS and Hard PMA	Final
Stratix V devices–Hard PCS and PMA	Final
Other device families	No support

Note: For speed grade information, refer to “Transceiver Performance Specifications” in the DC and Switching Characteristics chapter in the Stratix IV Handbook for Stratix IV devices or Stratix V Device Datasheet.

10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices

Because the 10GBASE-R PHY is implemented in hard logic it uses less than 1% of the available ALMs, memory, primary and secondary logic registers. The following table lists the typical expected device resource utilization for duplex channels using the current version of the Quartus^® Prime software targeting a Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100.

Table 8. 10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device
Channels	Combinational ALUTs	Logic Registers (Bits)	Memory Bits
1	5200	4100	4700
4	15600	1300	18800
10	38100	32100	47500

10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices

The following table lists the resource utilization when targeting an Arria V (5AGTFD7K3F4015) device. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v12.1 release for 28 nm device families and upcoming device families. The numbers of ALMs and logic registers are rounded up to the nearest 100.

Note: For information about Quartus^® Prime resource utilization reporting, refer to Fitter Resources Reports in the Quartus^® Prime Help.

Table 9. 10GBASE-R PHY Performance and Resource Utilization—Arria V GT Device
Channels	ALMs	Primary Logic Registers	Secondary Logic Registers	Memory 10K
1	2800	3000	300	7

10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices

Because the 10GBASE-R PHY is implemented in hard logic in Arria V GZ and Stratix V devices, it uses less than 1% of the available ALMs, memory, primary and secondary logic registers.

The following table lists the total latency for an Ethernet packet with a 9600 byte payload and an inter-packet gap of 12 characters. The latency includes the number of cycles to transmit the payload from the TX XGMII interface, through the TX PCS and PMA, looping back through the RX PMA and PCS to the RX XGMII interface. (Stratix V Clock Generation and Distribution illustrates this datapath.)

Table 10. Latency
PPM Difference	Cycles
0 PPM	35
-200 PPM	35
+200 PPM	42

Note: If latency is critical, Altera recommends designing your own soft 10GBASE-R PCS and connecting to the Low Latency PHY IP Core.

Parameterizing the 10GBASE-R PHY

The 10GBASE-R PHY IP Core is available for the Arria V, Arria V GZ, Stratix IV, or Stratix V device families. Complete the following steps to configure the 10GBASE-R PHY IP Core:

Under Tools > IP Catalog, select the device family of your choice.
Under Tools > IP Catalog > Interface Protocols > Ethernet > select 10GBASE-R PHY.
Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
Refer to the following topics to learn more about the parameters:
1. General Option Parameters
2. Analog Parameters for Stratix IV Devices
Click Finish to generate your parameterized 10GBASE-R PHY IP Core.

General Option Parameters

This section describes general parameters.

This section describes the 10GBASE-R PHY parameters, which you can set using the MegaWizard Plug-In Manager.

Table 11. General Options
Name	Value	Description
General Options
Device family	Arria V Arria V GZ Stratix IV GT Stratix V	Specifies the target device.
Number of channels	`1-32`	The total number of 10GBASE-R PHY channels.
Mode of operation	Duplex TX Only RX Only	Arria V and Stratix V devices allow duplex, TX, or RX mode. Stratix IV GT devices only support duplex mode.
PLL type	CMU, ATX	For Arria V GZ, Stratix IV, and Stratix V devices: You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does. Altera recommends the ATX PLL for data rates <= 8 Gbps.
Reference Clock Frequency	322.265625 MHz 644.53125 MHz	Arria V and Stratix V devices support both frequencies. Stratix IV GT devices only support 644.53125 MHz.
PCS / PMA interface width	32 40	For Stratix V and Arria V GZ devices only: Specifies the data interface width between the 10G PCS and the transceiver PMA. Smaller width corresponds to lower PCS latency but higher frequency. For 40 bit width, rx_recovered_clock is 257.8125 MHz and the gearbox ratio is 66:40. For 40 bit width, rx_recovered_clock is 322.265626 MHz and the gearbox ratio is 66:32. 32 bit PCS / PMA interface with does not support data rates up to 10.3125 Gbps in C4/I4 Arria V GZ device variants. Refer to Arria V GZ Device Datasheet for details on data rates supported by different device variants.
Additional Options
Enable additional control and status pins	On/Off	If you turn this option On, the following 2 signals are brought out to the top level of the IP core to facilitate debugging: rx_hi_ber and rx_block_lock.
Enable rx_recovered_clk pin	On/Off	When you turn this option On, the RX recovered clock signal is an output signal.
Enable pll_locked status port	On/Off	For Arria V and Stratix V devices: When you turn this option On, a PLL locked status signal is included as a top-level signal of the core.
Use external PMA control and reconfig	On/Off	For Stratix IV devices: If you turn this option on, the PMA controller and reconfiguration block are external, rather than included in the 10GBASE-R PHY IP Core, allowing you to use the same PMA controller and reconfiguration IP cores for other protocols in the same transceiver quad. When you turn this option On, the `cal_blk_powerdown` (0x021) and `pma_tx_pll_is_locked` (0x022) registers are available.
Enable rx_coreclkin port	On/Off	When selected, `rx_coreclkin` is sourced from the 156.25 MHz `xgmii_rx_clk` signal avoiding the use of a FPLL to generate this clock. This clock drives the read side of RX FIFO.
Enable embedded reset control	On/Off	When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using `tx_analogreset` , `rx_analogreset`, `tx_digitalreset`, `rx_digitalreset`, and `pll_powerdown` which are top‑level ports of the Custom Transceiver PHY. You may also use the Transceiver PHY Reset Controller to reset the transceivers. For more information, refer to the Transceiver Reconfiguration Controller IP Core . By default, the CDR circuitry is in automatic lock mode whether you use the embedded reset controller or design your own reset logic. You can switch the CDR to manual mode by writing the `pma_rx_setlocktodata` or `pma_rx_set_locktoref` registers to 1. If either the `pma_rx_set_locktodata` and `pma_rx_set_locktoref` is set, the CDR automatic lock mode is disabled.
Starting channel number	0-96	For Stratix IV devices, specifies the starting channel number. Must be 0 or a multiple of 4. You only need to set this parameter if you are using external PMA and reconfiguration modules. In Stratix V devices, by default, the logical channel 0 is assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane assignment for logical channel 0, you can use the work around shown in the example below. Assignment of the starting channel number is required for serial transceiver dynamic reconfiguration.
Enable IEEE 1588 latency adjustment ports	On/Off	When you turn this option On, the core includes logic to implement the IEEE 1588 Precision Time Protocol.

Changing the Default Logical Channel 0 Channel Assignments in Stratix V Devices for ×6 or ×N Bonding

This example shows how to change the default logical channel 0 assignment in Stratix V devices by redefining the pma_bonding_master parameter using the Quartus^® Prime Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the 10GBASE-R instance name. You must substitute the instance name from your design for the instance name shown in quotation marks.

set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"

Analog Parameters for Stratix IV Devices

For Stratix IV devices, you specify analog options on the Analog Options tab.

Table 12. PMA Analog Options for Stratix IV Devices
Name	Value	Description
Transmitter termination resistance	OCT_85_OHMS, OCT_100_OHMS, OCT_120_OHMS, OCT_150_OHMS	Indicates the value of the termination resistor for the transmitter.
Transmitter V_OD control setting	0–7	Sets V_OD for the various TX buffers.
Pre-emphasis pre-tap setting	0–7	Sets the amount of pre-emphasis on the TX buffer.
Invert the pre-emphasis pre-tap polarity setting	On, Off	Determines whether or not the pre-emphasis control signal for the pre-tap is inverted. If you turn this option on, the pre-emphasis control signal is inverted.
Pre-emphasis first post-tap setting	0-15	Sets the amount of pre-emphasis for the 1st post-tap.
Pre-emphasis second post-tap setting	0–7	Sets the amount of pre-emphasis for the 2nd post-tap.
Invert the pre-emphasis second post-tap polarity	On, Off	Determines whether or not the pre-emphasis control signal for the second post-tap is inverted. If you turn this option on, the pre-emphasis control signa is inverted.
Receiver common mode voltage	Tri-State 0.82V 1.1v	Specifies the RX common mode voltage.
Receiver termination resistance	OCT_85_OHMS OCT_100_OHMs OCT_120_OHMS OCT_150_OHMS	Indicates the value of the termination resistor for the receiver.
Receiver DC	0-4	Sets the equalization DC gain using one of the following settings: 0: 0 dB 1: 3 dB 2: 6 dB 3: 9 dB 4: 12 dB
Receiver static equalizer setting:	0-15	This option sets the equalizer control settings. The equalizer uses a pass band filter. Specifying a low value passes low frequencies. Specifying a high value passes high frequencies.

Analog Parameters for Arria V, Arria V GZ, and Stratix V Devices

Click on the appropriate links to review the analog parameters for these devices.

10GBASE-R PHY Interfaces

This section describes the 10GBASE-R PHY interfaces.

The following figure illustrates the top-level signals of the 10BASE-R PHY; <n> is the channel number.

Figure 11. 10GBASE-R PHY Top-Level Signals

Note: The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the Hardware Component Description File (_hw.tcl). If you turn on Show signals, the block diagram displays all top-level signal names.

For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus^® Prime Handbook.

10GBASE-R PHY Data Interfaces

This section describes the 10GBASE-R PHY data interfaces.

The TX signals are driven from the MAC to the PCS. The RX signals are driven from the PCS to the MAC.

Table 13. SDR XGMII TX Inputs
Signal Name	Direction	Description
XGMII TX Interface
`xgmii_tx_dc_[<n>71:0]`	Input	Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control. Lane 0-[7:0]/[8] Lane 1-[16:9]/[17] Lane 2-[25:18]/[26] Lane 3-[34:27]/[35] Lane 4-[43:36]/[44] Lane 5-[52:45]/[53] Lane 6-[61:54]/[62] Lane 7-[70:63]/[71] Refer toTable 2 for the mapping of the `xgmii_tx_dc` data and control to the `xgmii_sdr_data` and `xgmii_sdr_ctrl` signals.
`tx_ready`	Output	Asserted when the TX channel is ready to transmit data. Because the `readyLatency` on this Avalon-ST interface is 0, the MAC may drive `tx_ready` as soon as it comes out of reset.
`xgmii_tx_clk`	Input	The XGMII TX clock which runs at 156.25 MHz. Connect `xgmii_tx_clk` to `xgmii_rx_clk` to guarantee this clock is within 150 ppm of the transceiver reference clock.
XGMII RX Interface
`xgmii_rx_dc_<n>[71:0]`	Output	Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control. Lane 0-[7:0]/[8] Lane 1-[16:9]/[17] Lane 2-[25:18]/[26] Lane 3-[34:27]/[35] Lane 4-[43:36]/[44] Lane 5-[52:45]/[53] Lane 6-[61:54]/[62] Lane 7-[70:63]/[71] Refer toTable 3 for the mapping of the `xgmii_rx_dc` data and control to the `xgmii_sdr_data` and `xgmii_sdr_ctrl` signals.
`rx_ready`	Output	Asserted when the RX reset is complete.
`rx_data_ready [<n>-1:0]`	Output	When asserted, indicates that the PCS is sending data to the MAC. Because the `readyLatency` on this Avalon-ST interface is 0, the MAC must be ready to receive data whenever this signal is asserted. After `rx_ready` is asserted indicating the exit from the reset state, the MAC should store `xgmii_rx_dc_<n>[71:0]` in each cycle where `rx_data_ready<n>` is asserted.
`xgmii_rx_clk`	Output	This clock is generated by the same reference clock that is used to generate the transceiver clock. Its frequency is 156.25 MHz. Use this clock for the MAC interface to minimize the size of the FIFO between the MAC and SDR XGMII RX interface.
`rx_coreclkin`	Input	When you turn on Create `rx_coreclkin` port, this signal is available as a 156.25 MHz clock input port to drive the RX datapath interface (RX read FIFO).
Serial Interface
`rx_serial_data_<n>`	Input	Differential high speed serial input data using the PCML I/O standard. The clock is recovered from the serial data stream.
`tx_serial_data_<n>`	Output	Differential high speed serial input data using the PCML I/O standard. The clock is embedded from the serial data stream.

Table 14. Mapping from XGMII TX Bus to XGMII SDR Bus
Signal Name	XGMII Signal Name	Description
`xgmii_tx_dc_[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_tx_dc_[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_tx_dc_[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_tx_dc_[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_tx_dc_[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_tx_dc_[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_tx_dc_[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_tx_dc_[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_tx_dc_[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_tx_dc_[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_tx_dc_[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_tx_dc_[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_tx_dc_[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_tx_dc_[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_tx_dc_[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_tx_dc_[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

Table 15. Mapping from XGMII RX Bus to the XGMII SDR Bus
Signal Name	XGMII Signal Name	Description
`xgmii_rx_dc_[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_rx_dc_[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_rx_dc_[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_rx_dc_[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_rx_dc_[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_rx_dc_[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_rx_dc_[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_rx_dc_[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_rx_dc_[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_rx_dc_[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_rx_dc_[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_rx_dc_[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_rx_dc_[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_rx_dc_[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_rx_dc_[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_rx_dc_[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces

This section describes the 10GBASE-R PHY status, 1588, and PLL reference clock interfaces.

Table 16. 10GBASE-R Status, 1588, and PLL Reference Clock Outputs
Signal Name	Direction	Description
`rx_block_lock`	Output	Asserted to indicate that the block synchronizer has established synchronization.
`rx_hi_ber`	Output	Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10^-4.
`rx_recovered_clk[<n>:0]`	Output	This is the RX clock, which is recovered from the received data stream.
`pll_locked`	Output	When asserted, indicates that the TX PLL is locked.
IEEE 1588 Precision Time Protocol
`rx_latency_adj_10g [15:0]`	Output	When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
`tx_latency_adj_10g [15:0]`	Output	When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.25 MHz) for the TX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
PLL Reference Clock
`pll_ref_clk`	Input	For Stratix IV GT devices, the TX PLL reference clock must be 644.53125 MHz. For Arria V and Stratix V devices, the TX PLL reference clock can be either 644.53125 MHz or 322.265625 MHz.

10GBASE-R PHY Clocks for Arria V GT Devices

The following figure illustrates Arria V GT clock generation and distribution.

Figure 12. Arria V GT Clock Generation and Distribution

10GBASE-R PHY Clocks for Arria V GZ Devices

The following figure illustrates clock generation and distribution for Arria V GZ devices.

Figure 13. Arria V GZ Clock Generation and Distribution

10GBASE-R PHY Clocks for Stratix IV Devices

The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY. A positive edge on this signal triggers a reset.

Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device Handbook for additional information about reset sequences in Stratix IV devices.

The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA an input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock.

Figure 14. Stratix IV Clock Generation and Distribution

10GBASE-R PHY Clocks for Stratix V Devices

The following figure illustrates clock generation and distribution in Stratix V devices.

Figure 15. Stratix V Clock Generation and Distribution

To ensure proper functioning of the PCS, the maximum PPM difference between the pll_ref_clk and xgmii_tx_clk clock inputs is 0 PPM. The FIFO in the RX PCS can compensate ±100 PPM between the RX PMA clock and xgmii_rx_clk. You should use xgmii_rx_clk to drive xgmii_tx_clk. The CDR logic recovers 257.8125 MHz clock from the incoming data.

10GBASE-R PHY Register Interface and Register Descriptions

The Avalon-MM PHY management interface provides access to the 10GBASER-R PHY PCS and PMA registers. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.

Table 18. Avalon-MM PHY Management Interface
Signal Name	Direction	Description
`phy_mgmt_clk`	Input	The clock signal that controls the Avalon-MM PHY management, interface. For Stratix IV devices, the frequency range is 37.5-50 MHz. There is no frequency restriction for Stratix V devices; however, if you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range of `phy_mgmt_clk` to 100-150 MHz to meet the specification for the transceiver reconfiguration clock.
`phy_mgmt_clk_reset`	Input	Global reset signal that resets the entire 10GBASE-R PHY. This signal is active high and level sensitive. This signal is not synchronized internally.
`phy_mgmt_addr[8:0]`	Input	9-bit Avalon-MM address.
`phy_mgmt_writedata[31:0]`	Input	Input data.
`phy_mgmt_readdata[31:0]`	Output	Output data.
`phy_mgmt_write`	Input	Write signal. Asserted high.
`phy_mgmt_read`	Input	Read signal. Asserted high.
`phy_mgmt_waitrequest`	Output	When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

Refer to the “Typical Slave Read and Write Transfers” and “Master Transfers” sections in the “Avalon Memory-Mapped Interfaces” chapter of the Avalon Interface Specifications for timing diagrams.

The following table specifies the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

Note: Writing to reserved or undefined register addresses may have undefined side effects.

Table 19. 10GBASE-R Register Descriptions
Word Addr	Bit	R/W	Name	Description
PMA Common Control and Status
0x021	[31:0]	RW	`cal_blk_powerdown`	Writing a 1 to channel <`n`> powers down the calibration block for channel <`n`>. This register is only available if you select Use external PMA control and reconfig on the Additional Options tab of the GUI.
0x022	[31:0]	RO	`pma_tx_pll_is_locked`	Bit[P] indicates that the TX clock multiplier unit CMU PLL [P] is locked to the input reference clock. This register is only available if you select Use external PMA control and reconfig on the Additional Options tab of the GUI.
Reset Control Registers-Automatic Reset Controller
0x041	[31:0]	RW	`reset_ch_bitmask`	Reset controller channel bitmask for digital resets. The default value is all 1 s. Channel <`n`> can be reset when bit<`n`> = 1. Channel <`n`> cannot be reset when bit<`n`>=0.
0x042	[1:0]	WO	`reset_control` (write)	Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the `reset_ch_bitmask`. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the `reset_ch_bitmask`. Both bits 0 and 1 self-clear.
0x042	[1:0]	RO	`reset_status` (read)	Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit.
0x044	[31:0]	RW	`reset_fine_control`	You can use the `reset_fine_control`register to create your own reset sequence. The reset control module performs a standard reset sequence at power on and whenever the `phy_mgmt_clk_reset` is asserted. Bits [31:4,0] are reserved.
	[31:4,0]	RW	Reserved	It is safe to write 0s to reserved bits.
	[1]	RW	`reset_tx_digital`	Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in `reset_ch_bitmask`. You must write a 0 to clear the reset condition.
	[2]	RW	`reset_rx_analog`	Writing a 1 causes the internal RX digital reset signal to be asserted, resetting the RX analog logic of all channels enabled in `reset_ch_bitmask`. You must write a 0 to clear the reset condition.
	[3]	RW	`reset_rx_digital`	Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in `reset_ch_bitmask`. You must write a 0 to clear the reset condition.
PMA Channel Control and Status
0x061	[31:0]
0x061	[31:0]	RW	`phy_serial_loopback`	Writing a 1 to channel <`n`> puts channel <`n`> in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback Modes.
0x064	[31:0]	RW	`pma_rx_set_locktodata`	When set, programs the RX CDR PLL to lock to the incoming data. Bit <`n`> corresponds to channel <`n`>.
0x065	[31:0]	RW	`pma_rx_set_locktoref`	When set, programs the RX CDR PLL to lock to the reference clock. Bit <`n`> corresponds to channel <`n`>.
0x066	[31:0]	RO	`pma_rx_is_lockedtodata`	When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <`n`> corresponds to channel <`n`>.
0x067	[31:0]	RO	`pma_rx_is_lockedtoref`	When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <`n`> corresponds to channel <`n`>.
10GBASE-R PCS
0x080	[31:0]	WO	`INDIRECT_ADDR`
0x080	[31:0]	WO	`INDIRECT_ADDR`	Provides for indirect addressing of all PCS control and status registers. Use this register to specify the logical channel number of the PCS channel you want to access.
0x081	[2]	RW	`RCLR_ERRBLK_CNT`	When set to 1, clears the error block count register. To block: Block synchronizer
0x081	[3]	RW	`RCLR_BER_COUNT`	When set to 1, clears the bit error rate (BER) register. To block: BER monitor
0x082	[0]	R	`PCS_STATUS`	For Stratix IV devices: When asserted indicates that the PCS link is up.
	[1]	R	`HI_BER`	When asserted by the BER monitor block, indicates that the PCS is recording a high BER. From block: BER monitor
	[2]	R	`BLOCK_LOCK`	When asserted by the block synchronizer, indicates that the PCS is locked to received blocks. From Block: Block synchronizer
	[3]	R	`TX_FIFO_FULL`	When asserted, indicates the TX FIFO is full. From block: TX FIFO
	[4]	R	`RX_FIFO_FULL`	When asserted, indicates the RX FIFO is full. From block: RX FIFO
	[5]	R	`RX_SYNC_HEAD_ERROR`	For Stratix V devices, when asserted, indicates an RX synchronization error. This signal is Stratix V devices only.
	[6]	R	`RX_SCRAMBLER_ERROR`	For Stratix V devices: When asserted, indicates an RX scrambler error.
	[7]	R	`RX_DATA_READY`	When asserted indicates that the RX interface is ready to send out received data. From block: 10 Gbps Receiver PCS
0x083	[5:0]	R	`BER_COUNT[5:0]`	For Stratix IV devices only, records the bit error rate (BER). From block: BER monitor
	[13:6]	R	`ERROR_BLOCK_COUNT[7:0]`	For Stratix IV devices only, records the number of blocks that contain errors. From Block: Block synchronizer
	[14]	R	`LATCHED_HI_BER`	Latched version of `HI_BER`. From block: BER monitor
	[15]	R	`LATCHED_BLOCK_LOCK`	Latched version of `BLOCK_LOCK`. From Block: Block synchronizer

10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices

The 10GBASE-R PHY includes additional top-level signals when configured with an external modules for PMA control and dynamic reconfiguration.

You enable this configuration by turning on Use external PMA control and reconfig available for Stratix IV GT devices.

Table 20. External PMA and Reconfiguration Signals
Signal Name	Direction	Description
`gxb_pdn`	Input	When asserted, powers down the entire GT block. Active high. For Stratix IV de
`pll_pdn`	Input	When asserted, powers down the TX PLL. Active high.
`cal_blk_pdn`	Input	When asserted, powers down the calibration block. Active high.
`cal_blk_clk`	Input	Calibration clock. For Stratix IV devices only. It must be in the range 37.5-50 MHz. You can use the same clock for the `phy_mgmt_clk` and the `cal_blk_clk`.
`pll_locked`	Output	When asserted, indicates that the TX PLL is locked.
`reconfig_to_xcvr[3:0]`	Input	Reconfiguration signals from the Transceiver Reconfiguration Controller to the PHY device. This signal is only available in Stratix IV devices.
`reconfig_from_xcvr [(<n>/4)17-1:0]`	Output	Reconfiguration RAM. The PHY device drives this RAM data to the transceiver reconfiguration IP. This signal is only available in Stratix IV devices.

10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices

For Arria V and Stratix V devices, each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The example below shows the messages for a single duplex channel.

Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design, when the Quartus^® Prime software compiles your design, it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration Controllers. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfiguration Controller to PHY IP Connectivity. Allowing the Quartus^® Prime software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels.

Informational Messages for the Transceiver Reconfiguration Interface

Reconfiguration interface offset 0 is connected to the transceiver channel.

PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller.

Reconfiguration interface offset 0 is connected to the transceiver channel.

Reconfiguration interface offset 1 is connected to the transmit PLL.

The following table describes the signals in the reconfiguration interface; this interface uses the Avalon-MM PHY Management interface clock.

Table 21. Reconfiguration Interface
Signal Name	Direction	Description
`reconfig_to_xcvr` `[(<n>70-1):0]`	Input	Reconfiguration signals from the Transceiver Reconfiguration Controller. <`n`> grows linearly with the number of reconfiguration interfaces. This signal is only available in Stratix V devices.
`reconfig_from_xcvr` `[(<n>46-1):0]`	Output	Reconfiguration signals to the Transceiver Reconfiguration Controller. <`n`> grows linearly with the number of reconfiguration interfaces. This signal is only available in Stratix V devices.

1588 Delay Requirements

The 1588 protocol requires symmetric delays or known asymmetric delays for all external connections.

In calculating the delays for all external connections, you must consider the delay contributions of the following elements:

The PCB traces
The backplane traces
The delay through connectors
The delay through cables

Accurate calculation of the channel-to-channel delay is important in ensuring the overall system accuracy.

10GBASE-R PHY TimeQuest Timing Constraints

The timing constraints for Stratix IV GT designs are in alt_10gbaser_phy.sdc. If your design does not meet timing with these constraints, use LogicLock™ for the alt_10gbaser_pcs block. You can also apply LogicLock to the alt_10gbaser_pcs and slightly expand the lock region to meet timing.

The following example provides the Synopsys Design Constraints file (.sdc) timing constraints for the 10GBASE-R IP Core when implemented in a Stratix IV device. To pass timing analysis, you must decouple the clocks in different time domains. Be sure to verify the each clock domain is correctly buffered in the top level of your design. You can find the .sdc file in your top-level working directory. This is the same directory that includes your top-level .v or .vhd file.

Synopsys Design Constraints for Clocks

#**************************************************************
# Timing Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clocks
#**************************************************************
create_clock -name {xgmii_tx_clk} -period 6.400 -waveform { 0.000 3.200 } [get_ports {xgmii_tx_clk}]
create_clock -name {phy_mgmt_clk}   -period 20.00 -waveform { 0.000 10.000 } [get_ports {phy_mgmt_clk}]
create_clock -name {pll_ref_clk} -period 1.552 -waveform { 0.000 0.776  } [get_ports {ref_clk}]
#derive_pll_clocks
derive_pll_clocks -create_base_clocks
#derive_clocks -period "1.0"
# Create Generated Clocks
#**************************************************************
create_generated_clock -name pll_mac_clk -source [get_pins -compatibility_mode {*altpll_component|auto_generated|pll1|clk[0]}] 
create_generated_clock -name pma_tx_clk -source [get_pins -compatibility_mode {*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] 
**************************************************************
## Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
derive_clock_uncertainty
set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -to pll_ref_clk -setup 0.1
set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -setup 0.08
set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -to pll_ref_clk -hold 0.1
set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -hold 0.08
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************# Set Clock Groups
#**************************************************************
set_clock_groups -exclusive -group phy_mgmt_clk -group xgmii_tx_clk -group [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}] -group [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -group [get_clocks {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]}] 
##**************************************************************
# Set False Path
#**************************************************************
set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|rx_pma_rstn} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout} {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|rx_usr_rstn} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}  {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|tx_pma_rstn} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}  {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|tx_usr_rstn} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}  {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
set_false_path -from {*siv_10gbaser_xcvr*rx_analog_rst_lego|rinit} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}  {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
set_false_path -from {*siv_10gbaser_xcvr*rx_digital_rst_lego|rinit} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout} {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}  {*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk xgmii_tx_clk}]
#**************************************************************
# Set Multicycle Paths
#**************************************************************
**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

Note: This .sdc file is only applicable to the 10GBASE-R PHY IP Core when compiled in isolation. You can use it as a reference to help in creating your own .sdc file.

Note: For Arria V and Stratix V devices, timing constraints are built into the HDL code.

Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V Native PHY for details.

10GBASE-R PHY Simulation Files and Example Testbench

Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus^® Prime software creates automatically when you generate your 10GBASE-R PHY IP Core.

Backplane Ethernet 10GBASE-KR PHY IP Core

The Backplane Ethernet 10GBASE-KR PHY MegaCore® function is available for Stratix® V and Arria V GZ devices.

This transceiver PHY allows you to instantiate both the hard Standard PCS and the higher performance hard 10G PCS and hard PMA for a single Backplane Ethernet channel. It implements the functionality described in the IEEE Std 802.3ap-2007 Standard. Because each instance of the 10GBASE-KR PHY IP Core supports a single channel, you can create multi-channel designs by instantiating more than one instance of the core. The following figure shows the 10GBASE-KR transceiver PHY and additional blocks that are required to implement this core in your design.

Figure 16. 10GBASE-KR PHY MegaCore Function and Supporting Blocks

The Backplane Ethernet 10GBASE-KR PHY IP Core includes the following new modules to enable operation over a backplane:

Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the link-partner TX PMDs for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
Auto negotiation (AN)—The Altera 10GBASE-KR PHY IP Core can auto-negotiate between 1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std 802.3ap-2007.
Forward Error Correction—Forward Error Correction (FEC) function is an optional feature defined in Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism allowing noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10^-12 .

10GBASE-KR PHY Release Information

Table 22. 10GBASE-KR PHY Release Information
Item	Description
Version	13.1
Release Date	November 2013
Ordering Codes	IP-10GBASEKR PHY (primary)
Product ID	0106
Vendor ID	6AF7

10GBASE-KR PHY Performance and Resource Utilization

This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V devices.

The following table shows the typical expected resource utilization for selected configurations using the current version of the Quartus^® Prime software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v14.1 release for 28 nm device families and upcoming device families.

Table 24. 10GBASE-KR PHY Performance and Resource Utilization
Module Options	ALMs	Logic Registers	Memory
10GBASE-KR PHY only, no AN or LT	400	700	0
10GBASE-KR PHY with AN and Sequencer	1000	1700	0
10GBASE-KR PHY with LT and Sequencer,	2100	2300	0
10GBASE-KR PHY with AN, LT, and Sequencer	2700	3300	0
10GBASE-KR MIF, Port A depth 256, width 16, ROM (For reconfiguration from low latency or 1GbE mode)	0	0	1 (M20K)
Low Latency MIF, Port A depth 256, width 16, ROM (Required for auto-negotiation and link training.)	0	0	1 (M20K)
10GBASE-KR PHY with FEC	3700	5100	40 (M20K)

Parameterizing the 10GBASE-KR PHY

The10GBASE-KR PHY IP Core is available for the Arria V GZ and Stratix V device families. The IP variant allows you specify either the Backplane-KR or 1Gb/10Gb Ethernet variant. When you select the Backplane-KR variant, the Link Training (LT) and Auto Negotiation (AN) tabs appear. The 1Gb/10Gb Ethernet variant (1G/10GbE) does not implement LT and AN parameters.

Complete the following steps to configure the 10GBASE-KR PHY IP Core:

Under Tools > IP Catalog, select the device family of your choice.
Under Tools > IP Catalog > Interface Protocols > Ethernet, select 10GBASE-KR PHY.
Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
Specify 10GBASE-KR parameters. Refer to the topics listed as Related Links to understand 10GBASE-KR parameters.
Click Finish to generate your parameterized 10GBASE-KR PHY IP Core.

10GBASE-KR Link Training Parameters

The 10GBASE-KR variant provides parameters to customize the Link Training parameters.

Table 25. Link Training Settings
Name	Value	Description
Enable Link Training	On/Off	When you turn this option On, the core includes the link training module which configures the remote link-partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
Enable daisy chain mode	On/Off	When you turn this option On, the core includes support for non-standard link configurations where the TX and RX interfaces connect to different link partners. This mode overrides the TX adaptation algorithm.
Enable microprocessor interface	On/Off	When you turn this option On, the core includes a microprocessor interface which enables the microprocessor mode for link training.
Maximum bit error count	15, 31,63, 127, 255	Specifies the maximum number of errors before the Link Training Error bit (0xD2, bit 4) is set indicating an unacceptable bit error rate. You can use this parameter to tune PMA settings. For example, if you see no difference in error rates between two different sets of PMA settings, you can increase the width of the bit error counter to determine if a larger counter enables you to distinguish between PMA settings.
Number of frames to send before sending actual data	127, 255	Specifies the number of additional training frames the local link partner delivers to ensure that the link partner can correctly detect the local receiver state.
PMA Parameters
VMAXRULE	`0-63`	Specifies the maximum V_OD. The default value is 60 which represents 1200 mV.
VMINRULE	`0-63`	Specifies the minimum V_OD. The default value is 9 which represents 165 mV.
VODMINRULE	`0-63`	Specifies the minimum V_ODfor the first tap. The default value is 24 which represents 440mV.
VPOSTRULE	`0-31`	Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting. The default value is 31.
VPRERULE	`0-15`	Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting. The default value is 15.
PREMAINVAL	`0-63`	Specifies the Preset V_OD Value. Set by the Preset command as defined in Clause 72.6.10.2.3.1 of the link training protocol. This is the value from which the algorithm starts. The default value is 60.
PREPOSTVAL	`0-31`	Specifies the preset Pre-tap Value. The default value is 0.
PREPREVAL	`0-15`	Specifies the preset Post-tap value. The default value is 0.
INITMAINVAL	`0-63`	Specifies the Initial VOD Value. Set by the Initialize command in Clause 72.6.10.2.3.2 of the link training protocol. The default value is 52.
INITPOSTVAL	`0-31`	Specifies the initial first Post-tap value. The default value is 30.
INITPREVAL	`0-15`	Specifies the Initial Pre-tap Value. The default value is 5.

10GBASE-KR Auto-Negotiation and Link Training Parameters

Table 26. Auto Negotiation and Link Training Settings
Name	Range	Description
Enable Auto-Negotiation	On Off	Enables or disables the Auto-Negotiation feature.
Pause ability-C0	On Off	Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word. C0 is the same as PAUSE.
Pause ability-C1	On Off	Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word. C1 is the same as ASM_DIR.
Enable Link Training	On Off	Enables or disables the Link Training feature.
Maximum bit error count	15, 31, 63, 127, 255, 511, 1023	Specifies the number of bit errors for the error counter expected during each step of the link training. If the number of errors exceeds this number for each step, the core returns an error. The number of errors depends upon the amount of time for each step and the quality of the physical link media. The default value is 511.
Number of frames to send before sending actual data	127, 255	This timer is started when the local receiver is trained and detects that the remote receiver is ready to receive data. The local physical medium dependent (PMD) layer delivers `wait_timer` additional training frames to ensure that the link partner correctly detects the local receiver state. The default value is 127.

10GBASE-R Parameters

The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC options allow you to specify the FEC ability.

Table 27. 10GBASE-R Parameters
Parameter Name	Options	Description
Enable IEEE 1588 Precision Time Protocol	On/Off	When you turn this option On, the core includes logic to implement the IEEE 1588 Precision Time Protocol.
Reference clock frequency	644.53125MHz 322.265625MHz	Specifies the input reference clock frequency. The default is 322.265625MHz.
PLL Type	ATX CMU	Specifies the PLL type. You can specify either a CMU or ATX PLL. The ATX PLL has better jitter performance at higher data rates than the CMU PLL. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.
Enable additional control and status pins	On/Off	When you turn this option On, the core includes the `rx_block_lock` and `rx_hi_ber` ports.
Enable rx_recovered_clk pin	On/Off	When you turn this option On, the core includes the `rx_recovered_clk` port.
Enable pll_locked status port	On/Off	When you turn this option On, the core includes the `pll_locked` port.

Table 28. FEC Options
Parameter Name	Options	Description
Include FEC sublayer	On/Off	When you turn this option On, the core includes logic to implement FEC and a soft 10GBASE-R PCS.
Set `FEC_ability` bit on power up and reset	On/Off	When you turn this option On, the core sets the FEC ability bit on power up and reset.
Set `FEC_Enable` bit on power up and reset	On/Off	When you turn this option On, the core sets the FEC enable bit on power up and reset.
Set `FEC_Error_Indication_ability` bit on power up and reset	On/Off	When you turn this option On, the core indicates errors to the PCS.
Good parity counter threshold to achieve FEC block lock	Default value: 4	Specifies the number of good parity blocks the RX FEC module must receive before indicating block lock as per Clause 74.10.2.1 of IEEE 802.3ap-2007.
Invalid parity counter threshold to lose FEC block lock	Default value: 8	Specifies the number of bad parity blocks the RX FEC module must receive before indicating loss of block lock as per Clause 74.10.2.1 of IEEE 802.3ap-2007.
Use M20K for FEC Buffer (if available)	On/Off	When you turn this option On, the Quartus^® Prime software saves resources by replacing the FEC buffer with M20K memory.

10GBASE-KR PHY IP Core Functional Description

This topic provides high-level block diagram of the 10GBASE-KR hardware.

The following figure shows the 10GBASE‑KR PHY IP Core and the supporting modules required for integration into your system. In this figure, the colors have the following meanings:

Green-Altera- Cores available Quartus^® Prime IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller.
Orange-Arbitration Logic Requirements. Logic you must design, including the Arbiter and State Machine. Refer to 10GBASE-KR PHY Arbitration Logic Requirements and 10GBASE-KR PHY State Machine Logic Requirements for a description of this logic.
White - 1G,10G and AN/LT settings files that you must generate. Refer to Creating a 10GBASE-KR Design for more information.
Blue-The 10GBASE-KR PHY IP core available in the Quartus^® Prime IP Library.

Figure 17. Detailed 10GBASE-KR PHY IP Core Block Diagram

As this figure illustrates, the 10GBASE-KR PHY is built on the Native PHY and includes the following additional blocks implemented in soft logic to implement Ethernet functionality defined in Clause 72 of IEEE 802.3ap-2007.

Link Training (LT), Clause 72

This module performs link training as defined in Clause 72. The module facilitates two features:

Daisy‑chain mode for non-standard link configurations where the TX and RX interfaces connect to different link partners instead of in a spoke and hub or switch topology.

An embedded processor mode to override the state‑machine‑based training algorithm. This mode allows an embedded processor to establish link data rates instead of establishing the link using the state‑machine‑based training algorithm.

The following figure illustrates the link training process, where the link partners exchange equalization data.

Figure 18. TX Equalization for Link Partners

TX equalization includes the following steps which are identified in this figure.

The receiving link partner calculates the BER.
The receiving link partner transmits an update to the transmitting link partner TX equalization parameters to optimize the TX equalization settings
The transmitting partner updates its TX equalization settings.
The transmitting partner acknowledges the change.

This process is performed first for the V_OD, then the pre-emphasis, the first post‑tap, and then pre-emphasis pre-tap.

The optional backplane daisy-chain topology can replace the spoke or hub switch topology. The following illustration highlights the steps required for TX Equalization for Daisy Chain Mode.

Figure 19. TX Equalization in Daisy-Chain Mode

Data transmission proceeds clockwise from link partner A, to B, to C. TX equalization includes the following steps which are identified in the figure :

The receiving partner B calculates the BER for data received from transmitting partner A.
The receiving partner B sends updates for TX link partner C.
The receiving link partner C transmits an update to the transmitting link partner A.
Transmit partner A updates its equalization settings.
Transmit partner A acknowledges the change.

This procedure is repeated for the other two link partners.

Sequencer

The Sequencer (Rate change) block controls the start-up (reset, power-on) sequence of the PHY IP. It automatically selects which PCS (1G, 10GbE, or Low Latency) is required and sends requests to reconfigure the PCS. The Sequencer also performs the parallel detection function that reconfigures between the 1G and 10GbE PCS until the link is established or times out.

Auto Negotiation (AN), Clause 73

The Auto Negotiation module in the 10GBASE-KR PHY IP implements Clause 73 of the Ethernet standard. This module currently supports auto negotiation between 1GbE and 10GBASE-R data rates. Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto negotiation module is reset.

The following figures illustrate the handshaking between the Auto Negotiation, Link Training, Sequencer and Transceiver Reconfiguration Controller blocks. Reconfig controller should use lt_start_rc signal in combination with main_rc, post_rc, pre_rc, and tap_to_upd to change TX equalization settings.

Figure 20. Transition from Auto Negotiation to Link Training Mode

The Transceiver Reconfiguration Controller uses seq_start_rc in combination with the pcs_mode_rc value to initiate a change to Auto Negotiation mode or from Link Training mode to 10GBASE-KR Data mode. After TX equalization completes, this timing diagram shows the transition from Link Training mode to 10GBASE-KR Data mode and MIF streaming.

Figure 21. Transition from Link Training to Data Mode

10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE

This topic illustrates the necessary logic to reconfigure between the 1G and 10G data rates.

The following figure illustrates the necessary modules to create a design that can dynamically change between 1G and 10GbE operation on a channel‑by‑channel basis.

In this figure, the colors have the following meanings:

Green-Altera- Cores available Quartus^® Prime IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller.
Arbitration Logic Requirements Orange-Logic you must design, including the Arbiter and State Machine. Refer to 10GBASE-KR PHY Arbitration Logic Requirements and 10GBASE-KR PHY State Machine Logic Requirements for a description of this logic.
White-1G and 10G settings files that you must generate. Refer to Creating a 10GBASE-KR Design for more information.
Blue-The 10GBASE-KR PHY IP core available in the Quartus^® Prime IP Library.

Figure 22. Block Diagram for Reconfiguration Example

10GBASE-KR PHY Arbitration Logic Requirements

This topic describes the arbitration functionality that you must implement.

The arbiter should implement the following logic. You can modify this logic based on your system requirements:

Accept requests from either the Sequencer or Link Training block. Prioritize requests to meet system requirements. Requests should consist of the following two buses:
- Channel number—specifies the requested channel
- Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel
Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received.
Pass the selected channel and rate information or PMA reconfiguration information for LT to the state machine for processing.
Wait for a done signal from the state machine indicating that the reconfiguration process is complete and it is ready to service another request.

10GBASE-KR PHY State Machine Logic Requirements

The state machine should implement the following logic. You can modify this logic based on your system requirements:

Wait forreconfig_busy from the Transceiver Reconfiguration Controller to be deasserted and the tx_ready and rx_ready signals from the Transceiver PHY Reset Controller to be asserted. These conditions indicate that the system is ready to service a reconfiguration request.
Set the appropriate channel for reconfiguration.
Initiate the MIF streaming process. The state machine should also select the appropriate MIF (stored in the ROMs) to stream based on the requested mode.
Wait for thereconfig_busy signal from the Transceiver Reconfiguration Controller to assert and then deassert indicating the reconfiguration process is complete.
Toggle the digital resets for the reconfigured channel and wait for the link to be ready.
Deassert the ack/busy signal for the selected channel. Deassertion of ack/busy indicates to the arbiter that the reconfiguration process is complete and the system is ready to service another request.

Forward Error Correction (Clause 74)

The optional Forward Error Correction (FEC) function is defined in Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism allowing noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10^-12 .

The following figure illustrates the interface between the FEC, PCS and PMA modules as defined in IEEE802.3ap-2007.

Figure 23. FEC Functional Block Diagram

The FEC capability is encoded in the FEC Ability and FEC Requested bits of the baseLink Codeword. It is transmitted within a Differential Manchester Encoded page during Auto Negotiation. The link enables the FEC function if the link partners meet the following conditions:

Both partners advertise the FEC Ability
At least one partner requests FEC

Note: If neither device requests FEC, FEC is not enabled even if both devices have the FEC Ability.

The TX FEC encoder (2112, 2080) creates 2112-bit FEC blocks or codewords from 32, 64B/66B encoded and scrambled 10GBASE-R words. It compresses the 32, 66-bit words into 32, 65-bit words and generates 32-bit parity using the following polynomial:

g(x) = x³² +  x²³ + x²¹ + x¹¹ + x² + 1

Parity is appended to the encoded data. The receiving device can use parity to detect and correct burst errors of up to 11 bits. The FEC encoder preserves the standard 10GBASE-KR line rate of 10.3125 Gbps by compressing the 32 sync bits from 64B/66B words. The TX FEC module is clocked at 161.1 MHz.

Figure 24. FEC Codeword Format

Error detection and correction consists of calculating the syndrome of the received codeword. The syndrome is the remainder from the polynomial division of the received codeword by g(x). If the syndrome is zero, the codeword is correct. If the syndrome is non-zero, you can use it to determine the most likely error.

Figure 25. Codewords, Parity and Syndromes

TX FEC Module Scrambler

In addition to the TX FEC encoder, the TX FEC module includes the following functions:

FEC Scrambler: The FEC scrambler scrambles the encoded output. The polynomial used to scramble the encoded output ensures DC balance to facilitate block synchronization at the receiver. It is shown below.
```
X = x⁵⁸+ X ³⁹ + 1
```
FEC Gearbox: The FEC gearbox adapts the FEC data width to the smaller bus width of the interface to the PCS. It supports a special 65:64 gearbox ratio.

RX FEC Module

The RX FEC module is clocked at 161.1 MHz. It includes the following functions:

FEC Block Synchronizer: The FEC block synchronizer achieves FEC block delineation by locking to correctly received FEC blocks. An algorithm with hysteresis maintains block and word delineation.
FEC Descrambler: The FEC descrambler descrambles the received data to regenerate unscrambled data utilizing the original FEC scrambler polynomial.
FEC Decoder:The FEC decoder performs the (2112, 2080) decoding by analyzing the received FEC block for errors. It can correct burst errors of 11 bits per FEC block. The FEC receive gearbox adapts the data width to the larger bus width of the PCS channel. It supports a 64:65 ratio.
FEC Transcode Decoder: The FEC transcode decoder performs 65-bit to 64B/66B reconstruction by regenerating the 64B/66B sync header.

10BASE-KR PHY Interfaces

Figure 26. 10GBASE-KR Top-Level Signals

The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn on Show signals, the block diagram displays all top-level signal names. For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus^® Prime Handbook

10GBASE-KR PHY Clock and Reset Interfaces

This topic provides a block diagram of the 10GBASE-KR clock and reset connectivity and describes the clock and reset signals.

Use the Transceiver PHY Reset Controller IP Core to automatically control the transceiver reset sequence. This reset controller also has manual overrides for the TX and RX analog and digital circuits to allow you to reset individual channels upon reconfiguration.

If you instantiate multiple channels within a transceiver bank they share TX PLLs. If a reset is applied to this PLL, it will affect all channels. Altera recommends leaving the TX PLL free-running after the start-up reset sequence is completed. After a channel is reconfigured you can simply reset the digital portions of that specific channel instead of going through the entire reset sequence. If you are not using the sequencer and the data link is lost, you must assert the rx_digitalreset when the link recovers. For more information about reset, refer to the "Transceiver PHY Reset Controller IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.

The following figure provides an overview of the clocking for this core.

Figure 27. Clocks for Standard and 10G PCS and TX PLLs

The following table describes the clock and reset signals. The frequencies of the XGMII clocks increases to 257.8125 MHz when you enable 1588.

Table 31. Clock and Reset Signals
Signal Name	Direction	Description
`rx_recovered_clk`	Output	The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 257.8125 MHz.
`tx_clkout_1g`	Output	GMII TX clock for the 1G TX parallel data source interface. The frequency is 125 MHz.
`rx_clkout_1g`	Output	GMII RX clock for the 1G RX parallel data source interface. The frequency is 125 MHz.
`rx_coreclkin_1g`	Input	Clock to drive the read side of the RX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.
`tx_coreclkin_1g`	Input	Clock to drive the write side of the TX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.
`pll_ref_clk_1g`	Input	Reference clock for the PMA block for the 1G mode. Its frequency is 125 or 62.5 MHz.
`pll_ref_clk_10g`	Input	Reference clock for the PMA block in 10G mode. Its frequency is 644.53125 or 322.265625 MHz.
`pll_powerdown_1g`	Input	Resets the 1Gb TX PLLs.
`pll_powerdown_10g`	Input	Resets the 10Gb TX PLLs.
`tx_analogreset`	Input	Resets the analog TX portion of the transceiver PHY.
`tx_digitalreset`	Input	Resets the digital TX portion of the transceiver PHY.
`rx_analogreset`	Input	Resets the analog RX portion of the transceiver PHY.
`rx_digitalreset`	Input	Resets the digital RX portion of the transceiver PHY.
`usr_an_lt_reset`	Input	Resets only the AN and LT logic. This signal is only available for the 10GBASE‑KR variants.
`usr_seq_reset`	Input	Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled.
`usr_fec_reset`	Input	When asserted, resets the 10GBASE-KR FEC module.
`usr_soft_10g_pcs_reset`	Input	When asserted, resets the 10G PCS associated with the FEC module.

10GBASE-KR PHY Data Interfaces

The following table describes the signals in the XGMII and GMII interfaces. The MAC drives the TX XGMII and GMII signals to the 10GBASE-KR PHY. The 10GBASE-KR PHY drives the RX XGMII or GMII signals to the MAC.

Table 32. XGMII and GMII Signals
Signal Name	Direction	Description
10GBASE-KR XGMII Data Interface
`xgmii_tx_dc[71:0]`	Input	XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
`xgmii_tx_clk`	Input	Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to `xgmii_rx_clk` . The frequency is 156.25 MHz irrespective of 1588 being enabled or disabled. Driven from the MAC. This clock is derived from the transceiver reference clock (`pll_ref_clk_10g`).
`xgmii_rx_dc[71:0]`	Output	RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
`xgmii_rx_clk`	Input	Clock for SDR XGMII RX interface to the MAC. The frequency is 156.25 MHz irrespective of 1588 being enabled or disabled. Driven from the MAC. This clock is derived from the transceiver reference clock (`pll_ref_clk_10g`).
10GBASE-KR GMII Data Interface
`gmii_tx_d[7:0]`	Input	TX data for 1G mode. Synchronized to `tx_clkout_1g` clock. The TX PCS 8B/10B module encodes this data which is sent to link partner.
`gmii_rx_d[7:0]`	Output	RX data for 1G mode. Synchronized to `rx_clkout_1g` clock. The RX PCS 8B/10B decoders decodes this data and sends it to the MAC.
`gmii_tx_en`	Input	When asserted, indicates the start of a new frame. It should remain asserted until the last byte of data on the frame is present on `gmii_tx_d` .
`gmii_tx_err`	Input	When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame.
`gmii_rx_err`	Output	When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame.
`gmii_rx_dv`	Output	When asserted, indicates the start of a new frame. It remains asserted until the last byte of data on the frame is present on `gmii_rx_d` .
`led_char_err`	Output	10-bit character error. Asserted for one `rx_clkout_1g` cycle when an erroneous 10-bit character is detected
`led_link`	Output	When asserted, indicates successful link synchronization.
`led_disp_err`	Output	Disparity error signal indicating a 10-bit running disparity error. Asserted for one `rx_clkout_1g` cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.
`led_an`	Output	Clause 37 Auto-Negotiation status. The PCS function asserts this signal when Auto‑Negotiation completes.

10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data

The 72‑bit TX XGMII data bus format is different than the standard SDR XGMII interface. The following table lists the mapping of this non‑standard format to the standard SDR XGMII interface.

Table 33. TX XGMII Mapping to Standard SDR XGMII Interface
Signal Name	SDR XGMII Signal Name	Description
`xgmii_tx_dc[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_tx_dc[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_tx_dc[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_tx_dc[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_tx_dc[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_tx_dc[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_tx_dc[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_tx_dc[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_tx_dc[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_tx_dc[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_tx_dc[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_tx_dc[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_tx_dc[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_tx_dc[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_tx_dc[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_tx_dc[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

The 72‑bit RX XGMII data bus format is different from the standard SDR XGMII interface. The following table lists the mapping of this non‑standard format to the standard SDR XGMII interface:

Table 34. RX XGMII Mapping to Standard SDR XGMII Interface
Signal Name	XGMII Signal Name	Description
`xgmii_rx_dc[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_rx_dc[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_rx_dc[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_rx_dc[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_rx_dc[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_rx_dc[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_rx_dc[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_rx_dc[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_rx_dc[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_rx_dc[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_rx_dc[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_rx_dc[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_rx_dc[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_rx_dc[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_rx_dc[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_rx_dc[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

10GBASE-KR PHY Serial Data Interface

This topic describes the serial data interface.

Signal Name	Direction	Description
`rx_serial_data`	Input	RX serial input data
`tx_serial_data`	Output	TX serial output data

10GBASE-KR PHY Control and Status Interfaces

The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.

Table 36. Control and Status Signals
Signal Name	Direction	Description
`rx_block_lock`	Output	Asserted to indicate that the block synchronizer has established synchronization.
`rx_hi_ber`	Output	Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10^-4.
`pll_locked`	Output	When asserted, indicates the TX PLL is locked.
`rx_is_lockedtodata`	Output	When asserted, indicates the RX channel is locked to input data.
`tx_cal_busy`	Output	When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes.
`rx_cal_busy`	Output	When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
`calc_clk_1g`	Input	An independent clock to calculate the latency of the SGMII TX and RX FIFOs. It is only required for when you enable 1588 in 1G mode. The `calc_clk_1g` should have a frequency that is not equivalent to 8 ns (125MHz). The accuracy of the PCS latency measurement is limited by the greatest common denominator (GCD) of the RX and TX clock periods (8 ns) and `calc_clk_1g`. The GCD is 1 ns, if no other higher common factor exists. When the GCD is 1, the accuracy of the measurement is 1 ns. If the period relationship has too small a phase, the phase measurement requires more time than is available. Theoretically, 8.001 ns would provide 1 ps of accuracy. But this phase measurement period requires 1000 cycles to converge which is beyond the averaging capability of the design. The GCD of the clock periods should be no less than 1/64 ns (15ps). To achieve high accuracy for all speed modes, the recommended frequency for `calc_clk_1g` is 80 MHz. In addition, the 80 MHz clock should have same parts per million (ppm) as the 125 MHz `pll_ref_clk_1g` input. The random error without a rate match FIFO mode is: +/- 1 ns at 1000 Mbps +/- 5 ns at 100 Mbps +/- 25 ns at 10 Mbps
`rx_sync_status`	Output	When asserted, indicates the Standard PCS word aligner has aligned to in incoming word alignment pattern.
`tx_pcfifo_error_1g`	Output	When asserted, indicates that the Standard PCS TX phase compensation FIFO is either full or empty.
`rx_pcfifo_error_1g`	Output	When asserted, indicates that the Standard PCS RX phase compensation FIFO is either full or empty.
`lcl_rf`	Input	When asserted, indicates a Remote Fault (RF).The MAC to sends this fault signal to its link partner. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. Bit 3 of the `Auto Negotiation Advanced Remote Fault`register (0xC2) records this error.
`tm_in_trigger[3:0]`	Input	This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. If unused, tie this signal to 1'b0.
`tm_out_trigger[3:0]`	Output	This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. You can ignore this signal if not used.
`rx_rlv`	Output	When asserted, indicates a run length violation.
`rx_clkslip`	Input	When you turn this signal on, the deserializer skips one serial bit or the serial clock is paused for one cycle to achieve word alignment. As a result, the period of the parallel clock can be extended by 1 unit interval (UI). This is an optional control input signal.
`rx_latency_adj_1g[21:0]`	Output	When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
`tx_latency_adj_1g[21:0]`	Output	When you enable 1588, this signal outputs real time latency in GMII clock cycles (125 MHz) for the TX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
`rx_latency_adj_10g[15:0]`	Output	When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
`tx_latency_adj_10g[15:0]`	Output	When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.25 MHz) for the TX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
`rx_data_ready`	Output	When asserted, indicates that the MAC can begin sending data to the 10GBASE-KR PHY IP Core.
`tx_frame`	Output	Asynchronous status flag output of the TX FEC module. When asserted, indicates the beginning of the generated 2112-bit FEC frame.
`rx_clr_counters`	Input	When asserted, resets the status counters in the RX FEC module. This is an asynchronous input.
`rx_frame`	Output	Asynchronous status flag output of the RX FEC module. When asserted, indicates the beginning of a 2112-bit received FEC frame.
`rx_block_lock`	Output	Asynchronous status flag output of the RX FEC module. When asserted, indicates successful FEC block lock.
`rx_parity_good`	Output	Asynchronous status flag output of the RX FEC module. When asserted, indicates that the parity calculation is good for the current received FEC frame. Used in conjunction with the `rx_frame` signal.
`rx_parity_invalid`	Output	Asynchronous status flag output of the RX FEC module. When asserted, indicates that the parity calculation is not good for the current received FEC frame. Used in conjunction with the `rx_frame` signal.
`rx_error_corrected`	Output	Asynchronous status flag output of the RX FEC module. When asserted, indicates that an error was found and corrected in the current received FEC frame. Used in conjunction with the `rx_frame` signal.

Daisy-Chain Interface Signals

The optional daisy-chain interface signals connect link partners using a daisy-chain topology.

Table 37. Daisy Chain Interface Signals
Signal Name	Direction	Description
`dmi_mode_en`	Input	When asserted, enable Daisy Chain mode.
`dmi_frame_lock`	Input	When asserted, the daisy chain state machine has locked to the training frames.
`dmi_rmt_rx_ready`	Input	Corresponds to bit 15 of Status report field. When asserted, the remote receiver.
`dmi_lcl_coefl[5:0]`	Input	Local update low bits[5:0]. In daisy-chained configurations, the local update coefficients substitute for the coefficients that would be set using Link Training.
`dmi_lcl_coefh[1:0]`	Input	Local update high bits[13:12]. In daisy-chained configurations, the local update coefficients substitute for the coefficients that would be set using Link Training.
`dmi_lcl_upd_new`	Input	When asserted, indicates a local update has occurred.
`dmi_rx_trained`	Input	When asserted, indicates that the state machine has finished local training.
`dmo_frame_lock`	Output	When asserted, indicates that the state machine has locked to the training frames.
`dmo_rmt_rx_ready`	Output	Corresponds to the link partner's remote receiver ready bit.
`dmo_lcl_coefl[5:0]`	Output	Local update low bits[5:0]. In daisy-chained configurations, the local update coefficients substitute for the coefficients that would be set using Link Training.
`dmo_lcl_coefh[1:0]`	Output	Local update high bits[13:12]. In daisy-chained configurations, the local update coefficients substitute for the coefficients that would be set using Link Training.
`dmo_lcl_upd_new`	Output	When asserted, indicates a local update has occurred.
`dmo_rx_trained`	Output	When asserted, indicates that the state machine has finished local training.

Embedded Processor Interface Signals

The optional embedded processor interface signals allow you to use the embedded processor mode of Link Training. This mode overrides the TX adaptation algorithm and allows an embedded processor to initialize the link.

Table 38. Embedded Processor Interface Signals
Signal Name	Direction	Description
`upi_mode_en`	Input	When asserted, enables embedded processor mode.
`upi_adj[1:0]`	Input	Selects the active tap. The following encodings are defined: 2'b01: Main tap 2'b10: Post‑tap 2'b11: Pre‑tap
`upi_inc`	Input	When asserted, sends the increment command.
`upi_dec`	Input	When asserted, sends the decrement command.
`upi_pre`	Input	When asserted, sends the preset command.
`upi_init`	Input	When asserted, sends the initialize command.
`upi_st_bert`	Input	When asserted, starts the BER timer.
`upi_train_err`	Input	When asserted, indicates a training error.
`upi_rx_trained`	Input	When asserted, the local RX interface is trained.
`upo_enable`	Output	When asserted, indicates that the 10GBASE‑KR PHY IP Core is ready to receive commands from the embedded processor.
`upo_frame_lock`	Output	When asserted, indicates the receiver has achieved training frame lock.
`upo_cm_done`	Output	When asserted, indicates the master state machine handshake is complete.
`upo_bert_done`	Output	When asserted, indicates the BER timer is at its maximum count.
`upo_ber_cnt` `[ <w>-1:0]`	Output	Records the BER count.
`upo_ber_max`	Output	When asserted, the BER counter has rolled over.
`upo_coef_max`	Output	When asserted, indicates that the remote coefficients are at their maximum or minimum values.

10GBASE-KR PHY Register Definitions

Creating a 10GBASE-KR Design

Here are the steps you must take to create a 10GBASE-KR design using this PHY.

Generate the 10GBASE-KR PHY with the required parameterization.
Generate a Transceiver Reconfiguration Controller with the correct number of reconfiguration interfaces based on the number of channels you are using. This controller is connected to all the transceiver channels. It implements the reconfiguration process.
Generate a Transceiver Reset Controller.
Create arbitration logic that prioritizes simultaneous reconfiguration requests from multiple channels. This logic should also acknowledge the channel being serviced causing the requestor to deassert its request signal.
Create a state machine that controls the reconfiguration process. The state machine should:
1. Receive the prioritized reconfiguration request from the arbiter
2. Put the Transceiver Reconfiguration Controller into MIF streaming mode.
3. Select the correct MIF and stream it into the appropriate channel.
4. Wait for the reconfiguration process to end and provide status signal to arbiter.
Generate one ROM for each required configuration.
Create a MIF for each configuration and associate each MIF with a ROM created in Step 6. For example, create a MIF for 1G with 1588 , a MIF for 10G with 1588, and a MIF for AN/LT. AN/LT MIF is is used to reconfigure the PHY into low latency mode during AN/LT. These MIFs are the three configurations used in the MIF streaming process. The example design contains five required MIFs (1G, 10G, 1G with 1588,10G with 1588 and AN/LT). Altera recommends that you use these MIFs even if you are not using the example design.
Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
Instantiate the PHY in your design based on the required number of channels.
To complete the system, connect all the blocks.

Editing a 10GBASE-KR MIF File

This topic shows how to edit a 10GBASE-KR MIF file to change between 1G and 10Gb Ethernet.

The MIF format contains all bit settings for the transceiver PMA and PCS. Because the 10GBASE-KR PHY IP Core only requires PCS reconfiguration for a rate change, the PMA settings should not change. Removing the PMA settings from the MIF file also prevents an unintended overwrite of PMA parameters set through other assignments. A few simple edits to the MIF file removes the PMA settings. Complete the following steps to to remove PMA settings from the MIF file:

Replace line 17 with "13: 0001000000010110; -- PMA - RX changed to removed CTLE".
Replace line 20 with"16: 0010100000011001; -- PMA - RX continued".
Replace line 4 with "4: 0001000000000000; -- PMA - TX".
Remove lines 7-10. These lines contain the TX settings (V_OD, post-tap, pre-tap).
Renumber the lines starting with the old line 11.
Change the depth at the top of the file from 168 to 164.

Edits to a MIF to Remove PMA Settings

1G/10Gbps Ethernet PHY IP Core

The 1G/10 Gbps Ethernet PHY MegaCore® (1G/10GbE) function allows you to instantiate both the Standard PCS and the higher performance 10G PCS and a PMA. The Standard PCS implements the 1 GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto‑negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard standard. The 10G PCS implements the 10 Gb Ethernet protocol as defined in IEEE 802.3 2005 Standard.

You can switch dynamically between the 1G and 10G PCS using the Altera Transceiver Reconfiguration Controller IP Core to reprogram the core. This Ethernet core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE‑T copper external PHY devices to drive CAT‑6/7 shielded twisted pair cables, and chip‑to‑chip interfaces.

The following figure shows the top‑level modules of the 1G/10GbE PHY IP Core. As this figure indicates, the 1G/10 Gbps Ethernet PHY connects to a separately instantiated MAC. The 10G PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data. An Avalon Memory‑Mapped (Avalon‑MM) slave interface provides access to PCS registers. the PMA receives and transmits serial data.

Figure 29. Level Modules of the 1G/10GbE PHY MegaCore Function

An Avalon^® Memory‑Mapped (Avalon‑MM) slave interface provides access to the 1G/10GbE PHY IP Core registers. These registers control many of the functions of the other blocks. Many of these bits are defined in Clause 45 of IEEE Std 802.3ap‑2007.

1G/10GbE PHY Release Information

This topic provides information about this release of the 1G/10GbE PHY IP Core.

Table 47. 1G/10GbE Release Information
Item	Description
Version	13.1
Release Date	November 2013
Ordering Codes	IP-1G10GBASER PHY (primary)
Product ID	0106
Vendor ID	6AF7

Device Family Support

IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions:

Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.

Table 23. Table 48. Device Family Support
Device Family	Support	Supported Speed Grades
Arria V GZ devices–Hard PCS and PMA	Final	I3L, C3, I4, C4
Stratix V devices–Hard PCS and PMA	Final	All speed grades except I4 and C4
Other device families	No support

Altera verifies that the current version of the Quartus^® Prime software compiles the previous version of each IP core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with IP core versions older than the previous release.

Note: For speed grade information, refer to DC and Switching Characteristics for Stratix V Devices in the Stratix V Device Datasheet.

1G/10GbE PHY Performance and Resource Utilization

This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V devices.

The following table shows the typical expected resource utilization for selected configurations using the current version of the Quartus^® Prime software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v12.1 release 28 nm device families and upcoming device families.

Table 49. 1G/10 GbE PHY Performance and Resource Utilization
PHY Module Options	ALMs	M20K Memory	Logic Registers
1GbE/10GbE - 1GbE only	300	0	600
1GbE/10GbE - 1GbE only with Sequencer	400	0	700
1GbE/10GbE - 1GbE/10GbE with 1588	1000	4	2000
1GbE/10GbE - 1GbE/10GbE with 1588 and Sequencer	1100	4	2000

Parameterizing the 1G/10GbE PHY

The 1G/10GbE PHY IP Core is available for the Arria V GZ and Stratix V device families. The IP variant allows you specify either the Backplane-KR or 1Gb/10Gb Ethernet variant. When you select the Backplane-KR variant, the Link Training (LT) and Auto Negotiation (AN) tabs appear. The 1Gb/10Gb Ethernet variant (1G/10GbE) does not implement LT and AN parameters.

Complete the following steps to configure the 1G/10GbE PHY IP Core in the MegaWizard Plug-In Manager:

Under Tools > IP Catalog, select the device family of your choice.
Under Tools > IP Catalog > Interfaces > Ethernet select 1G10GbE and 10GBASE-KR PHY.
Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
Refer to the topics listed as Related Links to understand and specify 1G/10GbE parameters:
Click Finish to generate your parameterized 1G/10GbE PHY IP Core.

1GbE Parameters

The 1GbE parameters allow you to specify options for the 1GbE mode.

Table 50. 1Gb Ethernet Parameters
Parameter Name	Options	Description
Enable 1Gb Ethernet protocol	On/Off	When you turn this option On, the core includes the GMII interface and related logic.
Expose MII interface	On/Off	When you turn this option On, the core exposes the MII interface and related logic.
Enable IEEE 1588 Precision Time Protocol	On/Off	When you turn this option On, the core includes a module in the PCS to implement the IEEE 1588 Precision Time Protocol.
PHY ID (32 bit)	`32-bit value`	An optional 32-bit value that serves as a unique identifier for a particular type of PCS. The identifier includes the following components: Bits 3-24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE 6‑bit model number 4-bit revision number If unused, do not change the default value which is 0x00000000.
PHY Core version (16 bits)	`16-bit value`	This is an optional 16‑bit value identifies the PHY core version.
Reference clock frequency	125.00 MHz 62.50 MHz	Specifies the clock frequency for the 1GBASE‑KR PHY IP Core. The default is 125 MHz.

Speed Detection Parameters

Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.

Table 30. Table 51. Speed Detection
Parameter Name	Options	Description
Enable automatic speed detection	On Off	When you turn this option On, the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able to detect AN data.
Avalon‑MM clock frequency	`100-162 MHz`	Specifies the clock frequency for `phy_mgmt_clk`.
Link fail inhibit time for 10Gb Ethernet	`504 ms`	Specifies the time before `link_status` is set to FAIL or OK. A link fails if the `link_fail_inhibit_time` has expired before `link_status` is set to OK. The legal range is 500-510 ms. For more information, refer to "Clause 73 Auto Negotiation for Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for 1Gb Ethernet	`40-50 ms`	Specifies the time before `link_status` is set to FAIL or OK . A link fails if the `link_fail_inhibit_time` has expired before `link_status` is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port	On Off	Enables or disables the PCS-Mode port.

PHY Analog Parameters

You can specify analog parameters using the Quartus^® Prime Assignment Editor, the Pin Planner, or the Quartus^® Prime Settings File (.qsf).

1G/10GbE PHY Interfaces

Figure 30. 1G/10GbE PHY Top-Level Signals

Note: Some of the signals shown in are this figure are unused and will be removed in a future release. The descriptions of these identifies them as not functional.

1G/10GbE PHY Clock and Reset Interfaces

This topic illustrates the 1G/10GbE PHY clock and reset connectivity and describes the clock and reset signals.

If you instantiate multiple channels within a transceiver bank they share TX PLLs. If a reset is applied to this PLL, it will affect all channels. Altera recommends leaving the TX PLL free-running after the start-up reset sequence is completed. After a channel is reconfigured you can simply reset the digital portions of that specific channel instead of going through the entire reset sequence. If you are not using the sequencer and the data link is lost, you must assert the rx_digitalreset when the link recovers. For more information about reset, refer to the "Transceiver PHY Reset IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.

Phy_mgmt_clk_reset is the Avalon-MM reset signal. Phy_mgmt_clk_reset is also an input to the Transceiver PHY Reset Controller IP Core which is a separately instantiated module not included in the 1G/10GbE and 10GBASE‑KR variants. The Transceiver PHY Reset Controller IP Core resets the TX PLL and RX analog circuits and the TX and RX digital circuits. When complete, the Reset Controller asserts the tx_ready and rx_ready signals.

The following figure provides an overview of the clocking for this IP core.

Figure 31. Clocks for Standard and 10G PCS and TX PLLs

The following table describes the clock and reset signals.

Table 52. Clock and Reset Signals
Signal Name	Direction	Description
`rx_recovered_clk`	Output	The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 156.25 MHz. For 10G PCS, its frequency is 257.8125 MHz.
`tx_clkout_1g`	Output	GMII TX clock for the 1G TX and RX parallel data source interface. The frequency is 125 MHz.
`rx_clkout_1g`	Output	GMII RX clock for the 1G RX parallel data source interface. The frequency is 125 MHz.
`rx_coreclkin_1g`	Input	Clock to drive the read side of the RX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.
`tx_coreclkin_1g`	Input	Clock to drive the write side of the TX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.
`pll_ref_clk_1g`	Input	Reference clock for the PMA block for the 1G mode. Its frequency is 125 or 62.5 MHz.
`pll_ref_clk_10g`	Input	Reference clock for the PMA block in 10G mode. Its frequency is 644.53125 or 322.265625 MHz.
`pll_powerdown_1g`	Input	Resets the 1Gb TX PLLs.
`pll_powerdown_10g`	Input	Resets the 10Gb TX PLLs.
`tx_analogreset`	Input	Resets the analog TX portion of the transceiver PHY.
`tx_digitalreset`	Input	Resets the digital TX portion of the transceiver PHY.
`rx_analogreset`	Input	Resets the analog RX portion of the transceiver PHY.
`rx_digitalreset`	Input	Resets the digital RX portion of the transceiver PHY.
`usr_seq_rest`	Input	Resets the sequencer.

1G/10GbE PHY Data Interfaces

The following table describes the signals in the XGMII and GMII interfaces. The MAC drives the TX XGMII and GMII signals to the 1G/10GbE PHY. The 1G/10GbE PHY drives the RX XGMII or GMII signals to the MAC.

Table 53. SGMII and GMII Signals

Signal Name

Direction

Description

1G/10GbE XGMII Data Interface

xgmii_tx_dc[71:0]

Input

XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.

xgmii_tx_clk

Input

Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to xgmii_rx_clk. The frequency is 156.25 MHz irrespective of 1588 being enabled or disabled. Driven from the MAC.

xgmii_rx_dc[71:0]

Output

RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.

xgmii_rx_clk

Input

Clock for SDR XGMII RX interface to the MAC. The frequency is 156.25 MHz irrespective of 1588 being enabled or disabled.

1G/10GbE GMII Data Interface

gmii_tx_d[7:0]

Input

TX data for 1G mode. Synchronized to tx_clkout_1g clock. The TX PCS 8B/10B module encodes this data which is sent to link partner.

gmii_rx_d[7:0]

Output

RX data for 1G mode. Synchronized to tx_clkout_1g clock. The RX PCS 8B/10B decoders decodes this data and sends it to the MAC.

gmii_tx_en

Input

When asserted, indicates the start of a new frame. It should remain asserted until the last byte of data on the frame is present on gmii_tx_d.

gmii_tx_err

Input

When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame.

gmii_rx_err

Output

When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame.

gmii_rx_dv

Output

When asserted, indicates the start of a new frame. It remains asserted until the last byte of data on the frame is present on gmii_rx_d.

led_char_err

Output

10-bit character error. Asserted for one rx_clkout_1g cycle when an erroneous 10-bit character is detected.

led_link

Output

When asserted, indicates successful link synchronization at 1Gb. This signal is not used at 10Gb

led_disp_err

Output

Disparity error signal indicating a 10-bit running disparity error. Asserted for one rx_clkout_1g cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.

led_an

Output

Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.

led_panel_link

Output

When asserted, this signal indicates the following behavior:

Mode	Signal Behavior
1000 Base-X without auto-negotiation	When asserted, indicates successful link synchronization.
1000 Base-X with auto-negotiation	Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
SGMII mode without auto-negotiation	When asserted, indicates successful link synchronization.
SGMII mode (MAC) auto-negotiation	Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes. Also refer to the description of `partner_ability [15]`.
SGMII mode (PHY) auto-negotiation	Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes. Also refer to the description of `dev_ability [15]`.

XGMII Mapping to Standard SDR XGMII Data

Table 54. TX XGMII Mapping to Standard SDR XGMII Interface. The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the mapping of this non‑standard format to the standard SDR XGMII interface.
Signal Name	SDR XGMII Signal Name	Description
`xgmii_tx_dc[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_tx_dc[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_tx_dc[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_tx_dc[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_tx_dc[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_tx_dc[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_tx_dc[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_tx_dc[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_tx_dc[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_tx_dc[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_tx_dc[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_tx_dc[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_tx_dc[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_tx_dc[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_tx_dc[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_tx_dc[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

Table 55. RX XGMII Mapping to Standard SDR XGMII Interface. The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name	XGMII Signal Name	Description
`xgmii_rx_dc[7:0]`	`xgmii_sdr_data[7:0]`	Lane 0 data
`xgmii_rx_dc[8]`	`xgmii_sdr_ctrl[0]`	Lane 0 control
`xgmii_rx_dc[16:9]`	`xgmii_sdr_data[15:8]`	Lane 1 data
`xgmii_rx_dc[17]`	`xgmii_sdr_ctrl[1]`	Lane 1 control
`xgmii_rx_dc[25:18]`	`xgmii_sdr_data[23:16]`	Lane 2 data
`xgmii_rx_dc[26]`	`xgmii_sdr_ctrl[2]`	Lane 2 control
`xgmii_rx_dc[34:27]`	`xgmii_sdr_data[31:24]`	Lane 3 data
`xgmii_rx_dc[35]`	`xgmii_sdr_ctrl[3]`	Lane 3 control
`xgmii_rx_dc[43:36]`	`xgmii_sdr_data[39:32]`	Lane 4 data
`xgmii_rx_dc[44]`	`xgmii_sdr_ctrl[4]`	Lane 4 control
`xgmii_rx_dc[52:45]`	`xgmii_sdr_data[47:40]`	Lane 5 data
`xgmii_rx_dc[53]`	`xgmii_sdr_ctrl[5]`	Lane 5 control
`xgmii_rx_dc[61:54]`	`xgmii_sdr_data[55:48]`	Lane 6 data
`xgmii_rx_dc[62]`	`xgmii_sdr_ctrl[6]`	Lane 6 control
`xgmii_rx_dc[70:63]`	`xgmii_sdr_data[63:56]`	Lane 7 data
`xgmii_rx_dc[71]`	`xgmii_sdr_ctrl[7]`	Lane 7 control

MII Interface Signals

The following signals are available when you turn on the Expose MII interface parameter.

Table 35. Table 56. MII Interface Signals
Signal Name	Direction	Description
`mii_tx_d[3:0]`	Input	TX data to be encoded and sent to link partner.
`mii_tx_en`	Input	MII transmit control signal.
`mii_tx_err`	Input	MII transmit error signal.
`mii_tx_clkena`	Output	Clock enabled signal from PHY to MAC. Following are the effective rates: For 100 Mbps: 25 MHz For 10 Mbps: 2.5 MHz
`mii_tx_clkena_half_rate`	Output	Clock enabled signal from PHY to MAC. Following are the effective rates: For 100 Mbps: 12.5 MHz For 10 Mbps: 1.25 MHz
`mii_rx_d[3:0]`	Output	RX data to be encoded and sent to link partner.
`mii_rx_dv`	Output	MII receive control signal.
`mii_rx_err`	Output	MII receive error signal.
`mii_rx_clkena`	Output	Clock enabled signal from PHY to MAC. Following are the effective rates: For 100 Mbps: 25 MHz For 10 Mbps: 2.5 MHz
`mii_rx_clkena_half_rate`	Output	Clock enabled signal from PHY to MAC. Following are the effective rates: For 100 Mbps: 12.5 MHz For 10 Mbps: 1.25 MHz
`mii_speed_sel[1:0]`	Output	This signal indicates the current speed of the PHY. 2’b00: 10 Gbps 2’b01: 1 Gbps 2’b10: 100 Mbps 2’b11: 10 Mbps

Serial Data Interface

Table 57. Serial Data Signals
Signal Name	Direction	Description
`rx_serial_data`	Input	RX serial input data
`tx_serial_data`	Output	TX serial output data

1G/10GbE Control and Status Interfaces

The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.

Table 58. Control and Status Signals
Signal Name	Direction	Description
`rx_block_lock`	Output	Asserted to indicate that the block synchronizer has established synchronization at 10G.
`rx_hi_ber`	Output	Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10^-4.
`pll_locked`	Output	When asserted, indicates the TX PLL is locked.
`rx_is_lockedtodata`	Output	When asserted, indicates the RX channel is locked to input data.
`tx_cal_busy`	Output	When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes.
`rx_cal_busy`	Output	When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
`calc_clk_1g`	Input	This clock is used for calculating the latency of the soft 1G PCS block. This clock is only required for when you enable 1588 in 1G mode.
`rx_sync_status`	Output	When asserted, indicates the word aligner has aligned to in incoming word alignment pattern.
`tx_pcfifo_error_1g`	Output	When asserted, indicates that the Standard PCS TX phase compensation FIFO is full.
`rx_pcfifo_error_1g`	Output	When asserted, indicates that the Standard PCS RX phase compensation FIFO is full.
`lcl_rf`	Input	When asserted, indicates a Remote Fault (RF).The MAC sends this fault signal to its link partner. Bit D13 of the `Auto Negotiation Advanced Remote Fault` register (0xC2) records this error.
`tm_in_trigger[3:0]`	Input	This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. If unused, tie this signal to 1'b0.
`tm_out_trigger[3:0]`	Output	This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. You can ignore this signal if not used.
`rx_rlv`	Output	When asserted, indicates a run length violation.
`rx_clkslip`	Input	When you turn this signal on, the deserializer skips one serial bit or the serial clock is paused for one cycle to achieve word alignment. As a result, the period of the parallel clock can be extended by 1 unit interval (UI). This is an optional control input signal.
`rx_latency_adj_1g[21:0]`	Output	When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent fractional number of clock cycles. Bits 10 to 21 represent number of clock cycles.
`tx_latency_adj_1g[21:0]`	Output	When you enable 1588, this signal outputs real time latency in GMII clock cycles (125 MHz) for the TX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent fractional number of clock cycles. Bits 10 to 21 represent number of clock cycles.
`rx_latency_adj_10g[15:0]`	Output	When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent fractional number of clock cycles. Bits 10 to 15 represent number of clock cycles.
`tx_latency_adj_10g[15:0]`	Output	When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.25 MHz) for the TX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent fractional number of clock cycles. Bits 10 to 15 represent number of clock cycles.
`rx_data_ready`	Output	When asserted, indicates that the MAC can begin sending data to the 10GBASE-KRPHY IP Core.

Register Interface Signals

The Avalon-MM master interface signals provide access to all registers.

Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Avalon Memory-Mapped Interfaces chapter of the Avalon Interface Specifications for timing diagrams.

Table 40. Table 59. Avalon-MM Interface Signals
Signal Name	Direction	Description
`mgmt_clk`	Input	The clock signal that controls the Avalon-MM PHY management, interface. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.
`mgmt_clk_reset`	Input	Resets the PHY management interface. This signal is active high and level sensitive.
`mgmt_addr[7:0]`	Input	8-bit Avalon-MM address.
`mgmt_writedata[31:0]`	Input	Input data.
`mgmt_readdata[31:0]`	Output	Output data.
`mgmt_write`	Input	Write signal. Active high.
`mgmt_read`	Input	Read signal. Active high.
`mgmt_waitrequest`	Output	When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

1G/10GbE PHY Register Definitions

You can access the 1G/10GbE registers using the Avalon-MM PHY management interface with word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

Notes:

Unless otherwise indicated, the default value of all registers is 0.
Writing to reserved or undefined register addresses may have undefined side effects.
To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to change the register values.

Table 60. 1G/10GbE Register Definitions
Addr	Bit	R/W	Name	Description
0xB0	0	RW	`Reset SEQ`	When set to 1, resets the sequencer. This bit must be used in conjunction with SEQ Force Mode[2:0] . This reset self clears.
	1			Reserved.
	2	RW	`Disable LF Timer`	When set to 1, disables the Link Fault timer. When set to 0, the Link Fault timer is enabled.
	6:4	RW	`SEQ Force Mode[2:0]`	Forces the sequencer to a specific protocol. Allows you to change speeds if you have turned on Enable automatic speed detection in the GUI. You must write the Reset SEQ bit to 1 for the Force to take effect. The following encodings are defined: 3'b000: No force 3'b001: GigE 3'b010: Reserved 3'b011: Reserved 3'b100: 10GBASE-R 3'b101: Reserved Others: Reserved
0xB1	0	RO	`SEQ Link Ready`	When asserted, the sequencer is indicating that the link is ready.

PMA Registers

The PMA registers allow you to reset the PMA and provide status information.

Table 42. Table 61. PMA Registers - Reset and Status. The following PMA registers allow you to reset the PMA and provide status information.
Addr	Bit	Access	Name	Description
0x22	0	RO	`pma_tx_pll_is_locked`	Indicates that the TX PLL is locked to the input reference clock.
0x44	1	RW	`reset_tx_digital`	Writing a 1 causes the internal TX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
	2	RW	`reset_rx_analog`	Writing a 1 causes the internal RX analog reset signal to be asserted. You must write a 0 to clear the reset condition.
	3	RW	`reset_rx_digital`	Writing a 1 causes the internal RX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
0x61	[31:0]	RW	`phy_serial_loopback`	Writing a 1 puts the channel in serial loopback mode.
0x64	[31:0]	RW	`pma_rx_set_locktodata`	When set, programs the RX CDR PLL to lock to the incoming data.
0x65	[31:0]	RW	`pma_rx_set_locktoref`	When set, programs the RX clock data recovery (CDR) PLL to lock to the reference clock.
0x66	[31:0]	RO	`pma_rx_is_lockedtodata`	When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode.
0x67	[31:0]	RO	`pma_rx_is_lockedtoref`	When asserted, indicates that the RX CDR PLL is locked to the reference clock.

Table 43. Table 62. PMA Registers - TX and RX Serial Data Interface . The following PMA registers allow you to customize the TX and RX serial data interface
Address	Bit	R/W	Name	Description
0xA8	0	RW	`tx_invpolarity`	When set to 1, the TX interface inverts the polarity of the TX data. Inverted TX data is output from the 8B/10B encoder.
	1	RW	`rx_invpolarity`	When set to 1, the RX channels inverts the polarity of the received data. Inverted RX data is input to the 8B/10B decoder.
	2	RW	`rx_bitreversal_enable`	When set to 1, enables bit reversal on the RX interface. The RX data is input to the word aligner.
	3	RW	`rx_bytereversal_enable`	When set, enables byte reversal on the RX interface. The RX data is input to the byte deserializer.
	4	RW	`force_electrical_idle`	When set to 1, forces the TX outputs to electrical idle.
0xA9	0	R	`rx_syncstatus`	When set to 1, indicates that the word aligner is synchronized to incoming data.
	1	R	`rx_patterndetect`	When set to 1, indicates the 1G word aligner has detected a comma.
	2	R	`rx_rlv`	When set to 1, indicates a run length violation.
	3	R	`rx_rmfifodatainserted`	When set to 1, indicates the rate match FIFO inserted code group.
	4	R	`rx_rmfifodatadeleted`	When set to 1, indicates that rate match FIFO deleted code group.
	5	R	`rx_disperr`	When set to 1, indicates an RX 8B/10B disparity error.
	6	R	`rx_errdetect`	When set to 1, indicates an RX 8B/10B error detected.

PCS Registers

Table 44. Table 63. PCS Registers. These registers provide PCS status information.
Addr	Bit	Access	Name	Description
0x80	31:0	RW	`Indirect_addr`	Because the PHY implements a single channel, this register must remain at the default value of 0 to specify logical channel 0.
0x81	2	RW	`RCLR_ERRBLK_CNT`	Error Block Counter clear register. When set to 1, clears the `RCLR_ERRBLK_CNT` register. When set to 0, normal operation continues.
0x81	3	RW	`RCLR_BER_COUNT`	BER Counter clear register. When set to 1, clears the `RCLR_BER_COUNT` register. When set to 0, normal operation continues.
0x82	1	RO	`HI_BER`	High BER status. When set to 1, the PCS is reporting a high BER. When set to 0, the PCS is not reporting a high BER.
	2	RO	`BLOCK_LOCK`	Block lock status. When set to 1, the PCS is locked to received blocks. When set to 0, the PCS is not locked to received blocks.
	3	RO	`TX_FULL`	When set to 1, the `TX_FIFO` is full.
	4	RO	`RX_FULL`	When set to 1, the `RX_FIFO` is full.
	5	RO	`RX_SYNC_HEAD_ERROR`	When set to 1, indicates an RX synchronization error.
	6	RO	`RX_SCRAMBLER_ERROR`	When set to 1, indicates an RX scrambler error.
	7	RO	`Rx_DATA_READY`	When set to 1, indicates the PHY is ready to receive data.

Table 45. Table 64. Pattern Generator Registers. 1G/10Gbps Ethernet PHY IP core supports the 10G PCS Pattern Generator.
Offset	Bits	R/W	Name	Description
0x12D	[15:0]	R/W	`Seed A for PRP`	Bits [15:0] of seed A for the pseudo-random pattern.
0x12E	[15:0]			Bits [31:16] of seed A for the pseudo-random pattern.