Intel Arria 10 Transceiver PHY User Guide

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UG-01143 | 2020.05.15

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Updated for:
Intel® Quartus® Prime Design Suite 20.1

1. Arria 10 Transceiver PHY Overview

This user guide provides details about the Arria^® 10 transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.

Intel^® Arria^® 10 FPGAs offer up to 96 GX transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques for chip-to-chip, chip-to-module, and backplane applications.

The Arria^® 10 GX and SX devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications.

The Arria^® 10 GT device has up to 6 GT transceiver channels, that can support data rates up to 25.8 Gbps for short reach chip-to-chip and chip-to-module applications. Additionally, the GT devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip and 12.5 Gbps for backplane applications. If all 6 GT channels are used in GT mode, then the GT device also has up to 54 GX transceiver channels.

The Arria^® 10 transceivers support reduced power modes with data rates up to 11.3 Gbps (chip-to-chip) for critical power sensitive designs. In GX devices that have transceivers on both sides of the device, each side can be operated independently in standard and reduced power modes. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.

Table 1. Data Rates Supported by GX Transceiver Channel Type
Device Variant	Standard Power Mode ¹ ^, ²		Reduced Power Mode ¹ ^, ²
Device Variant	Chip-to-Chip	Backplane	Chip-to-Chip
SX ³	1.0 Gbps to 17.4 Gbps	1.0 Gbps to 12.5 Gbps	1.0 Gbps to 11.3 Gbps
GX³	1.0 Gbps to 17.4 Gbps	1.0 Gbps to 12.5 Gbps	1.0 Gbps to 11.3 Gbps
GT ⁴	1.0 Gbps to 17.4 Gbps	1.0 Gbps to 12.5 Gbps	1.0 Gbps to 11.3 Gbps

Table 2. Data Rates Supported by GT Transceiver Channel Type
Device Variant ⁴	Data Rates⁵ ^, ²
Device Variant ⁴	Chip-to-Chip	Backplane
GT	1.0 Gbps to 25.8 Gbps	1.0 Gbps to 12.5 Gbps

Note: The device data rates depend on the device speed grade. Refer to Intel^® Arria^® 10 Device Datasheet for details on available speed grades and supported data rates.

¹ To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. Refer to the Arria 10 Device Datasheet for more details.

² The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

³ For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade.

⁴ For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade.

⁵ Because the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation.

1.1. Device Transceiver Layout

Figure 1. Arria^® 10 FPGA Architecture Block DiagramThe transceiver channels are placed on the left side periphery in most Arria^® 10 devices. For larger Arria 10 devices, additional transceiver channels are placed on the right side periphery.

1.1.1. Arria 10 GX Device Transceiver Layout

The largest Arria^® 10 GX device includes 96 transceiver channels. A column array of eight transceiver banks on the left and the right side periphery of the device is shown in the following figure. Each transceiver bank has six transceiver channels. Some devices have transceiver banks with only three channels. The transceiver banks with only three channels are the uppermost transceiver banks. Arria^® 10 devices also include PCI Express* Hard IP blocks.

The figures below illustrate different transceiver bank layouts for Arria^® 10 GX device variants.

For more information about PCIe* Hard IP transceiver placements, refer to Related Information at the end of this section.

Figure 2. Arria^® 10 GX Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks

Figure 3. Arria^® 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard IP Blocks.

Figure 4. Arria^® 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP Blocks

Figure 5. Arria^® 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks

Figure 6. Arria^® 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block

Figure 7. Arria^® 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block

1.1.2. Intel Arria 10 GT Device Transceiver Layout

The Intel^® Arria^® 10 GT device has 72 transceiver channels and four PCI Express* Hard IP blocks. A total of 6 GT transceiver channels that can support data rates up to 25.8 Gbps.

In the GT device, transceiver banks GXBL1E, GXBL1G, and GXBL1H each contain two GT transceiver channels. Transceiver banks GXBL1E and GXBL1H channels 3 and 4 can be used as GT or GX transceiver channel. Transceiver bank GXBL1G channels 0 and 1 can be used as GT or GX transceiver channels. When none of the GT capable transceiver channels are used as GT transceiver channels, the entire transceiver channels in the bank can be reconfigured as GX transceiver channels. However, when any of the GT capable transceiver channels in transceiver banks GXBL1E, GXBL1G, and GXBL1H is enabled as a GT transceiver channel, the remaining channels in the transceiver bank cannot be used with the exception of the other GT capable channel in the transceiver bank.

If you're using GT transceivers in bank GXBL1E, then the adjacent PCIe* Hard IP block cannot be used.

Figure 8. Intel^® Arria^® 10 GT Device with 72 Transceiver Channels and Four PCIe Hard IP Blocks

The GT device has 72 transceiver channels, which include 6 GT transceiver channels supporting data rates greater than 17.4 Gbps. If all six GT transceiver channels are used in GT mode, there are 54 GX transceiver channels that can drive chip to chip data rates up to 17.4 Gbps and backplanes at data rates up to 12.5 Gbps and 12 GX channels that are unusable.

In the GT device, the GX transceiver channels on the entire right side can be used in standard or reduced power mode. In GT devices where none of the GT channels are used to operate in GT data rates above 17.4 Gbps, the transceiver channels on either the entire right side or entire left side can be used as GX channels in standard or reduced power mode.

1.1.3. Arria 10 GX and GT Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express* Hard IP blocks for Arria^® 10 GX and GT devices.

Table 3. Package Details for GX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device

Package U19: 19mm x 19mm package; 484 pins.

Package F27: 27mm x 27mm package; 672 pins.

Package F29: 29mm x 29mm package; 780 pins.

Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.

Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
Device	U19	F27	F29	F34	F35	K F40	N F40
	Transceiver Count, PCIe* Hard IP Block Count
GX 016	6, 1	12, 1	12, 1
GX 022	6, 1	12, 1	12, 1
GX 027		12, 1	12, 1	24, 2	24, 2
GX 032		12, 1	12, 1	24, 2	24, 2
GX 048			12, 1	24, 2	36, 2
GX 057				24, 2	36, 2	36, 2	48, 2
GX 066				24, 2	36, 2	36, 2	48, 2
GX 090				24, 2			48, 2
GX 115				24, 2			48, 2

Table 4. Package Details for GX and GT Devices with Transceivers and Hard IP Blocks Located on the Left and Right Side Periphery of the Device

Package F40: 40 mm x 40 mm package size; 1517 pins. R = 66 transceiver channels.

Package F45: 45mm x 45mm package size; 1932 pins. N = 48 transceiver channels, S = 72 transceiver channels, U = 96 transceiver channels.

If you're using GT transceivers in bank GXBL1E, the nth adjacent PCIe Hard IP block cannot be used.
Device	R F40	N F45	S F45	U F45
	Transceiver Count, PCIe Hard IP Block Count
GX 090	66, 3	48, 4	72, 4	96, 4
GX 115	66, 3	48, 4	72, 4	96, 4
GT 090			72, 4
GT 115			72, 4

1.1.4. Arria 10 SX Device Transceiver Layout

The largest SX device includes 48 transceiver channels. All SX devices include GX transceiver channel type. The transceiver banks in SX devices are located on the left side periphery of the device.

For more information about PCIe* Hard IP transceiver placements, refer to Related Information at the end of this section.

Figure 9. Arria^® 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP Blocks

Figure 10. Arria^® 10 SX Device with 12 Transceiver Channels and One Hard IP Block

Figure 11. Arria^® 10 SX Device with Six Transceiver Channels and One Hard IP Block

1.1.5. Arria 10 SX Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express* Hard IP blocks for Arria^® 10 SX devices.

Table 5. Package Details for SX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device

Package U19: 19mm x 19mm package; 484 pins.

Package F27: 27mm x 27mm package; 672 pins.

Package F29: 29mm x 29mm package; 780 pins.

Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.

Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
Device	U19	F27	F29	F34	F35	K F40	N F40
	Transceiver Count, PCIe* Hard IP Block Count
SX 016	6, 1	12, 1	12, 1
SX 022	6, 1	12, 1	12, 1
SX 027		12, 1	12, 1	24, 2	24, 2
SX 032		12, 1	12, 1	24, 2	24, 2
SX 048			12, 1	24, 2	36, 2
SX 057				24, 2	36, 2	36, 2	48, 2
SX 066				24, 2	36, 2	36, 2	48, 2

1.2. Transceiver PHY Architecture Overview

A link is defined as a single entity communication port. A link can have one or more transceiver channels. A transceiver channel is synonymous with a transceiver lane.

For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of 10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B Physical Coding Sublayer (PCS) encoding and decoding).

1.2.1. Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes six transceiver channels in all devices except for the devices with 66 transceiver channels. Devices with 66 transceiver channels have both six channel and three channel transceiver banks. The uppermost transceiver bank on the left and the right side of these devices is a three channel transceiver bank. All other devices contain only six channel transceiver banks.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

Figure 12. Three-Channel GX Transceiver Bank Architecture

Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.

Figure 13. Six-Channel GX Transceiver Bank Architecture

Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.

Figure 14. GT Transceiver Bank ArchitectureIn the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.

Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.

Figure 15. GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H

Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.

The transceiver channels perform all the required PHY layer functions between the FPGA fabric and the physical medium. The high speed clock required by the transceiver channels is generated by the transceiver PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.

1.2.2. PHY Layer Transceiver Components

Transceivers in Arria^® 10 devices support both Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.

A PMA is the transceiver's electrical interface to the physical medium. The transceiver PMA consists of standard blocks such as:

serializer/deserializer (SERDES)
clock and data recovery PLL
analog front end transmit drivers
analog front end receive buffers

The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs. In PCS Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA fabric.

1.2.2.1. The GX Transceiver Channel

Figure 16. GX Transceiver Channel in Full Duplex Mode.

Arria^® 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 17.4 Gbps.

Table 6. PCS Types Supported by GX Transceiver Channels
PCS Type	Data Rate
Standard PCS	1.0 Gbps to 10.81344 Gbps
Enhanced PCS	1.0 Gbps ⁶ to 17.4 Gbps
PCIe* Gen3 PCS	8 Gbps

Note:

The GX channel can also operate in PCS Direct configuration for data rates from 1.0 Gbps to 17.4 Gbps. To operate GX transceiver channels in PCS Direct designated data rates, refer to the Intel^® Arria^® 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
To operate GX transceiver channels with the PCS at designated data rates, refer to the Intel^® Arria^® 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.

⁶ Applies when operating in reduced power modes. For standard power modes, the Enhanced PCS minimum data rate is 1600 Mbps.

1.2.2.2. The GT Transceiver Channel

The GT transceiver channels are used for supporting data rates from 17.4 Gbps to 25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration used to support GT data rates from 17.4 Gbps to 25.8 Gbps. Alternatively, the Enhanced PCS in Basic low latency configuration can also be used to support GT data rates from 17.4 Gbps to 25.8 Gbps. The GT transceiver channels can also be configured as GX transceiver channels. When they are configured as GX transceiver channels, the Standard PCS, Enhanced PCS, and PCIe* Gen3 PCS are available and they support data rates from 1.0 Gbps to 17.4 Gbps.

Figure 17. GT Transceiver Channel in Full Duplex Mode Operating Between 17.4 Gbps and 25.8 Gbps

Table 7. PCS Types and Data Rates Supported by GT Channel Configurations
GT Channel Configuration	PCS Type	Data Rates Supported
GT	Standard PCS	Not available for GT configuration
	Enhanced PCS	17.4 Gbps to 25.8 Gbps⁷
	PCIe Gen3 PCS	Not available for GT configuration
GX	Standard PCS	1.0 Gbps to 12 Gbps
	Enhanced PCS	1.0 Gbps ⁸ to 17.4 Gbps
	PCIe Gen3 PCS	8 Gbps

Note:

The GT channels can also operate in PCS Direct configuration for data rates from 1.0 Gbps to 25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration used to support GT data rates from 17.4 Gbps to 25.8 Gbps. To operate GX and GT transceiver channels in PCS Direct designated data rates, refer to the Intel^® Arria^® 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
To operate GX and GT transceiver channels with the PCS at designated data rates, refer to the Intel^® Arria^® 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.

⁷ The Enhanced PCS must be configured in Basic low latency mode to support data rate range from 17.4 Gbps to 25.8 Gbps.

⁸ Applies when operating in reduced power modes. For standard power modes, the Enhanced PCS minimum data rate is 1600 Mbps.

1.2.3. Transceiver Phase-Locked Loops

Each transceiver channel in Arria^® 10 devices has direct access to three types of high performance PLLs:

Advanced Transmit (ATX) PLL
Fractional PLL (fPLL)
Channel PLL / Clock Multiplier Unit (CMU) PLL.

These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

1.2.3.1. Advanced Transmit (ATX) PLL

An advanced transmit (ATX ) PLL is a high performance PLL. It supports both integer frequency synthesis and coarse resolution fractional frequency synthesis. The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported data rates required for high data rate applications.

1.2.3.2. Fractional PLL (fPLL)

A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for 12.5 Gbps and lower data rate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, the fPLL can also be used to synthesize frequencies that can drive the core through the FPGA fabric clock networks.

1.2.3.3. Channel PLL (CMU/CDR PLL)

A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in clock data recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be used as transmit PLLs.

1.2.4. Clock Generation Block (CGB)

In Arria^® 10 devices, there are two types of clock generation blocks (CGBs):

Master CGB
Local CGB

Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank. Transceiver banks with three channels have only one master CGB. The master CGB divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network.

Each transceiver channel has a local CGB. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.

1.3. Calibration

Arria^® 10 FPGAs contain a dedicated calibration engine to compensate for process variations. The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at optimum performance.

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance.

Note: For more information about CLKUSR electrical characteristics, refer to Intel^® Arria^® 10 Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For information about configuration requirements for the CLKUSR pin, refer to the Configuration, Design Security, and Remote System Upgrades in Arria^® 10 Devices chapter in the Arria^® 10 Core Fabric and General-Purpose I/O Handbook. For more information about calibration, refer to the Calibration chapter. For more information about CLKUSR pin requirements, refer to the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines.

1.4. Intel Arria 10 Transceiver PHY Overview Revision History

Document Version	Changes
2018.06.15	Made the following changes: Changed the data rate range for the Standard PCS in the "PCS types Supported by GX Transceiver Channels" table.
2016.05.02	Made the following changes: Maximum backplane rate updated from 16.0 Gbps to 12.5 Gbps. No Backplane support when VCCR/T_GXB=0.95 (Low Power Mode). Added a footnote to refer to Arria 10 Device datasheet for PCS Types Supported by GX and GT Transceiver Channels.
2016.02.11	Made the following changes: Changed the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks" figure. Changed the "GT Transceiver Bank Architecture" figure. Added the "GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H" figure.
2015.11.02	Made the following changes: Changed the minimum data rate from 611 Mbps to 1.0 Gbps. Changed the location of a PCIe Hard IP block in the "Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP Blocks" figure.
2015.05.11	Changed lower limit of supported data rate from 1.0 Gbps to 611 Mbps
2014.12.15	Made the following changes: Added statement that a 125-Mbps data rate is possible with oversampling in the "Arria 10 Transceiver PHY Overview" section. Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types Supported by GX Transceiver Channels" table. Changed the note in "The GX Transceiver Channel" section. Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types and Data Rates Supported by GT Channel Configurations" table. Added a legend entry to the "Arria 10 GT Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks" figure. Added a legend entry to the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks" figure. Added a legend entry to the "Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks" figure. Changed the note to the "PCS Types and Data Rates Supported by GT Channel Configurations" table. Changed the Data Rates Supported for GT channel Standard PCS and PCIe Gen3 PCS types in the "PCS Types and Data Rates Supported by GT Channel Configurations" table. Added a related link to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines in the "Calibration" section.
2014.08.15	Made the following changes: Changed the maximum data rate for GT channels to 25.8 Gbps. Changed minimum data rate supported by GT transceiver channels to 1 Gbps from 611 Mbps. Changed the figure "Arria 10 GX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to adda a clarification about PCIe Hard IP block. Updated the legend for all figures in "Arria 10 GT Device Transceiver Layout" section. Changed the device package names in Table1-3 and Table 1-4 in "Arria 10 GX and GT Device Package Details Section." Updated figure "Arria 10 SX Device with 48,36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks. Updated figure "Arria 10 SX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to add a clarification about PCIe Hard IP. Updated the device package names in Table 1-5 in "Arria 10 SX Device Package Details" section. Removed all references of the note about PCS-Direct support available in future release.
2013.12.02	Initial release.

2. Implementing Protocols in Arria 10 Transceivers

2.1. Transceiver Design IP Blocks

Figure 18. Arria^® 10 Transceiver Design Fundamental Building Blocks

2.2. Transceiver Design Flow

Figure 19. Transceiver Design Flow

Note: The design examples in the FPGA Developer Center provide useful guidance for developing your own design. However, they are not guaranteed by Intel.

2.2.1. Select and Instantiate the PHY IP Core

Select the appropriate PHY IP core to implement your protocol.

Refer to the Arria^® 10 Transceiver Protocols and PHY IP Support section to decide which PHY IP to select to implement your protocol.

You can create your Quartus^® Prime project first, and then instantiate the various IPs required for your design. In this case, specify the location to save your IP HDL files. The current version of the PHY IP does not have the option to set the speed grade. Specify the device family and speed grade when you create the Quartus^® Prime project.

You can also instantiate the PHY IP directly to evaluate the various features.

To instantiate a PHY IP:

Open the Quartus^® Prime software.
Click Tools > IP Catalog.
At the top of the IP Catalog window, select Arria^® 10 device family
In IP Catalog, under Library > Interface Protocols, select the appropriate PHY IP and then click Add.
In the New IP Instance Dialog Box, provide the IP instance name.
Select Arria^® 10 device family.
Select the appropriate device and click OK.

The PHY IP Parameter Editor window opens.

Figure 20. Arria^® 10 Transceiver PHY Types

2.2.2. Configure the PHY IP Core

Configure the PHY IP core by selecting the valid parameters for your design. The valid parameter settings are different for each protocol. Refer to the appropriate protocol's section for selecting valid parameters for each protocol.

2.2.3. Generate the PHY IP Core

After configuring the PHY IP, complete the following steps to generate the PHY IP.

Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.
Click Generate.

The Quartus^® Prime software generates a <phy ip instance name> folder, <phy ip instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design files used for simulation and compilation.

2.2.4. Select the PLL IP Core

Arria^® 10 devices have three types of PLL IP cores:

Advanced Transmit (ATX) PLL IP core.
Fractional PLL (fPLL) IP core.
Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.

Select the appropriate PLL IP for your design. For additional details, refer to the PLLs and Clock Networks chapter.

To instantiate a PLL IP:

Open the Quartus^® Prime software.
Click Tools > IP Catalog.
At the top of the IP Catalog window, select Arria^® 10 device family
In IP Catalog, under Library > Basic Functions > Clocks, PLLs, and Resets > PLL choose the PLL IP ( Arria^® 10 fPLL, Arria^® 10 Transceiver ATX PLL, or Arria^® 10 Transceiver CMU PLL) you want to include in your design and then click Add.
In the New IP Instance Dialog Box, provide the IP instance name.
Select Arria^® 10 device family.
Select the appropriate device and click OK.

The PLL IP GUI window opens.

Figure 21. Arria^® 10 Transceiver PLL Types

2.2.5. Configure the PLL IP Core

Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.

2.2.6. Generate the PLL IP Core

After configuring the PLL IP core, complete the following steps to generate the PLL IP core.

Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.
Click Generate.

The Quartus ^® Prime software generates a <pll ip core instance name> folder, <pll ip core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance name>.vhd file. The <pll ip core instance name>.v file is the top level design file for the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The other folders contain lower level design files used for simulation and compilation.

2.2.7. Reset Controller

There are two methods to reset the transceivers in Arria^® 10 devices:

Use the Transceiver PHY Reset Controller.
Create your own reset controller that follows the recommended reset sequence.

2.2.8. Create Reconfiguration Logic

Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings during device operation. To support dynamic reconfiguration, your design must include an Avalon master that can access the dynamic reconfiguration registers using the Avalon^® memory-mapped interface.

The Avalon^® memory-mapped interface master enables PLL and channel reconfiguration. You can dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-emphasis settings. This adjustment can be done by writing to the Avalon^® memory-mapped interface reconfiguration registers through the user generated Avalon^® memory-mapped interface master.

For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface and Dynamic Reconfiguration chapter.

2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller

Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to connect all the IP blocks.

All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy instance name>.vhd, and in the <phy_instance_name>_bb.v file.

For more information about description of the ports, refer to the ports tables in the PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.

2.2.10. Connect Datapath

Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.

2.2.11. Make Analog Parameter Settings

Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File.

After verifying your design functionality, make pin assignments and PMA analog parameter settings for the transceiver pins.

Assign FPGA pins to all the transceiver and reference clock I/O pins. For more details, refer to the Arria^® 10 Pin Connection Guidelines.
Set the analog parameters to the transmitter, receiver, and reference clock pins using the Assignment Editor.
All of the pin assignments and analog parameters set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Quartus Settings File (.qsf) to set PMA analog parameters.

2.2.12. Compile the Design

To compile the transceiver design, add the <phy_instancename>.qip files for all the IP blocks generated using the IP Catalog to the Quartus Prime project library. You can alternatively add the .qsys and .qip variants of the IP cores.

Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the software generates an error.

2.2.13. Verify Design Functionality

Simulate your design to verify the functionality of your design. For more details, refer to Simulating the Native Transceiver PHY IP Core section.

2.3. Arria 10 Transceiver Protocols and PHY IP Support

Table 8. Arria^® 10 Transceiver Protocols and PHY IP Support
Protocol	Transceiver PHY IP Core	PCS Support	Transceiver Configuration Rule⁹	Protocol Preset ¹⁰
PCIe* Gen3 x1, x2, x4, x8	Native PHY IP core (PIPE)/Hard IP for PCI Express* ¹¹	Standard and Gen3	Gen3 PIPE	PCIe PIPE Gen3 x1 PCIe PIPE Gen3 x8
PCIe Gen2 x1, x2, x4, x8	Native PHY IP (PIPE) core/Hard IP for PCI Express ¹¹	Standard	Gen2 PIPE	PCIe PIPE Gen2 x1 PCIe PIPE Gen2 x8
PCIe Gen1 x1, x2, x4, x8	Native PHY IP (PIPE) core/Hard IP for PCI Express ¹¹	Standard	Gen1 PIPE	User created
1000BASE-X Gigabit Ethernet	Native PHY IP core	Standard	GbE	GIGE - 1.25 Gbps
1000BASE-X Gigabit Ethernet with 1588	Native PHY IP core	Standard	GbE 1588	GIGE - 1.25 Gbps 1588
10GBASE-R	Native PHY IP core	Enhanced	10GBASE-R	10GBASE-R Low Latency
10GBASE-R 1588	Native PHY IP core	Enhanced	10GBASE-R 1588	10GBASE-R 1588
10GBASE-R with KR FEC	Native PHY IP core	Enhanced	10GBASE-R w/KR FEC	10GBASE-R w/KR FEC
10GBASE-KR and 1000BASE-X	1G/10GbE and 10GBASE-KR PHY IP¹²	Standard and Enhanced	Not applicable	BackPlane_wo_1588 LineSide (optical) LineSide(optical)_1588
40GBASE-R	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	Low Latency Enhanced PCS ¹³
40GBASE-R with FEC/40GBASE-KR4 ¹⁴	Native PHY IP core	Enhanced	Basic w/KR FEC	User created
100GBASE-R via CAUI-4/CPPI-4/BP and CEI-25G	Native PHY IP core	Enhanced and PCS Direct	Basic (Enhanced PCS) / PCS Direct	Low Latency GT¹⁵
100GBASE-R via CAUI	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	Low Latency Enhanced PCS ¹⁶
100GBASE-R via CAUI with FEC	Native PHY IP core	Enhanced	Basic w/KR FEC	User created
XAUI	XAUI PHY IP core	Soft PCS	Not applicable	Not applicable
SPAUI	Native PHY IP core	Standard and Enhanced	Basic/Custom (Standard PCS) Basic (Enhanced PCS)	User created
DDR XAUI	Native PHY IP core	Standard and Enhanced	Basic/Custom (Standard PCS) Basic (Enhanced PCS)	User created
Interlaken (CEI-6G/11G) ¹⁷	Native PHY IP core	Enhanced	Interlaken	Interlaken 10x12.5Gbps Interlaken 6x10.3Gbps Interlaken 1x6.25Gbps
OTU-4 (100G) via OTL4.10/OIF SFI-S	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	SFI-S 64:64 4x11.3 Gbps¹⁸
OTU-3 (40G) via OTL3.4/OIF SFI-5.2/SFI-5.1	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
OTU-2 (10G) via SFP+/SFF-8431/CEI-11G	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
OTU-2 (10G) via OIF SFI-5.1s	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
OTU-1 (2.7G)	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2/STL256.4	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.1	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SONET/SDH STS-192/STM-64 (10G) via SFP+/SFF-8431/CEI-11G	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SONET/SDH STS-192/STM-64 (10G) via OIF SFI-5.1s/SxI-5/SFI-4.2	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SONET STS-96 (5G) via OIF SFI-5.1s	Native PHY IP core	Enhanced	Basic/Custom (Standard PCS)	SONET/SDH OC-96
SONET/SDH STS-48/STM-16 (2.5G) via SFP/TFI-5.1	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	SONET/SDH OC-48
SONET/SDH STS-12/STM-4 (0.622G) via SFP/TFI-5.1	Native PHY IP core ¹⁹	Standard	Basic/Custom (Standard PCS)	SONET/SDH OC-12
Intel^® QPI 1.1/2.0	Native PHY IP core	PCS Direct	PCS Direct	User created
SD-SDI/HD-SDI/3G-SDI	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	3G/HD SDI NTSC 3G/HD SDI PAL
Vx1	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
DisplayPort ²⁰	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
1.25G/ 2.5G 10G GPON/EPON	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
2.5G/1.25G GPON/EPON	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
16G/10G Fibre Channel	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
8G/4G/2G/1G Fibre Channel	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
EDR Infiniband x1, x4	Native PHY IP core	Enhanced (low latency mode) PCS Direct	Basic (Enhanced PCS) PCS Direct	User created
FDR/FDR-10 Infiniband x1, x4, x12	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SDR/DDR/QDR Infiniband x1, x4, x12	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
CPRI v6.1 12.16512/CPRI v6.0 10.1376 Gbps	Native PHY IP core	Enhanced	10GBASE-R 1588 10GBASE-R	User created
CPRI 4.2/OBSAI RP3 v4.2	Native PHY IP core	Standard	CPRI (Auto) / CPRI (Manual)	CPRI 9.8Gbps Auto Mode CPRI 9.8 Gbps Manual Mode
SRIO 2.2/1.3	Native PHY IP core	Standard	Basic/Custom with Rate Match(Standard PCS)	Serial Rapid IO 1.25 Gbps
SAS 3.0	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
SATA 3.0/2.0/1.0 and SAS 2.0/1.1/1.0	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	SAS Gen2/Gen1.1/Gen1 SATA Gen3/Gen2/Gen1
HiGig/HiGig+/HiGig2/HiGig2+	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
JESD204A / JESD204B	Native PHY IP core	Standard and Enhanced	Basic/Custom (Standard PCS) Basic (Enhanced PCS) ²¹	User created
ASI	Native PHY IP core	Standard	Basic/Custom (Standard PCS)	User created
SPI-5 (100G) / SPI-5 (50G)	Native PHY IP core	Enhanced	Basic (Enhanced PCS)	User created
Custom and other protocols	Native PHY IP core	Standard and Enhanced PCS Direct	Basis/Custom (Standard PCS) Basic (Enhanced PCS) Basic/Custom with Rate Match (Standard PCS) PCS Direct	User created

⁹ For more information about Transceiver Configuration Rules, refer to Using the Intel^® Arria^® 10Transceiver Native PHY IP Core section.

¹⁰ For more information about Protocol Presets, refer to Using the Intel^® Arria^® 10Transceiver Native PHY IP Core section.

¹¹ Hard IP for PCI Express is also available as a separate IP core.

¹² The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed negotiation, and sequencer functions.

¹³ To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.

¹⁴ Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP.

¹⁵ Low Latency GT protocol preset requires some modification to implement CAUI-4/CPPI-4/BP-4 and CEI-25G.

¹⁶ To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.

¹⁷ A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.

¹⁸ To implement OTU-4 (100G) via OTL4.10/OIF SFI-S using SFI-S 64:64 4x11.3Gbps preset, change the number of data channels to 10 for OTL4.10 or user desired number of channels and datarate implemented for SFI-S.

¹⁹ The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

²⁰ To meet DisplayPort TX electrical full compliance to VESA DisplayPort Standard version 1.3 and VESA DisplayPort PHY Compliance Specification version 1.2b , VCCT_GXB & VCCR_GXB needs to be 1.03V or higher. Test Refer to AN745: Design Guidelines for DisplayPort and HDMI Interfaces for further details.

²¹ For JESD204B, Enhanced PCS is used when the data rate is above 12.0 Gbps

2.4. Using the Arria 10 Transceiver Native PHY IP Core

This section describes the use of the Intel^® -provided Arria^® 10 Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Arria^® 10 transceiver PHY features.

Use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. To instantiate the IP, click Tools > IP Catalog to select your IP core variation. Use the Parameter Editor to specify the IP parameters and configure the PHY IP for your protocol implementation. To quickly configure the PHY IP, select a preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.

You can also configure the PHY IP by selecting an appropriate Transceiver Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.

Use the Native PHY IP core to instantiate the following PCS options:

Standard PCS
Enhanced PCS
PCIe* Gen3 PCS
PCS Direct

Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you intend to dynamically reconfigure from one PCS to another. Refer to General and Datapath Parameters section for more details on how to enable PCS blocks for dynamic reconfiguration. Refer to the How to Place Channels for PIPE Configuration section or the PCIE solutions guides on restrictions on placement of transceiver channels next to active banks with PCI Express* interfaces that are Gen3 capable..

After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.

Figure 22. Native PHY IP Core Ports and Functional Blocks

Figure 23. Native PHY IP Core Parameter Editor

Note:

Although the Quartus^® Prime software provides legality checks, the supported FPGA fabric to PCS interface widths and the supported data rates are pending characterization.

2.4.1. Presets

You can select preset settings for the Native PHY IP core defined for each protocol. Use presets as a starting point to specify parameters for your specific protocol or application.

To apply a preset to the Native PHY IP core, double-click on the preset name. When you apply a preset, all relevant options and parameters are set in the current instance of the Native PHY IP core. For example, selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires.

Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Any changes that you make are validated by the design rules for the transceiver configuration rules you specified, not the selected preset.

Note: Selecting a preset clears any prior selections user has made so far.

2.4.2. General and Datapath Parameters

You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:

General, Common PMA Options, and Datapath Options
TX PMA
RX PMA
Standard PCS
Enhanced PCS
PCS Direct Datapath
Dynamic Reconfiguration
Analog PMA Settings (Optional)
Generation Options

Table 9. General, Common PMA Options, and Datapath Options
Parameter	Value	Description
Message level for rule violations	error warning	Specifies the messaging level for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations. ²²
`VCCR_GXB` and `VCCT_GXB` supply voltage for the Transceiver	0_9V, 1_0V, 1_1V	Selects the `VCCR_GXB` and `VCCT_GXB` supply voltage for the Transceiver. Note: This option is only used for GUI rule validation. Use Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Transceiver Link Type	sr, lr	Selects the type of transceiver link. sr-Short Reach (Chip-to-chip communication), lr-Long Reach (Backplane communication). Note: This option is only used for GUI rule validation. Use Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Transceiver configuration rules	User Selection	Specifies the valid configuration rules for the transceiver. This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings. To determine the transceiver configuration rule to be selected for your protocol, refer to the "Transceiver Configuration Rule Parameters" table below for more details about each transceiver configuration rule. This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.
PMA configuration rules	Basic SATA/SAS QPI GPON	Specifies the configuration rule for PMA. Select Basic for all other protocol modes except for SATA, GPON, and QPI. SATA (Serial ATA) can be used only if the Transceiver configuration rule is set to Basic/Custom (Standard PCS). GPON can be used only if the Transceiver configuration rule is set to Basic (Enhanced PCS). QPI can be used only if the Transceiver configuration rule is set to PCS Direct.
Transceiver mode	TX/RX Duplex TX Simplex RX Simplex	Specifies the operational mode of the transceiver. TX/RX Duplex : Specifies a single channel that supports both transmission and reception. TX Simplex : Specifies a single channel that supports only transmission. RX Simplex : Specifies a single channel that supports only reception. The default is TX/RX Duplex.
Number of data channels	1 – <n>	Specifies the number of transceiver channels to be implemented. The maximum number of channels available, ( <n> ), depends on the package you select. The default value is 1.
Data rate	< valid Transceiver data rate >	Specifies the data rate in megabits per second (Mbps).
Enable datapath and interface reconfiguration	On/Off	When you turn this option on, you can preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths. The default value is Off.
Enable simplified data interface	On/Off	By default, all 128-bits are ports for the `tx_parallel_data` and `rx_parallel_data` buses are exposed. You must understand the mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals. When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 128-bits that are active for a particular FPGA fabric width are ports. The default value is Off.²³
Provide separate interface for each channel	On/Off	When selected the Native PHY IP core presents separate data, reset and clock interfaces for each channel rather than a wide bus.

Table 10. Transceiver Configuration Rule Parameters
Transceiver Configuration Setting	Description
Basic/Custom (Standard PCS)	Enforces a standard set of rules within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match (Standard PCS)	Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
CPRI (Auto)	Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual)	Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.
GbE	Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588	Enforces rules for the 1 GbE protocol with support for Precision time protocol (PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE	Enforces rules for a Gen1 PCIe* ^® PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen2 PIPE	Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen3 PIPE	Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Basic (Enhanced PCS)	Enforces a standard set of rules within the Enhanced PCS. Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
Interlaken	Enforces rules required by the Interlaken protocol.
10GBASE-R	Enforces rules required by the 10GBASE-R protocol.
10GBASE-R 1588	Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
10GBASE-R w/KR FEC	Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
40GBASE-R w/KR FEC	Enforces rules required by the 40GBASE-R protocol with the KR FEC block enabled.
Basic w/KR FEC	Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block. Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
PCS Direct	Enforces rules required by the PCS Direct mode. In this configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.

²² Although you can generate the PHY with warnings, you can not compile the PHY in Quartus Prime.

²³ This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths, or reconfigure the interface of the transceiver.

2.4.3. PMA Parameters

You can specify values for the following types of PMA parameters:

TX PMA

TX Bonding Options
TX PLL Options
TX PMA Optional Ports

RX PMA

RX CDR Options
Equalization
RX PMA Optional Ports

Table 11. TX Bonding Options
Parameter	Value	Description
TX channel bonding mode	Not bonded PMA only bonding PMA and PCS bonding	Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available: Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated. PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master CGB generates the high speed and low parallel clocks and the local CGB for each channel is bypassed. Refer to the Channel Bonding section for more details. PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block. The default value is Not bonded. Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details.
PCS TX channel bonding master	Auto, 0 to <number of channels> -1	Specifies the master PCS channel for PCS bonded configurations. Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel. The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master.
Actual PCS TX channel bonding master	0 to <number of channels> -1	This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations.

Table 12. TX PLL Options
Parameter	Value	Description
TX local clock division factor	1, 2, 4, 8	Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.
Number of TX PLL clock inputs per channel	1, 2, 3 , 4	Specifies the number of TX PLL clock inputs per channel. Use this parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible.
Initial TX PLL clock input selection	0 to <number of TX PLL clock inputs> -1	Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs.

Table 13. TX PMA Optional Ports
Parameter	Value	Description
Enable tx_pma_analog_reset_ack port	On/Off	Enables the optional `tx_pma_analog_reset_ack` output port. This port should not be used for register mode data transfers.
Enable tx_pma_clkout port	On/Off	Enables the optional `tx_pma_clkout` output clock. This is the low speed parallel clock from the TX PMA. The source of this clock is the serializer. It is driven by the PCS/PMA interface block. ²⁴
Enable tx_pma_div_clkout port	On/Off	Enables the optional `tx_pma_div_clkout` output clock. This clock is generated by the serializer. You can use this to drive core logic, to drive the FPGA - transceivers interface. If you select a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a tx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA high serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.
tx_pma_div_clkout division factor	Disabled, 1, 2, 33, 40, 66	Selects the division factor for the `tx_pma_div_clkout` output clock when enabled. ²⁵
Enable tx_pma_iqtxrx_clkout port	On/Off	Enables the optional `tx_pma_iqtxrx_clkout` output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL.
Enable tx_pma_elecidle port	On/Off	Enables the `tx_pma_elecidle` port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express*.
Enable tx_pma_qpipullup port (QPI)	On/Off	Enables the `tx_pma_qpipullup` control input port. Use this port only for Quick Path Interconnect (QPI) applications.
Enable tx_pma_qpipulldn port (QPI)	On/Off	Enables the `tx_pma_qpipulldn` control input port. Use this port only for QPI applications.
Enable tx_pma_txdetectrx port (QPI)	On/Off	Enables the `tx_pma_txdetectrx` control input port. The receiver detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a `tx_pma_txdetectrx` request the receiver detect block initiates the detection process. Use this port only in QPI applications.
Enable tx_pma_rxfound port (QPI)	On/Off	Enables the `tx_pma_rxfound` status output port. The receiver detect block in TX PMA detects the presence of a receiver at the other end by using the `tx_pma_txdetectrx` input. The `tx_pma_rxfound` port reports the status of the detection operation. Use this port only in QPI applications.
Enable rx_seriallpbken port	On/Off	Enables the optional `rx_seriallpbken` control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.

Table 14. RX CDR Options
Parameter	Value	Description
Number of CDR reference clocks	1 - 5	Specifies the number of CDR reference clocks. Up to 5 sources are possible. The default value is 1. Use this feature when you want to dynamically re-configure CDR reference clock source.
Selected CDR reference clock	0 to <number of CDR reference clocks> -1	Specifies the initial CDR reference clock. This parameter determines the available CDR references used. The default value is 0.
Selected CDR reference clock frequency	< data rate dependent >	Specifies the CDR reference clock frequency. This value depends on the data rate specified.
PPM detector threshold	100 300 500 1000	Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock, exceeds this threshold value, the CDR loses lock. The default value is 1000.

Table 15. Equalization
Parameters	Value	Description
CTLE adaptation mode	Manual	Specifies the Continuous Time Linear Equalization (CTLE) operation mode. For manual mode, set the CTLE options through the Assignment Editor, or modify the Quartus Settings File (.qsf), or write to the reconfiguration registers using the Avalon Memory-Mapped interface. Refer to Continuous Time Linear Equalization (CTLE) section in Arria^® 10 Transceiver Architecture chapter for more details about CTLE architecture. Refer to How to Enable CTLE and DFE for more details on supported adaptation modes.
DFE adaptation mode	Adaptation enabled Manual, Disabled	Specifies the operating mode for the Decision Feedback Equalization (DFE) block in the RX PMA. The default value is Disabled. For manual mode, you can set the DFE options through the Assignment Editor, or by modifying the Quartus Settings File (.qsf), or write to the reconfiguration registers using the Avalon^® memory-mapped interface. Refer to the Decision Feedback Equalization (DFE) section in the Arria^® 10 Transceiver PHY Architecture chapter for more details about DFE. Refer to How to Enable CTLE and DFE for more details on supported adaptation modes.
Number of fixed DFE taps	3, 7 , 11	Specifies the number of fixed DFE taps. Select the number of taps depending on the loss in your transmission channel and the type of equalization required.

Table 16. RX PMA Optional Ports
Parameters	Value	Description
Enable rx_analog_reset_ack port	On/Off	Enables the optional `rx_analog_reset_ack` output. This port should not be used for register mode data transfers.
Enable rx_pma_clkout port	On/Off	Enables the optional `rx_pma_clkout` output clock. This port is the recovered parallel clock from the RX clock data recovery (CDR). ²⁶
Enable rx_pma_div_clkout port	On/Off	Enables the optional `rx_pma_div_clkout` output clock. The deserializer generates this clock. Use this to drive core logic, to drive the RX PCS-to-FPGA fabric interface, or both. If you select a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.
rx_pma_div_clkout division factor	Disabled, 1, 2, 33, 40, 66	Selects the division factor for the `rx_pma_div_clkout` output clock when enabled. ²⁷
Enable rx_pma_iqtxrx_clkout port	On/Off	Enables the optional `rx_pma_iqtxrx_clkout` output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL.
Enable rx_pma_clkslip port	On/Off	Enables the optional `rx_pma_clkslip` control input port. A rising edge on this signal causes the RX serializer to slip the serial data by one clock cycle, or 2 unit intervals (UI).
Enable rx_pma_qpipulldn port (QPI)	On/Off	Enables the `rx_pma_qpipulldn` control input port. Use this port only for QPI applications.
Enable rx_is_lockedtodata port	On/Off	Enables the optional `rx_is_lockedtodata` status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal.
Enable rx_is_lockedtoref port	On/Off	Enables the optional `rx_is_lockedtoref` status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal.
Enable rx_set_lockedtodata port and rx_set_lockedtoref ports	On/Off	Enables the optional `rx_set_lockedtodata` and `rx_set_lockedtoref` control input ports. You can use these control ports to manually control the lock mode of the RX CDR. These are asynchronous input signals.
Enable rx_seriallpbken port	On/Off	Enables the optional `rx_seriallpbken` control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.
Enable PRBS (Pseudo Random Bit Sequence) verifier control and status port	On/Off	Enables the optional `rx_prbs_err`, `rx_prbs_clr`, and `rx_prbs_done` control ports. These ports control and collect status from the internal PRBS verifier.

²⁴ This clock should not be used to clock the FPGA - transceivers interface. This clock may be used as a reference clock to an external clock cleaner.

²⁵ The default value is Disabled.

²⁶ This clock should not be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.

²⁷ The default value is Disabled.

2.4.4. Enhanced PCS Parameters

This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.

The following tables describe the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.

Note: For detailed descriptions about the optional ports that you can enable or disable, refer to the Enhanced PCS Ports section.

Table 17. Enhanced PCS Parameters
Parameter	Range	Description
Enhanced PCS / PMA interface width	32, 40, 64	Specifies the interface width between the Enhanced PCS and the PMA.
FPGA fabric /Enhanced PCS interface width	32, 40, , 64, 66, 67	Specifies the interface width between the Enhanced PCS and the FPGA fabric. The 66-bit FPGA fabric to PCS interface width uses 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus. The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus.
Enable Enhanced PCS low latency mode	On/Off	Enables the low latency path for the Enhanced PCS. When you turn on this option, the individual functional blocks within the Enhanced PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS. When enabled, this mode is applicable for GX devices. Intel recommends not enabling it for GT devices.
Enable RX/TX FIFO double width mode	On/Off	Enables the double width mode for the RX and TX FIFOs. You can use double width mode to run the FPGA fabric at half the frequency of the PCS.

Table 18. Enhanced PCS TX FIFO Parameters
Parameter	Range	Description
TX FIFO Mode	Phase-Compensation Register Interlaken Basic Fast Register	Specifies one of the following modes: Phase Compensation: The TX FIFO compensates for the clock phase difference between the read clock `rx_clkout` and the write clocks `tx_coreclkin` or `tx_clkout`. You can tie `tx_enh_data_valid` to 1'b1. Register: The TX FIFO is bypassed. The `tx_parallel_data`, `tx_control` and `tx_enh_data_valid` are registered at the FIFO output. Assert `tx_enh_data_valid` port 1'b1 at all times. The user must connect the write clock `tx_coreclkin` to the read clock `tx_clkout`. Interlaken: The TX FIFO acts as an elastic buffer. In this mode, there are additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You can control writes to the FIFO with `tx_enh_data_valid`. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reads. Basic: The TX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. `tx_coreclkin` or `rx_coreclkin` must have a minimum frequency of the lane data rate divided by 66. The frequency range for `tx_coreclkin` or `rx_coreclkin` is (data rate/32) - (data rate/66). For best results, Intel recommends that `tx_coreclkin` or `rx_coreclkin` = (data rate/32). Monitor FIFO flag to control write and read operations. For additional details refer to Enhanced PCS FIFO Operation section Fast Register: The TX FIFO allows a higher maximum frequency (f_MAX) between the FPGA fabric and the TX PCS at the expense of higher latency.
TX FIFO partially full threshold	10, 11, 12, 13	Specifies the partially full threshold for the Enhanced PCS TX FIFO. Enter the value at which you want the TX FIFO to flag a partially full status.
TX FIFO partially empty threshold	2, 3, 4, 5	Specifies the partially empty threshold for the Enhanced PCS TX FIFO. Enter the value at which you want the TX FIFO to flag a partially empty status.
Enable tx_enh_fifo_full port	On / Off	Enables the tx_enh_fifo_full port. This signal indicates when the TX FIFO is full. This signal is synchronous to `tx_coreclkin`.
Enable tx_enh_fifo_pfull port	On / Off	Enables the tx_enh_fifo_pfull port. This signal indicates when the TX FIFO reaches the specified partially full threshold. This signal is synchronous to `tx_coreclkin`.
Enable tx_enh_fifo_empty port	On / Off	Enables the tx_enh_fifo_empty port. This signal indicates when the TX FIFO is empty. This signal is synchronous to `tx_coreclkin`.
Enable tx_enh_fifo_pempty port	On / Off	Enables the tx_enh_fifo_pempty port. This signal indicates when the TX FIFO reaches the specified partially empty threshold. This signal is synchronous to `tx_coreclkin`.

Table 19. Enhanced PCS RX FIFO Parameters
Parameter	Range	Description
RX FIFO Mode	Phase-Compensation Register Interlaken 10GBASE-R Basic	Specifies one of the following modes for Enhanced PCS RX FIFO: Phase Compensation: This mode compensates for the clock phase difference between the read clocks `rx_coreclkin` or `tx_clkout` and the write clock `rx_clkout`. Register : The RX FIFO is bypassed. The`rx_parallel_data`, `rx_control`, and `rx_enh_data_valid` are registered at the FIFO output. The FIFO's read clock `rx_coreclkin` and write clock `rx_clkout` are tied together. Interlaken: Select this mode for the Interlaken protocol. To implement the deskew process, you must implement an FSM that controls the FIFO operation based on FIFO flags. In this mode the FIFO acts as an elastic buffer. 10GBASE-R: In this mode, data passes through the FIFO after block lock is achieved. OS (Ordered Sets) are deleted and Idles are inserted to compensate for the clock difference between the RX PMA clock and the fabric clock of +/- 100 ppm for a maximum packet length of 64000 bytes. Basic: In this mode, the RX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. `tx_coreclkin` or `rx_coreclkin` must have a minimum frequency of the lane data rate divided by 66. The frequency range for `tx_coreclkin` or `rx_coreclkin` is (data rate/32) - (data rate/66). The gearbox data valid flag controls the FIFO read enable. You can monitor the `rx_enh_fifo_pfull` and `rx_enh_fifo_empty` flags to determine whether or not to read from the FIFO. For additional details refer to Enhanced PCS FIFO Operation. Note: The flags are for Interlaken and Basic modes only. They should be ignored in all other cases.
RX FIFO partially full threshold	18-29	Specifies the partially full threshold for the Enhanced PCS RX FIFO. The default value is 23.
RX FIFO partially empty threshold	2-10	Specifies the partially empty threshold for the Enhanced PCS RX FIFO. The default value is 2.
Enable RX FIFO alignment word deletion (Interlaken)	On / Off	When you turn on this option, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
Enable RX FIFO control word deletion (Interlaken)	On / Off	When you turn on this option, Interlaken control word removal is enabled. When the Enhanced PCS RX FIFO is configured in Interlaken mode, enabling this option, removes all control words after frame synchronization is achieved. Enabling this option requires that you also enable alignment word deletion.
Enable rx_enh_data_valid port	On / Off	Enables the rx_enh_data_valid port. This signal indicates when RX data from RX FIFO is valid. This signal is synchronous to `rx_coreclkin.`
Enable rx_enh_fifo_full port	On / Off	Enables the rx_enh_fifo_full port. This signal indicates when the RX FIFO is full. This is an asynchronous signal.
Enable rx_enh_fifo_pfull port	On / Off	Enables the rx_enh_fifo_pfull port. This signal indicates when the RX FIFO has reached the specified partially full threshold. This is an asynchronous signal.
Enable rx_enh_fifo_empty port	On / Off	Enables the rx_enh_fifo_empty port. This signal indicates when the RX FIFO is empty. This signal is synchronous to `rx_coreclkin`.
Enable rx_enh_fifo_pempty port	On / Off	Enables the rx_enh_fifo_pempty port. This signal indicates when the RX FIFO has reached the specified partially empty threshold. This signal is synchronous to `rx_coreclkin`.
Enable rx_enh_fifo_del port (10GBASE‑R)	On / Off	Enables the optional rx_enh_fifo_del status output port. This signal indicates when a word has been deleted from the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This is an asynchronous signal.
Enable rx_enh_fifo_insert port (10GBASE‑R)	On / Off	Enables the rx_enh_fifo_insert port. This signal indicates when a word has been inserted into the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This signal is synchronous to `rx_coreclkin`.
Enable rx_enh_fifo_rd_en port	On / Off	Enables the rx_enh_fifo_rd_en input port. This signal is enabled to read a word from the RX FIFO. This signal is synchronous to `rx_coreclkin`.
Enable rx_enh_fifo_align_val port (Interlaken)	On / Off	Enables the rx_enh_fifo_align_val status output port. Only used for Interlaken transceiver configuration rule. This signal is synchronous to `rx_clkout`.
Enable rx_enh_fifo_align_clr port (Interlaken)	On / Off	Enables the rx_enh_fifo_align_clr input port. Only used for Interlaken. This signal is synchronous to `rx_clkout`.

Table 20. Interlaken Frame Generator Parameters
Parameter	Range	Description
Enable Interlaken frame generator	On / Off	Enables the frame generator block of the Enhanced PCS.
Frame generator metaframe length	5-8192	Specifies the metaframe length of the frame generator. This metaframe length includes 4 framing control words created by the frame generator.
Enable Frame Generator Burst Control	On / Off	Enables frame generator burst. This determines whether the frame generator reads data from the TX FIFO based on the input of port `tx_enh_frame_burst_en`.
Enable tx_enh_frame port	On / Off	Enables the `tx_enh_frame` status output port. When the Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enable tx_enh_frame_diag_status port	On / Off	Enables the `tx_enh_frame_diag_status` 2‑bit input port. When the Interlaken frame generator is enabled, the value of this signal contains the status message from the framing layer diagnostic word. This signal is synchronous to `tx_clkout`.
Enable tx_enh_frame_burst_en port	On / Off	Enables the `tx_enh_frame_burst_en` input port. When burst control is enabled for the Interlaken frame generator, this signal is asserted to control the frame generator data reads from the TX FIFO. This signal is synchronous to `tx_clkout`.

Table 21. Interlaken Frame Synchronizer Parameters
Parameter	Range	Description
Enable Interlaken frame synchronizer	On / Off	When you turn on this option, the Enhanced PCS frame synchronizer is enabled.
Frame synchronizer metaframe length	5-8192	Specifies the metaframe length of the frame synchronizer.
Enable rx_enh_frame port	On / Off	Enables the rx_enh_frame status output port. When the Interlaken frame synchronizer is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enable rx_enh_frame_lock port	On / Off	Enables the rx_enh_frame_lock output port. When the Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has achieved metaframe delineation. This is an asynchronous output signal.
Enable rx_enh_frame_diag_status port	On / Off	Enables therx_enh_frame_diag_status output port. When the Interlaken frame synchronizer is enabled, this signal contains the value of the framing layer diagnostic word (bits [33:32]). This is a 2 bit per lane output signal. It is latched when a valid diagnostic word is received. This is an asynchronous signal.

Table 22. Interlaken CRC32 Generator and Checker Parameters
Parameter	Range	Description
Enable Interlaken TX CRC-32 Generator	On / Off	When you turn on this option, the TX Enhanced PCS datapath enables the CRC32 generator function. CRC32 can be used as a diagnostic tool. The CRC contains the entire metaframe including the diagnostic word.
Enable Interlaken TX CRC-32 generator error insertion	On / Off	When you turn on this option, the error insertion of the interlaken CRC-32 generator is enabled. Error insertion is cycle-accurate. When this feature is enabled, the assertion of `tx_control[8]` or `tx_err_ins` signal causes the CRC calculation during that word is incorrectly inverted, and thus, the CRC created for that metaframe is incorrect.
Enable Interlaken RX CRC-32 checker	On / Off	Enables the CRC-32 checker function.
Enable rx_enh_crc32_err port	On / Off	When you turn on this option, the Enhanced PCS enables the rx_enh_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe. This is an asynchronous signal.

Table 23. 10GBASE-R BER Checker Parameters
Parameter	Range	Description
Enable rx_enh_highber port (10GBASE‑R)	On / Off	Enables the rx_enh_highber port. For 10GBASE-R transceiver configuration rule, this signal is asserted to indicate a bit error rate higher than 10 ^-4 . Per the 10GBASE-R specification, this occurs when there are at least 16 errors within 125 μs. This is an asynchronous signal.
Enable rx_enh_highber_clr_cnt port (10GBASE‑R)	On / Off	Enables the rx_enh_highber_clr_cnt input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_BAD_SH" state. This is an asynchronous signal.
Enable rx_enh_clr_errblk_count port (10GBASE‑R)	On / Off	Enables the rx_enh_clr_errblk_count input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of the times the RX state machine has entered the RX_E state. For protocols with FEC block enabled, this signal is asserted to reset the status counters within the RX FEC block. This is an asynchronous signal.

Table 24. 64b/66b Encoder and Decoder Parameters
Parameter	Range	Description
Enable TX 64b/66b encoder (10GBASE-R)	On / Off	When you turn on this option, the Enhanced PCS enables the TX 64b/66b encoder.
Enable RX 64b/66b decoder (10GBASE-R)	On / Off	When you turn on this option, the Enhanced PCS enables the RX 64b/66b decoder.
Enable TX sync header error insertion	On / Off	When you turn on this option, the Enhanced PCS supports cycle-accurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.

Table 25. Scrambler and Descrambler Parameters
Parameter	Range	Description
Enable TX scrambler (10GBASE-R/Interlaken)	On / Off	Enables the scrambler function. This option is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the scrambler in Basic (Enhanced PCS) mode when the block synchronizer is enabled and with 66:32, 66:40, or 66:64 gear box ratios.
TX scrambler seed (10GBASE-R/Interlaken)	User‑specified 58-bit value	You must provide a non-zero seed for the Interlaken protocol. For a multi-lane Interlaken Transceiver Native PHY IP, the first lane scrambler has this seed. For other lanes' scrambler, this seed is increased by 1 per each lane. The initial seed for 10GBASE-R is 0x03FFFFFFFFFFFFFF. This parameter is required for the 10GBASE‑R and Interlaken protocols.
Enable RX descrambler (10GBASE-R/Interlaken)	On / Off	Enables the descrambler function. This option is available for Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios.

Table 26. Interlaken Disparity Generator and Checker Parameters
Parameter	Range	Description
Enable Interlaken TX disparity generator	On / Off	When you turn on this option, the Enhanced PCS enables the disparity generator. This option is available for the Interlaken protocol.
Enable Interlaken RX disparity checker	On / Off	When you turn on this option, the Enhanced PCS enables the disparity checker. This option is available for the Interlaken protocol.
Enable Interlaken TX random disparity bit	On / Off	Enables the Interlaken random disparity bit. When enabled, a random number is used as disparity bit which saves one cycle of latency.

Table 27. Block Synchronizer Parameters
Parameter	Range	Description
Enable RX block synchronizer	On / Off	When you turn on this option, the Enhanced PCS enables the RX block synchronizer. This options is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
Enable rx_enh_blk_lock port	On / Off	Enables the `rx_enh_blk_lock` port. When you enable the block synchronizer, this signal is asserted to indicate that the block delineation has been achieved.

Table 28. Gearbox Parameters
Parameter	Range	Description
Enable TX data bitslip	On / Off	When you turn on this option, the TX gearbox operates in bitslip mode. The tx_enh_bitslip port controls number of bits which TX parallel data slips before going to the PMA.
Enable TX data polarity inversion	On / Off	When you turn on this option, the polarity of TX data is inverted. This allows you to correct incorrect placement and routing on the PCB.
Enable RX data bitslip	On / Off	When you turn on this option, the Enhanced PCS RX block synchronizer operates in bitslip mode. When enabled, the rx_bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS.
Enable RX data polarity inversion	On / Off	When you turn on this option, the polarity of the RX data is inverted. This allows you to correct incorrect placement and routing on the PCB.
Enable tx_enh_bitslip port	On / Off	Enables the tx_enh_bitslip port. When TX bit slip is enabled, this signal controls the number of bits which TX parallel data slips before going to the PMA.
Enable rx_bitslip port	On / Off	Enables the rx_bitslip port. When RX bit slip is enabled, the `rx_bitslip` signal is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS. This port is shared between Standard PCS and Enhanced PCS.

Note: If a design is slipping more bits than the PCS/PMA width, the Enhanced RX PCS FIFO could overflow. To clear the overflow, assert rx_digitalreset.

Table 29. KR-FEC Parameters
Parameter	Range	Description
Enable RX KR-FEC error marking	On/Off	When you turn on this option, the decoder asserts both sync bits (2'b11) when it detects an uncorrectable error. This feature increases the latency through the KR-FEC decoder.
Error marking type	10G, 40G	Specifies the error marking type (10G or 40G).
Enable KR-FEC TX error insertion	On/Off	Enables the error insertion feature of the KR-FEC encoder. This feature allows you to insert errors by corrupting data starting a bit 0 of the current word.
KR-FEC TX error insertion spacing	User Input (1 bit to 15 bit)	Specifies the spacing of the KR-FEC TX error insertion.
Enable tx_enh_frame port	On/Off	Enables the tx_enh_frame port.
Enable rx_enh_frame port	On/Off	Enables the rx_enh_frame port.
Enable rx_enh_frame_diag_status port	On/Off	Enables the rx_enh_frame_diag_status port.

2.4.5. Standard PCS Parameters

This section provides descriptions of the parameters that you can specify to customize the Standard PCS.

For specific information about configuring the Standard PCS for these protocols, refer to the sections of this user guide that describe support for these protocols.

Table 30. Standard PCS Parameters
Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the Standard PCS Ports section.
Parameter	Range	Description
Standard PCS/PMA interface width	8, 10, 16, 20	Specifies the data interface width between the Standard PCS and the transceiver PMA.
FPGA fabric/Standard TX PCS interface width	8, 10, 16, 20, 32, 40	Shows the FPGA fabric to TX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard TX PCS datapath.
FPGA fabric/Standard RX PCS interface width	8, 10, 16, 20, 32, 40	Shows the FPGA fabric to RX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard RX PCS datapath.
Enable Standard PCS low latency mode	On / Off	Enables the low latency path for the Standard PCS. Some of the functional blocks within the Standard PCS are bypassed to provide the lowest latency. You cannot turn on this parameter while using the Basic/Custom w/Rate Match (Standard PCS) specified for Transceiver configuration rules.

Table 31. Standard PCS FIFO Parameters
Parameter	Range	Description
TX FIFO mode	low_latency register_fifo fast_register	Specifies the Standard PCS TX FIFO mode. The following modes are available: low_latency: This mode adds 2-3 cycles of latency to the TX datapath. register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI. fast_register: This mode allows a higher maximum frequency (f_MAX) between the FPGA fabric and the TX PCS at the expense of higher latency.
RX FIFO mode	low_latency register_fifo	The following modes are available: low_latency: This mode adds 2-3 cycles of latency to the RX datapath. register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI or 1588.
Enable tx_std_pcfifo_full port	On / Off	Enables the `tx_std_pcfifo_full` port. This signal indicates when the standard TX phase compensation FIFO is full. This signal is synchronous with `tx_coreclkin`.
Enable tx_std_pcfifo_empty port	On / Off	Enables the `tx_std_pcfifo_empty` port. This signal indicates when the standard TX phase compensation FIFO is empty. This signal is synchronous with `tx_coreclkin`.
Enable rx_std_pcfifo_full port	On / Off	Enables the `rx_std_pcfifo_full` port. This signal indicates when the standard RX phase compensation FIFO is full. This signal is synchronous with `rx_coreclkin`.
Enable rx_std_pcfifo_empty port	On / Off	Enables the `rx_std_pcfifo_empty` port. This signal indicates when the standard RX phase compensation FIFO is empty. This signal is synchronous with `rx_coreclkin`.

Table 32. Byte Serializer and Deserializer Parameters
Parameter	Range	Description
Enable TX byte serializer	Disabled Serialize x2 Serialize x4	Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer. The byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Serialize x4 is only applicable for PCIe* protocol implementation.
Enable RX byte deserializer	Disabled Deserialize x2 Deserialize x4	Specifies the mode for the RX byte deserializer in the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA deserializer. The byte deserializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Deserialize x4 is only applicable for PCIe protocol implementation.

Table 33. 8B/10B Encoder and Decoder Parameters
Parameter	Range	Description
Enable TX 8B/10B encoder	On / Off	When you turn on this option, the Standard PCS enables the TX 8B/10B encoder.
Enable TX 8B/10B disparity control	On / Off	When you turn on this option, the Standard PCS includes disparity control for the 8B/10B encoder. You can force the disparity of the 8B/10B encoder using the `tx_forcedisp` control signal.
Enable RX 8B/10B decoder	On / Off	When you turn on this option, the Standard PCS includes the 8B/10B decoder.

Table 34. Rate Match FIFO Parameters
Parameter	Range	Description
RX rate match FIFO mode	Disabled Basic 10-bit PMA width Basic 20-bit PMA width GbE PIPE PIPE 0 ppm	Specifies the operation of the RX rate match FIFO in the Standard PCS. Rate Match FIFO in Basic (Single Width) Mode Rate Match FIFO Basic (Double Width) Mode Rate Match FIFO for GbE Transceiver Channel Datapath for PIPE
RX rate match insert/delete -ve pattern (hex)	User-specified 20 bit pattern	Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string.
RX rate match insert/delete +ve pattern (hex)	User-specified 20 bit pattern	Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.
Enable rx_std_rmfifo_full port	On / Off	Enables the optional `rx_std_rmfifo_full` port.
Enable rx_std_rmfifo_empty port	On / Off	Enables the `rx_std_rmfifo_empty` port.
PCI Express* Gen3 rate match FIFO mode	Bypass 0 ppm 600 ppm	Specifies the PPM tolerance for the PCI Express Gen3 rate match FIFO.

Table 35. Word Aligner and Bitslip Parameters
Parameter	Range	Description
Enable TX bitslip	On / Off	When you turn on this option, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the `tx_std_bitslipboundarysel` control signal.
Enable tx_std_bitslipboundarysel port	On / Off	Enables the `tx_std_bitslipboundarysel` control signal.
RX word aligner mode	bitslip manual (PLD controlled) synchronous state machine deterministic latency	Specifies the RX word aligner mode for the Standard PCS. The word aligned width depends on the PCS and PMA width, and whether or not 8B/10B is enabled. Refer to "Word Aligner" for more information.
RX word aligner pattern length	7, 8, 10, 16, 20, 32, 40	Specifies the length of the pattern the word aligner uses for alignment. Refer to "RX Word Aligner Pattern Length" table in "Word Aligner". It shows the possible values of "Rx Word Aligner Pattern Length" in all available word aligner modes.
RX word aligner pattern (hex)	User-specified	Specifies the word alignment pattern in hex.
Number of word alignment patterns to achieve sync	`0-255`	Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.
Number of invalid words to lose sync	`0-63`	Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.
Number of valid data words to decrement error count	`0-255`	Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.
Enable fast sync status reporting for deterministic Latency SM	On / Off	When enabled, the `rx_syncstatus` asserts high immediately after the deserializer has completed slipping the bits to achieve word alignment. When it is not selected, `rx_syncstatus` asserts after the cycle slip operation is complete and the word alignment pattern is detected by the PCS (i.e. `rx_patterndetect` is asserted). This parameter is only applicable when the selected protocol is CPRI (Auto).
Enable rx_std_wa_patternalign port	On / Off	Enables the `rx_std_wa_patternalign` port. When the word aligner is configured in manual mode and when this signal is enabled, the word aligner aligns to next incoming word alignment pattern.
Enable rx_std_wa_a1a2size port	On / Off	Enables the optional `rx_std_wa_a1a2size` control input port.
Enable rx_std_bitslipboundarysel port	On / Off	Enables the optional `rx_std_bitslipboundarysel` status output port.
Enable rx_bitslip port	On / Off	Enables the `rx_bitslip` port. This port is shared between the Standard PCS and Enhanced PCS.

Table 36. Bit Reversal and Polarity Inversion
Parameter	Range	Description
Enable TX bit reversal	On / Off	When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for serialization. The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. During the operation of the circuit, this setting can be changed through dynamic reconfiguration.
Enable TX byte reversal	On / Off	When you turn on this option, the 8B/10B Encoder reverses the byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS/PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules.
Enable TX polarity inversion	On / Off	When you turn on this option, the `tx_std_polinv` port controls polarity inversion of TX parallel data to the PMA. When you turn on this parameter, you also need to turn on the Enable tx_polinv port.
Enable tx_polinv port	On / Off	When you turn on this option, the `tx_polinv` input control port is enabled. You can use this control port to swap the positive and negative signals of a serial differential link, if they were erroneously swapped during board layout.
Enable RX bit reversal	On / Off	When you turn on this option, the word aligner reverses RX parallel data. The received RX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. This setting can be changed through dynamic reconfiguration. When you enable Enable RX bit reversal, you must also enable Enable rx_std_bitrev_ena port.
Enable rx_std_bitrev_ena port	On / Off	When you turn on this option and assert the `rx_std_bitrev_ena` control port, the RX data order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB.
Enable RX byte reversal	On / Off	When you turn on this option, the word aligner reverses the byte order, before storing the data in the RX FIFO. This function allows you to reverse the order of bytes that are erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS / PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules. When you enable Enable RX byte reversal, you must also select the Enable rx_std_byterev_ena port.
Enable rx_std_byterev_ena port	On / Off	When you turn on this option and assert the `rx_std_byterev_ena` input control port, the order of the individual 8‑ or 10‑bit words received from the PMA is swapped.
Enable RX polarity inversion	On / Off	When you turn on this option, the `rx_std_polinv` port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port.
Enable rx_polinv port	On / Off	When you turn on this option, the `rx_polinv` input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.
Enable rx_std_signaldetect port	On / Off	When you turn on this option, the optional `rx_std_signaldetect` output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified. You can specify the signal detect threshold using a Quartus Prime Assignment Editor or by modifying the Quartus Settings File (.qsf)

Table 37. PCIe Ports
Parameter	Range	Description
Enable PCIe dynamic datarate switch ports	On / Off	When you turn on this option, the `pipe_rate`, `pipe_sw`, and `pipe_sw_done` ports are enabled. You should connect these ports to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3 configurations. The `pipe_sw` and `pipe_sw_done` ports are only available for multi-lane bonded configurations.
Enable PCIe pipe_hclk_in and pipe_hclk_out ports	On / Off	When you turn on this option, the `pipe_hclk_in`, and `pipe_hclk_out` ports are enabled. The `pipe_hclk_in` port must be connected to the PLL IP core instance for the PCI Express configurations. The `pipe_hclk_out` port can be left floating when you connect `tx_clkout` to the MAC clock input.
Enable PCIe Gen3 analog control ports	On / Off	When you turn on this option, the `pipe_g3_txdeemph` and `pipe_g3_rxpresenthint` ports are enabled. You can use these ports for equalization for Gen3 configurations.
Enable PCIe electrical idle control and status ports	On / Off	When you turn on this option, the `pipe_rx_eidleinfersel` and `pipe_rx_elecidle` ports are enabled. These ports are used for PCI Express configurations.
Enable PCIe pipe_rx_polarity port	On / Off	When you turn on this option, the `pipe_rx_polarity` input control port is enabled. You can use this option to control channel signal polarity for PCI Express configurations. When the Standard PCS is configured for PCIe, the assertion of this signal inverts the RX bit polarity. For other Transceiver configuration rules the optional `rx_polinv` port inverts the polarity of the RX bit stream.

2.4.6. PCS Direct

PCS Direct Datapath Parameters
Parameter	Range	Description
PCS Direct interface width	8, 10, 16, 20, 32, 40, 64	Specifies the data interface width between the PLD and the transceiver PMA.

2.4.7. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device.

Each transceiver channel and PLL includes an Avalon^® memory-mapped interface slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon^® memory-mapped interface slave interface, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.

You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.

To enable Intel^® Arria^® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

Enable dynamic reconfiguration
Enable Native PHY Debug Master Endpoint
Enable capability registers
Enable control and status registers
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators

Table 38. Dynamic Reconfiguration
Parameter	Value	Description
Enable dynamic reconfiguration	On/Off	When you turn on this option, the dynamic reconfiguration interface is enabled.
Share reconfiguration interface	On/Off	When you turn on this option, the Transceiver Native PHY IP presents a single Avalon^® memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.
Enable Native PHY Debug Master Endpoint	On/Off	When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon^® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE	On/Off	When enabled, the `reconfig_waitrequest` does not indicate the status of Avalon^® memory-mapped interface arbitration with PreSICE. The Avalon^® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.

Table 39. Optional Reconfiguration Logic
Parameter	Value	Description
Enable capability registers	On/Off	Enables capability registers that provide high level information about the configuration of the transceiver channel.
Set user-defined IP identifier	User-defined	Sets a user-defined numeric identifier that can be read from the `user_identifier` offset when the capability registers are enabled.
Enable control and status registers	On/Off	Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators	On/Off	Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.

Table 40. Configuration Files
Parameter	Value	Description
Configuration file prefix	<prefix>	Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
Generate SystemVerilog package file	On/Off	When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.
Generate C header file	On/Off	When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.
Generate MIF (Memory Initialization File)	On/Off	When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
Include PMA analog settings in configuration files	On/Off	When enabled, the IP allows you to configure the PMA analog settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files. Note: You must still specify the analog settings for your current configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog Parameter Settings chapter in the Arria^® 10 Transceiver PHY User Guide for details on using the QSF assignments.

Table 41. Configuration Profiles
Parameter	Value	Description
Enable multiple reconfiguration profiles	On/Off	When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.²⁸
Enable embedded reconfiguration streamer	On/Off	Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.
Generate reduced reconfiguration files	On/Off	When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.
Number of reconfiguration profiles	1-8	Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selected reconfiguration profile	0-7	Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile.
Store configuration to selected profile	-	Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile	-	Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile	-	Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.
Clear all profiles	-	Clicking this button clears the Native PHY parameter settings for all the profiles.
Refresh selected profile	-	Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.

Table 42. Analog PMA Settings (Optional) for Dynamic Reconfiguration
Parameter	Value	Description
TX Analog PMA Settings
Analog Mode (Load Intel-recommended Default settings)	Cei_11100_lr to xfp_9950	Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings.
Override Intel-recommended Analog Mode Default settings	On/Off	Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters.
Output Swing Level (VOD)	0-31	Selects the transmitter programmable output differential voltage swing.
Pre-Emphasis First Pre-Tap Polarit	`Fir_pre_1t_neg` `Fir_pre_1t_pos`	Selects the polarity of the first pre-tap for pre-emphasis.
Pre-Emphasis First Pre-Tap Magnitude	0-16 ²⁹	Selects the magnitude of the first pre-tap for pre-emphasis
Pre-Emphasis Second Pre-Tap Polarity	`Fir_pre_2t_neg` `Fir_pre_2t_pos`	Selects the polarity of the second pre-tap for pre-emphasis.
Pre-Emphasis Second Pre-Tap Magnitude	0-7 ³⁰	Selects the magnitude of the second pre-tap for pre-emphasis.
Pre-Emphasis First Post-Tap Polarity	Fir_post_1t_neg Fir_post_1t_pos	Selects the polarity of the first post-tap for pre-emphasis
Pre-Emphasis First Post-Tap Magnitude	0-25 ³¹	Selects the magnitude of the first post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Polarity	`Fir_post_2t_neg` `Fir_post_2t_pos`	Selects the polarity of the second post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Magnitude	0-12 ³²	Selects the magnitude of the second post-tap for pre-emphasis
Slew Rate Control	`slew_r0` to `slew_r5`	Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
High-Speed Compensation	Enable/Disable	Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
On-Chip termination	`r_r1` `r_r2`	Selects the on-chip TX differential termination.
RX Analog PMA settings
Override Intel-recommended Default settings	On/Off	Enables the option to override the Intel-recommended settings for one or more RX analog parameters
CTLE (Continuous Time Linear Equalizer) mode	`non_s1_mode` `S1_mode`	Selects between the RX high gain mode `non_s1_mode` or RX high data rate mode `s1_mode` for the Continuous Time Linear Equalizer (CTLE).
DC gain control of high gain mode CTLE	`No_dc_gain` to `stg4_gain7`	Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode
AC Gain Control of High Gain Mode CTLE	`radp_ctle_acgain_4s_0` to `radp_ctle_acgain_4s_28`	Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode.
AC Gain Control of High Data Rate Mode CTLE	`radp_ctle_eqz_1s_sel_0` to `Radp_ctle_eqz_1s_sel_15`	Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high data rate mode when CTLE is in manual mode.
Variable Gain Amplifier (VGA) Voltage Swing Select	`radp_vga_sel_0` to`radp_vga_sel_7`	Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 1 Co-efficient	`radp_dfe_fxtap1_0` to `radp_dfe_fxtap1_127`	Selects the co-efficient of the fixed tap 1 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 2 Co-efficient	`radp_dfe_fxtap2_0` to `radp_dfe_fxtap2_127`	Selects the co-efficient of the fixed tap 2 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 3 Co-efficient	`radp_dfe_fxtap3_0` to `radp_dfe_fxtap3_127`	Selects the co-efficient of the fixed tap 3 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 4 Co-efficient	`radp_dfe_fxtap4_0` to `radp_dfe_fxtap4_63`	Selects the co-efficient of the fixed tap 4 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 5 Co-efficient	`radp_dfe_fxtap5_0` to `radp_dfe_fxtap5_63`	Selects the co-efficient of the fixed tap 5 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 6 Co-efficient	`radp_dfe_fxtap6_0` to `radp_dfe_fxtap6_31`	Selects the co-efficient of the fixed tap 6 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 7 Co-efficient	`radp_dfe_fxtap7_0` to `radp_dfe_fxtap7_31`	Selects the co-efficient of the fixed tap 7 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 8 Co-efficient	`radp_dfe_fxtap8_0` to `radp_dfe_fxtap8_31`	Selects the co-efficient of the fixed tap 8 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 9 Co-efficient	`radp_dfe_fxtap9_0` to `radp_dfe_fxtap9_31`	Selects the co-efficient of the fixed tap 9 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 10 Co-efficient	`radp_dfe_fxtap10_0` to `radp_dfe_fxtap10_31`	Selects the co-efficient of the fixed tap 10 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 11 Co-efficient	`radp_dfe_fxtap11_0` to `radp_dfe_fxtap11_31`	Selects the co-efficient of the fixed tap 11 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
On-Chip termination	`R_ext0, r_r1, r_r2`	Selects the on-chip RX differential termination.

Table 43. Generation Options
Parameter	Value	Description
Generate parameter documentation file	On/Off	When you turn on this option, generation produces a Comma-Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters.

²⁸ For more information on timing closure, refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter.

²⁹ For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter Settings chapter.

³⁰ For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter Settings chapter.

³¹ For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter Settings chapter.

³² For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter Settings chapter.

2.4.8. PMA Ports

This section describes the PMA and calibration ports for the Arria^® 10 Transceiver Native PHY IP core.

The following tables, the variables represent these parameters:

<n>—The number of lanes
<d>—The serialization factor
<s>—The symbol size
<p>—The number of PLLs

Table 44. TX PMA Ports
Name	Direction	Clock Domain	Description
`tx_serial_data[<n>-1:0]`	Input	N/A	This is the serial data output of the TX PMA.
`tx_serial_clk0`	Input	Clock	This is the serial clock from the TX PLL. The frequency of this clock depends on the data rate and clock division factor. This clock is for non bonded channels only. For bonded channels use the `tx_bonding_clocks` clock TX input.
`tx_bonding_clocks[<n><6>-1:0]`	Input	Clock	This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only.
Optional Ports
`tx_serial_clk1` `tx_serial_clk2` `tx_serial_clk3` `tx_serial_clk4`	Inputs	Clocks	These are the serial clocks from the TX PLL. The frequency of these clocks depends on the data rate and clock division factor. These additional ports are enabled when you specify more than one TX PLL.
`tx_analog_reset_ack`	Output	Asynchronous	Enables the optional `tx_pma_analog_reset_ack` output. This port should not be used for register mode data transfers
`tx_pma_clkout`	Output	Clock	This clock is the low speed parallel clock from the TX PMA. It is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP core Parameter Editor. ³³
`tx_pma_div_clkout`	Output	Clock	If you specify a `tx_pma_div_clkout` division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a `tx_pma_div_clkout` division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.
`tx_pma_iqtxrx_clkou`t	Output	Clock	This port is available if you turn on Enable tx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL.
`tx_pma_elecidle[<n>-1:0]`	Input	Asynchronous	When you assert this signal, the transmitter is forced to electrical idle. This port has no effect when you configure the transceiver for the PCI Express* protocol.
`tx_pma_qpipullup[<n>-1:0]`	Input	Asynchronous	This port is available if you turn on Enable tx_pma_qpipullup port (QPI) in the Transceiver Native PHY IP core Parameter Editor. It is only used for Quick Path Interconnect (QPI) applications.
`tx_pma_qpipulldn[<n>-1:0]`	Input	Asynchronous	This port is available if you turn on Enable tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY IP core Parameter Editor. It is only used for Quick Path Interconnect (QPI) applications.
`tx_pma_txdetectrx[<n>-1:0]`	Input	Asynchronous	This port is available if you turn on Enable tx_pma_txdetectrx port (QPI) in the Transceiver Native PHY IP core Parameter Editor. When asserted, the receiver detect block in TX PMA detects the presence of a receiver at the other end of the channel. After receiving the `tx_pma_txdetectrx` request, the receiver detect block initiates the detection process. Use this port for Quick Path Interconnect (QPI) applications only.
`tx_pma_rxfound[<n>-1:0]`	Output	Synchronous to `rx_coreclkin` or `rx_clkout` based on the configuration.	This port is available if you turn on Enable tx_rxfound_pma port (QPI) in the Transceiver Native PHY IP core Parameter Editor. When asserted, indicates that the receiver detect block in TX PMA has detected a receiver at the other end of the channel. Use this port for Quick Path Interconnect (QPI) applications only.
`rx_seriallpbken[<n>-1:0]`	Input	Asynchronous	This port is available if you turn on Enable rx_seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.

Table 45. RX PMA Ports
Name	Direction	Clock Domain	Description
`rx_serial_data[<n>-1:0]`	Input	N/A	Specifies serial data input to the RX PMA.
`rx_cdr_refclk0`	Input	Clock	Specifies reference clock input to the RX clock data recovery (CDR) circuitry.
Optional Ports
`rx_cdr_refclk1`– `rx_cdr_refclk4`	Input	Clock	Specifies reference clock inputs to the RX clock data recovery (CDR) circuitry.
`rx_analog_reset_ack`	Output	Asynchronous	Enables the optional rx_pma_analog_reset_ack output. This port should not be used for register mode data transfers.
`rx_pma_clkout`	Output	Clock	This clock is the recovered parallel clock from the RX CDR circuitry.
`rx_pma_div_clkout`	Output	Clock	The deserializer generates this clock. This is used to drive core logic, PCS-to-FPGA fabric interface, or both. If you specify a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock (low speed parallel clock) frequency, such as 66:40 applications.
`rx_pma_iqtxrx_clkout`	Output	Clock	This port is available if you turn on Enable rx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.
`rx_pma_clkslip`	Output	Clock	When asserted, indicates that the deserializer has either skipped one serial bit or paused the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.
`rx_pma_qpipulldn[<n>-1:0]`	Input	Asynchronous	This port is only used for Quick Path Interconnect (QPI) applications.
`rx_is_lockedtodata[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates that the CDR PLL is locked to the incoming data, `rx_serial_data`.
`rx_is_lockedtoref[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates that the CDR PLL is locked to the input reference clock.
`rx_set_locktodata[<n>-1:0]`	Input	Asynchronous	This port provides manual control of the RX CDR circuitry.
`rx_set_locktoref[<n>-1:0]`	Input	Asynchronous	This port provides manual control of the RX CDR circuitry.
`rx_seriallpbken[<n>-1:0]`	Input	Asynchronous	This port is available if you turn on Enable rx_ seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal is enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.
`rx_prbs_done[<n>-1:0]`	Output	`rx_coreclkin` or `rx_clkout`	When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.
`rx_prbs_err[<n>-1:0]`	Output	`rx_coreclkin` or `rx_clkout`	When asserted, indicates an error only after the `rx_prbs_done` signal has been asserted. This signal gets asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word.
`rx_prbs_err_clr[<n>-1:0]`	Input	`rx_coreclkin` or `rx_clkout`	When asserted, clears the PRBS pattern and deasserts the `rx_prbs_done` signal.

Table 46. Calibration Status Ports
Name	Direction	Clock Domain	Description
`tx_cal_busy[<n>-1:0]`	Output	Asynchronous	When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes.
`rx_cal_busy[<n>-1:0]`	Output	Asynchronous	When asserted, indicates that the initial RX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed.

Table 47. Reset Ports
Name	Direction	Clock Domain³⁴	Description
`tx_analogreset[<n>-1:0]`	Input	Asynchronous	Resets the analog TX portion of the transceiver PHY.
`tx_digitalreset[<n>-1:0]`	Input	Asynchronous	Resets the digital TX portion of the transceiver PHY.
`rx_analogreset[<n>-1:0]`	Input	Asynchronous	Resets the analog RX portion of the transceiver PHY.
`rx_digitalreset[<n>-1:0]`	Input	Asynchronous	Resets the digital RX portion of the transceiver PHY.

³³ This clock is not to be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.

³⁴ Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock.

2.4.9. Enhanced PCS Ports

Figure 24. Enhanced PCS InterfacesThe labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.

In the following tables, the variables represent these parameters:

<n>—The number of lanes
<d>—The serialization factor
<s>— The symbol size
<p>—The number of PLLs

Table 48. Enhanced TX PCS: Parallel Data, Control, and Clocks
Name	Direction	Clock Domain	Description
`tx_parallel_data[<n>128-1:0]`	Input	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified interface in the Transceiver Native PHY IP Parameter Editor, `tx_parallel_data` includes only the bits required for the configuration you specify. You must ground the data pins that are not active. For single width configuration, the following bits are active: 32-bit FPGA fabric to PCS interface width: tx_parallel_data[31:0]. Ground [127:32]. 40-bit FPGA fabric to PCS interface width: tx_parallel_data[39:0]. Ground [127:40]. 64-bit FPGA fabric to PCS interface width: tx_parallel_data[63:0] Ground [127:64]. For double width configuration, the following bits are active: 40-bit FPGA fabric to PCS interface width: data[103:64], [39:0]. Ground [127:104], [63:40]. 64-bit FPGA fabric to PCS interface width: data[127:64], [63:0]. Double-width mode is not supported for 32-bit, 50-bit, and 67-bit FPGA fabric to PCS interface widths.
`unused_tx_parallel_data`	Input	`tx_clkout`	Port is enabled, when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a part of `tx_parallel_data`. Refer to `tx_parallel_data` to identify the bits you need to ground.
`tx_control[<n><3>-1:0]` or `tx_control[<n><18>-1:0]`	Input	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	`tx_control` bits have different functionality depending on the transceiver configuration rule selected. When Simplified data interface is enabled, the number of bits in this bus change because the unused bits are shown as part of the `unused_tx_control` port. Refer to Enhanced PCS TX and RX Control Ports section for more details.
`unused_tx_control[<n> <15>-1:0]`	Input	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	This port is enabled when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a part of the `tx_control`. Refer to `tx_control` to identify the bits you need to ground.
`tx_err_ins`	Input	`tx_coreclkin`	For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on Enable simplified data interface. When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe. Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP GUI.
`tx_coreclkin`	Input	Clock	The FPGA fabric clock. Drives the write side of the TX FIFO. For the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption.
`tx_clkout`	Output	Clock	This is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX Enhanced PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width.

Table 49. Enhanced RX PCS: Parallel Data, Control, and Clocks
Name	Direction	Clock Domain	Description
`rx_parallel_data[<n>128-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver Native PHY IP GUI, `rx_parallel_data` includes only the bits required for the configuration you specify. Otherwise, this interface is 128 bits wide. When FPGA fabric to PCS interface width is 64 bits, the following bits are active for interfaces less than 128 bits. You can leave the unused bits floating or not connected. 32-bit FPGA fabric to PCS width: data[31:0]. 40-bit FPGA fabric to PCS width: data[39:0]. 64-bit FPGA fabric to PCS width: data[63:0]. When the FPGA fabric to PCS interface width is 128 bits, the following bits are active: 40-bit FPGA fabric to PCS width: data[103:64], [39:0]. 64-bit FPGA fabric to PCS width: data[127:0].
`unused_rx_parallel_data`	Output	`rx_clkout`	This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of `rx_parallel_data`. You can leave the unused data outputs floating or not connected.
`rx_control[<n> <20>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	Indicates whether the `rx_parallel_data` bus is control or data. Refer to the Enhanced PCS TX and RX Control Ports section for more details.
`unused_rx_control[<n>10-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	These signals only exist when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of `rx_control`. These outputs can be left floating.
`rx_coreclkin`	Input	Clock	The FPGA fabric clock. Drives the read side of the RX FIFO. For Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32.
`rx_clkout`	Output	Clock	The low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX Enhanced PCS. The frequency of this clock is equal to data rate divided by PCS/PMA interface width.

Table 50. Enhanced PCS TX FIFO
Name	Direction	Clock Domain	Description
`tx_enh_data_valid[<n>-1:0]`	Input	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	Assertion of this signal indicates that the TX data is valid. Connect this signal to 1'b1 for 10GBASE-R without 1588. For 10GBASE-R with 1588, you must control this signal based on the gearbox ratio. For Basic and Interlaken, you need to control this port based on TX FIFO flags so that the FIFO does not underflow or overflow. Refer to Enhanced PCS FIFO Operation for more details.
`tx_enh_fifo_full[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	Assertion of this signal indicates the TX FIFO is full. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`tx_enh_fifo_pfull[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO `tx_coreclkin` or `tx_clkout`	This signal gets asserted when the TX FIFO reaches its partially full threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`tx_enh_fifo_empty[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO `tx_coreclkin` or `tx_clkout`	When asserted, indicates that the TX FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`tx_enh_fifo_pempty[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO `tx_coreclkin` or `tx_clkout`	When asserted, indicates that the TX FIFO has reached its specified partially empty threshold. When you turn this option on, the Enhanced PCS enables the `tx_enh_fifo_pempty` port, which is asynchronous. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.

Table 51. Enhanced PCS RX FIFO
Name	Direction	Clock Domain	Description
`rx_enh_data_valid[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that `rx_parallel_data` is valid. Discard invalid RX parallel data when`rx_enh_data_valid` signal is low. This option is available when you select the following parameters: Enhanced PCS Transceiver configuration rules specifies Interlaken Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Phase compensation Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Register Refer to Enhanced PCS FIFO Operation for more details.
`rx_enh_fifo_full[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that the RX FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`rx_enh_fifo_pfull[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that the RX FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`rx_enh_fifo_empty[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that the RX FIFO is empty. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`rx_enh_fifo_pempty[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that the RX FIFO has reached its specified partially empty threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode. Refer to Enhanced PCS FIFO Operation for more details.
`rx_enh_fifo_del[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that a word has been deleted from the RX FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol.
`rx_enh_fifo_insert[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that a word has been inserted into the RX FIFO. This signal is used for the 10GBASE-R protocol.
`rx_enh_fifo_rd_en[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	For Interlaken only, when this signal is asserted, a word is read form the RX FIFO. You need to control this signal based on RX FIFO flags so that the FIFO does not underflow or overflow.
`rx_enh_fifo_align_val[<n>-1:0]`	Input	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, indicates that the word alignment pattern has been found. This signal is only valid for the Interlaken protocol.
`rx_enh_fifo_align_clr[<n>-1:0]`	Input	Synchronous to the clock driving the read side of the FIFO `rx_coreclkin` or `rx_clkout`	When asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles.

Table 52. Interlaken Frame Generator, Synchronizer, and CRC32
Name	Direction	Clock Domain	Description
`tx_enh_frame[<n>-1:0]`	Output	`tx_clkout`	Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe.
`tx_enh_frame_diag_status[<n> 2-1:0]`	Input	`tx_clkout`	Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the frame generator block. This bus must be held constant for 5 clock cycles before and after the `tx_enh_frame` pulse. The following encodings are defined: Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational. Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
`tx_enh_frame_burst_en[<n>-1:0]`	Input	`tx_clkout`	If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each Metaframe. If the value of `tx_enh_frame_burst_en` is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts SKIP words as the payload of Metaframe. When `tx_enh_frame_burst_en` is 1, the frame generator reads data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the `tx_enh_frame` pulse.
`rx_enh_frame[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates the beginning of a new received Metaframe. This signal is pulse stretched.
`rx_enh_frame_lock[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched.
`rx_enh_frame_diag_status[2 <n>-1:0]`	Output	`rx_clkout`	Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined: Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational. Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
`rx_enh_crc32_err[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates a CRC error in the current Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles.

Table 53. 10GBASE-R BER Checker
Name	Direction	Clock Domain	Description
`rx_enh_highber[<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates a bit error rate that is greater than 10 ^-4. For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs. This signal gets asserted for 2 to 3 clock cycles.
`rx_enh_highber_clr_cnt[<n>-1:0]`	Input	`rx_clkout`	When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state.
`rx_enh_clr_errblk_count[<n>-1:0]` (10GBASE-R and FEC)	Input	`rx_clkout`	When asserted the error block counter resets to 0. Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the `RX_E` state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block.

Table 54. Block Synchronizer
Name	Direction	Clock Domain	Description
`rx_enh_blk_lock<n>-1:0]`	Output	`rx_clkout`	When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for 10GBASE-R and Interlaken.

Table 55. Gearbox
Name	Direction	Clock Domain	Description
`rx_bitslip[<n>-1:0]`	Input	`rx_clkout`	The `rx_parallel_data` slips 1 bit for every positive edge of the `rx_bitslip` input. Keep the minimum interval between `rx_bitslip` pulses to at least 20 cycles. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.
`tx_enh_bitslip[<n>-1:0]`	Input	`rx_clkout`	The value of this signal controls the number of bits to slip the `tx_parallel_data` before passing to the PMA.

Table 56. KR-FEC
Name	Direction	Clock Domain	Description
`tx_enh_frame[<n>-1:0]`	Output	`tx_clkout`	Asynchronous status flag output of TX KR-FEC that signifies the beginning of generated KR FEC frame
`rx_enh_frame[<n>-1:0]`	Output	`rx_clkout`	Asynchronous status flag output of RX KR-FEC that signifies the beginning of received KR FEC frame
`rx_enh_frame_diag_status`	Output	`rx_clkout`	Asynchronous status flag output of RX KR-FEC that indicates the status of the current received frame. 00: No error 01: Correctable Error 10: Un-correctale error 11: Reset condition/pre-lock condition

2.4.9.1. Enhanced PCS TX and RX Control Ports

This section describes the tx_control and rx_control bit encodings for different protocol configurations.

When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port. For example: It appears as unused_tx_control/ unused_rx_control port.

Enhanced PCS TX Control Port Bit Encodings

Table 57. Bit Encodings for Interlaken
Name	Bit	Functionality	Description
`tx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[2]	Inversion control	A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity.
	[7:3]	Unused
	[8]	Insert synchronous header error or CRC32	You can use this bit to insert synchronous header error or CRC32 errors. The functionality is similar to `tx_err_ins`. Refer to `tx_err_ins` signal description for more details.
	[17:9]	Unused

Table 58. Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Name	Bit	Functionality
`tx_control`	[0]	XGMII control signal for `parallel_data[7:0]`
	[1]	XGMII control signal for `parallel_data[15:8]`
	[2]	XGMII control signal for `parallel_data[23:16]`
	[3]	XGMII control signal for `parallel_data[31:24]`
	[4]	XGMII control signal for `parallel_data[39:32]`
	[5]	XGMII control signal for `parallel_data[47:40]`
	[6]	XGMII control signal for `parallel_data[55:48]`
	[7]	XGMII control signal for `parallel_data[63:56]`
	[17:8]	Unused

Table 59. Bit Encodings for Basic Single Width ModeFor basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name	Bit	Functionality	Description
`tx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
`tx_control`	[17:2]	Unused

Table 60. Bit Encodings for Basic Double Width ModeFor basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.
Name	Bit	Functionality	Description
`tx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[8:2]	Unused
	[10:9]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[17:11]	Unused

Table 61. Bit Encodings for Basic ModeIn this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name	Bit	Functionality	Description
`tx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
`tx_control`	[2]	Inversion control	A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.

Enhanced PCS RX Control Port Bit Encodings

Table 62. Bit Encodings for Interlaken
Name	Bit	Functionality	Description
`rx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[2]	Inversion control	A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity. In the current implementation, this bit is always tied logic low (1'b0).
	[3]	Payload word location	A logic high (1'b1) indicates the payload word location in a metaframe.
	[4]	Synchronization word location	A logic high (1'b1) indicates the synchronization word location in a metaframe.
	[5]	Scrambler state word location	A logic high (1'b1) indicates the scrambler word location in a metaframe.
	[6]	SKIP word location	A logic high (1'b1) indicates the SKIP word location in a metaframe.
	[7]	Diagnostic word location	A logic high (1'b1) indicates the diagnostic word location in a metaframe.
	[8]	Synchronization header error, metaframe error, or CRC32 error status	A logic high (1'b1) indicates synchronization header error, metaframe error, or CRC32 error status.
	[9]	Block lock and frame lock status	A logic high (1'b1) indicates that block lock and frame lock have been achieved.
	[19:10]	Unused

Table 63. Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Name	Bit	Functionality
`rx_control`	[0]	XGMII control signal for `parallel_data[7:0]`
	[1]	XGMII control signal for `parallel_data[15:8]`
	[2]	XGMII control signal for `parallel_data[23:16]`
	[3]	XGMII control signal for `parallel_data[31:24]`
	[4]	XGMII control signal for `parallel_data[39:32]`
	[5]	XGMII control signal for `parallel_data[47:40]`
	[6]	XGMII control signal for `parallel_data[55:48]`
	[7]	XGMII control signal for `parallel_data[63:56]`
	[19:8]	Unused

Table 64. Bit Encodings for Basic Single Width ModeFor basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name	Bit	Functionality	Description
`rx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[7:2]	Unused
	[9:8]	Synchronous header error status	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[19:10]	Unused

Table 65. Bit Encodings for Basic Double Width ModeFor basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous header.
Name	Bit	Functionality	Description
`rx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[7:2]	Unused
	[8]	Synchronous header error status	Active-high status signal that indicates a synchronous header error.
	[9]	Block lock is achieved	Active-high status signal indicating when block lock is achieved.
	[11:10]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
	[17:12]	Unused
	[18]	Synchronous header error status	Active-high status signal that indicates a synchronous header error.
	[19]	Block lock is achieved	Active-high status signal indicating when Block Lock is achieved.

Table 66. Bit Encodings for Basic ModeIn this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name	Bit	Functionality	Description
`rx_control`	[1:0]	Synchronous header	The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
`rx_control`	[2]	Inversion control	A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.

2.4.10. Standard PCS Ports

Figure 25. Transceiver Channel using the Standard PCS PortsStandard PCS ports appear if either one of the transceiver configuration modes is selected that uses Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of those that uses Standard PCS.

In the following tables, the variables represent these parameters:

<n>—The number of lanes
<w>—The width of the interface
<d>—The serialization factor
<s>— The symbol size
<p>—The number of PLLs

Table 67. TX Standard PCS: Data, Control, and Clocks
Name	Direction	Clock Domain	Description
`tx_parallel_data[<n>128-1:0]`	Input	`tx_clkout`	TX parallel data input from the FPGA fabric to the TX PCS.
`unused_tx_parallel_data`	Input	`tx_clkout`	This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of `tx_parallel_data`. Connect all these bits to 0. If you do not connect the unused data bits to 0, then TX parallel data may not be serialized correctly by the Native PHY IP core.
`tx_coreclkin`	Input	Clock	The FPGA fabric clock. This clock drives the write port of the TX FIFO.
`tx_clkout`	Output	Clock	This is the parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configuration. This clocks the `tx_parallel_data` from the FPGA fabric to the TX PCS.

Table 68. RX Standard PCS: Data, Control, Status, and Clocks
Name	Direction	Clock Domain	Description
`rx_parallel_data[<n> 128-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	RX parallel data from the RX PCS to the FPGA fabric. For each 128-bit word of `rx_parallel_data`, the data bits correspond to `rx_parallel_data[7:0]` when 8B/10B decoder is enabled and `rx_parallel_data[9:0]` when 8B/10B decoder is disabled.
`unused_rx_parallel_data`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of `rx_parallel_data`. These outputs can be left floating.
`rx_clkout`	Output	Clock	The low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX Standard PCS.
`rx_coreclkin`	Input	Clock	RX parallel clock that drives the read side clock of the RX FIFO.

Table 69. Standard PCS FIFO
Name	Direction	Clock Domain	Description
`tx_std_pcfifo_full[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	Indicates when the standard TX FIFO is full.
`tx_std_pcfifo_empty[<n>-1:0]`	Output	Synchronous to the clock driving the write side of the FIFO (`tx_coreclkin` or `tx_clkout`)	Indicates when the standard TX FIFO is empty.
`rx_std_pcfifo_full[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	Indicates when the standard RX FIFO is full.
`rx_std_pcfifo_empty[<n>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	Indicates when the standard RX FIFO is empty.

Table 70. Rate Match FIFO
Name	Direction	Clock Domain	Description
`rx_std_rmfifo_full[<n>-1:0]`	Output	Asynchronous	Rate match FIFO full flag. When asserted the rate match FIFO is full. You must synchronize this signal. This port is only used for GigE mode.
`rx_std_rmfifo_empty[<n>-1:0]`	Output	Asynchronous	Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode.
`rx_rmfifostatus[<n>-1:0]`	Output	Asynchronous	Indicates FIFO status. The following encodings are defined: 2'b00: Normal operation 2'b01: Deletion, `rx_std_rmfifo_full = 1` 2'b10: Insertion, `rx_std_rmfifo_empty = 1` 2'b11: Full. `rx_rmfifostatus` is a part of `rx_parallel_data`. `rx_rmfifostatus` corresponds to `rx_parallel_data[14:13]`.

Table 71. 8B/10B Encoder and Decoder
Name	Direction	Clock Domain	Description
`tx_datak`	Input	tx_clkout	`tx_datak` is exposed if 8B/10B enabled and simplified data interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of `tx_parallel_data` is data. `tx_datak` is a part of `tx_parallel_data` when simplified data interface is not set.
`tx_forcedisp[<n>(<w>/<s>-1:0]`	Input	Asynchronous	This signal allows you to force the disparity of the 8B/10B encoder. When "1", forces the disparity of the output data to the value driven on `tx_dispval`. When "0", the current running disparity continues. `tx_forcedisp` is a part of `tx_parallel_data`. `tx_forcedisp` corresponds to `tx_parallel_data[9]`.
`tx_dispval[<n>(<w>/<s>-1:0]`	Input	Asynchronous	Specifies the disparity of the data. When 0, indicates positive disparity, and when 1, indicates negative disparity. `tx_dispval` is a part of `tx_parallel_data`. `tx_dispval` corresponds to `tx_dispval[10]`.
`rx_datak[<n><w>/<s>-1:0]`	Output	`rx_clkout`	`rx_datak` is exposed if 8B/10B is enabled and simplified data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of `rx_parallel_data` is data. `rx_datak` is a part of `rx_parallel_data` when simplified data interface is not set.
`rx_errdetect[<n><w>/<s>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	When asserted, indicates a code group violation detected on the received code group. Used along with `rx_disperr` signal to differentiate between code group violation and disparity errors. The following encodings are defined for `rx_errdetect/rx_disperr`: 2'b00: no error 2'b10: code group violation 2'b11: disparity error. `rx_errdetect` is a part of `rx_parallel_data`. For each 128-bit word, `rx_errdetect` corresponds to `rx_parallel_data[9]`.
`rx_disperr[<n><w>/<s>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	When asserted, indicates a disparity error on the received code group. `rx_disperr` is a part of `rx_parallel_data`. For each 128-bit word, `rx_disperr` corresponds to `rx_parallel_data[11]`.
`rx_runningdisp[<n><w>/<s>-1:0]`	Output	Synchronous to the clock driving the read side of the FIFO (`rx_coreclkin` or `rx_clkout`)	When high, indicates that `rx_parallel_data` was received with negative disparity. When low, indicates that `rx_parallel_data` was received with positive disparity. `rx_runningdisp` is a part of `rx_parallel_data`. For each 128 bit word, `rx_runningdisp` corresponds to `rx_parallel_data[15]`.
`rx_patterndetect[<n><w>/<s>-1:0]`	Output	Asynchronous	When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary. `rx_patterndetect` is a part of `rx_parallel_data`. For each 128-bit word, `rx_patterndetect` corresponds to `rx_parallel_data[12]`.
`rx_syncstatus[<n><w>/<s>-1:0]`	Output	Asynchronous	When asserted, indicates that the conditions required for synchronization are being met. `rx_syncstatus` is a part of `rx_parallel_data`. For each 128-bit word, `rx_syncstatus` corresponds to `rx_parallel_data[10]`.

Table 72. Word Aligner and Bitslip
Name	Direction	Clock Domain	Description
`tx_std_bitslipboundarysel[5 <n>-1:0]`	Input	Asynchronous	Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip.
`rx_std_bitslipboundarysel[5 <n>-1:0]`	Output	Asynchronous	This port is used in deterministic latency word aligner mode. This port reports the number of bits that the RX block slipped. This port values should be taken into consideration in either Deterministic Latency Mode or Manual Mode of Word Aligner.
`rx_std_wa_patternalign[<n>-1:0]`	Input	Synchronous to `rx_clkout`	Active when you place the word aligner in manual mode. In manual mode, you align words by asserting `rx_std_wa_patternalign`. When the PCS-PMA Interface width is 10 bits, `rx_std_wa_patternalign` is level sensitive. For all the other PCS-PMA Interface widths, `rx_std_wa_patternalign` is positive edge sensitive. You can use this port only when the word aligner is configured in manual or deterministic latency mode. When the word aligner is in manual mode, and the PCS-PMA interface width is 10 bits, this is a level sensitive signal. In this case, the word aligner monitors the input data for the word alignment pattern, and updates the word boundary when it finds the alignment pattern. For all other PCS-PMA interface widths, this signal is edge sensitive.This signal is internally synchronized inside the PCS using the PCS parallel clock and should be asserted for at least 2 clock cycles to allow synchronization.
`rx_std_wa_a1a2size[<n>-1:0]`	Input	Asynchronous	Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits.
`rx_bitslip[<n>-1:0]`	Input	Asynchronous	Used when word aligner mode is bitslip mode. When the Word Aligner is in either Manual (PLD controlled), Synchronous State Machine or Deterministic Latency ,the `rx_bitslip signal` is not valid and should be tied to 0. For every rising edge of the `rx_std_bitslip` signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data.

Table 73. Bit Reversal and Polarity Inversion
Name	Direction	Clock Domain	Description
`rx_std_byterev_ena[<n>-1:0]`	Input	Asynchronous	This control signal is available when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface. Used if the MSB and LSB of the transmitted data are erroneously swapped.
`rx_std_bitrev_ena[<n>-1:0]`	Input	Asynchronous	When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.
`tx_polinv[<n>-1:0]`	Input	Asynchronous	When asserted, the TX polarity bit is inverted. Only active when TX bit polarity inversion is enabled.
`rx_polinv[<n>-1:0]`	Input	Asynchronous	When asserted, the RX polarity bit is inverted. Only active when RX bit polarity inversion is enabled.
`rx_std_signaldetect[<n>-1:0]`	Output	Asynchronous	When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime Settings File (.qsf) assignment. This signal is required for the PCI Express*, SATA and SAS protocols.

2.4.11. IP Core File Locations

When you generate your Transceiver Native PHY IP, the Quartus^® Prime software generates the HDL files that define your instance of the IP. In addition, the Quartus Prime software generates an example Tcl script to compile and simulate your design in the ModelSim* simulator. It also generates simulation scripts for Synopsys* VCS, Aldec* Active-HDL, Aldec Riviera-Pro, and Cadence* Incisive Enterprise.

Figure 26. Directory Structure for Generated Files

The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.

Table 74. Transceiver Native PHY Files and Directories
File Name	Description
<project_dir>	The top-level project directory.
<your_ip_name> .v or .vhd	The top-level design file.
<your_ip_name> .qip	A list of all files necessary for Quartus Prime compilation.
<your_ip_name> .bsf	A Block Symbol File (.bsf) for your Transceiver Native PHY instance.
<project_dir>/<your_ip_name>/	The directory that stores the HDL files that define the Transceiver Native PHY IP.
<project_dir>/sim	The simulation directory.
<project_dir>/sim/aldec	Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence	Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor	Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys	Simulation files for Synopsys simulation tools.
<project_dir>/synth	The directory that stores files used for synthesis.

The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:

ModelSim SE
Synopsys VCS MX
Cadence NCSim

If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus Prime software is in VHDL. All the underlying files are written in Verilog or SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-language simulator.

For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim and QuestaSim Support chapter in volume 3 of the Quartus Prime Handbook.

The Transceiver Native PHY IP cores do not support the NativeLink feature in the Quartus Prime software.

2.4.12. Unused Transceiver RX Channels

To prevent performance degradation of unused transceiver RX channels over time, the following assignments must be added to an Arria^® 10 device QSF. You can either use a global assignment or per-pin assignments.

set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to <pin_name (U34, for example)>

An example of a <pin_name> is U34, not PIN_U34.

When you perform this procedure, the Intel^® Quartus^® Prime software instantiates the clock data recovery (CDR) PLL corresponding to each unused receiver channel. The CDR uses CLKUSR as reference clock and is configured to run at 1 Gbps. To use CLKUSR as reference clock, the pin must be assigned a 100- to 125 MHz clock. When you implement these assignments, it causes a power consumption increase per receiver channel. Please contact your local support center for details.

2.4.13. Unsupported Features

Native PHY should not be included in QXP.

2.5. Interlaken

Interlaken is a scalable, channelized chip-to-chip interconnect protocol.

The key advantages of Interlaken are scalability and low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking. Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst semantics include integrity checking and per logical channel flow control.

The Interlaken interface is supported with 1 to 48 lanes running at data rates up to 12.5 Gbps per lane on Arria 10 devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.

Arria 10 devices provide three preset variations for Interlaken in the Arria 10 Transceiver Native PHY IP Parameter Editor:

Interlaken 10x12.5 Gbps
Interlaken 1x6.25 Gbps
Interlaken 6x10.3 Gbps

Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of 32, 40, or 64 bits.

Figure 27. Transceiver Channel Datapath and Clocking for InterlakenThis figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.

2.5.1. Metaframe Format and Framing Layer Control Word

The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words. However, for stability and performance, Intel recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times. The payload of a metaframe could be pure data payload and a Burst/Idle control word from the MAC layer.

Figure 28. Framing Layer Metaframe Format

The framing control words include:

Synchronization (SYNC)—for frame delineation and lane alignment (deskew)
Scrambler State (SCRM)—to synchronize the scrambler
Skip (SKIP)—for clock compensation in a repeater
Diagnostic (DIAG)—provides per-lane error check and optional status message

To form a metaframe, the Enhanced PCS frame generator inserts the framing control words and encapsulates the control and data words read from the TX FIFO as the metaframe payload.

Figure 29. Interlaken Synchronization and Scrambler State Words Format

Figure 30. Interlaken Skip Word Format

The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is defined by the Interlaken specification as:

Bit 1 (Bit 33): Lane health
- 1: Lane is healthy
- 0: Lane is not healthy
Bit 0 (Bit 32): Link health
- 1: Link is healthy
- 0: Link is not healthy

The tx_enh_frame_diag_status[1:0] input from the FPGA fabric is inserted into the Status field each time a DIAG word is created by the framing generator.

Figure 31. Interlaken Diagnostic Word

2.5.2. Interlaken Configuration Clocking and Bonding

The Arria 10 Interlaken PHY layer solution is scalable and has flexible data rates. You can implement a single lane link or bond up to 48 lanes together. You can choose a lane data rate up to 17.4 Gbps for GX devices and 25.8 Gbps for GT devices. You can also choose between different reference clock frequencies, depending on the PLL used to clock the transceiver. Refer to the Arria 10 Device Datasheet for the minimum and maximum data rates that Arria 10 transceivers can support at different speed grades.

You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX PLL has better jitter performance compared to an fPLL. You can use the CMU PLL to clock only the non-bonded Interlaken transmit channels. However, if you use the CMU PLL, you lose one RX transceiver channel.

For the multi-lane Interlaken interface, TX channels are usually bonded together to minimize the transmit skew between all bonded channels. Currently, xN bonding and PLL feedback compensation bonding schemes are available to support a multi-lane Interlaken implementation. If the system tolerates higher channel-to-channel skew, you can choose to not bond the TX channels.

To implement bonded multi-channel Interlaken, all channels must be placed contiguously. The channels may all be placed in one bank (if not greater than six lanes) or they may span several banks.

2.5.2.1. xN Clock Bonding Scenario

The following figure shows a xN bonding example supporting 10 lanes. Each lane is running at 12.5 Gbps. The first six TX channels reside in one transceiver bank and the other four TX channels reside in the adjacent transceiver bank. The ATX PLL provides the serial clock to the master CGB. The CGB then provides parallel and serial clocks to all of the TX channels inside the same bank and other banks through the xN clock network.

Because of xN clock network skew, the maximum achievable data rate decreases when TX channels span several transceiver banks.

Figure 32. 10X12.5 Gbps xN Bonding

2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine

The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port signals are provided to the FPGA fabric. Connect these signals to the MAC layer as required by the protocol. Based on these FIFO status and control signals, you can implement the multi-lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block.

Note: You must also implement the soft bonding logic to control the transceiver TX FIFO block.

2.5.2.2.1. TX FIFO Soft Bonding

The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable) by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull, tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted high, the frame generator reads data from the TX FIFO.

A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding. The following figure shows the state of the pre-fill process.

Figure 33. TX Soft Bonding Flow

The following figure shows that after deasserting tx_digitalreset, TX soft bonding logic starts filling the TX FIFO until all lanes are full.

Figure 34. TX FIFO Pre-fill (6-lane Interface)

After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat the TX FIFO pre-fill stage.

For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You can begin sending an Interlaken word to the TX FIFO after tx_digitalreset deasserts.

The following figure shows the MAC layer sending valid data to the Native PHY after the pre-fill stage. tx_enh_frame_burst_en is asserted, allowing the frame generator to read data from the TX FIFO. The TX MAC layer can now control tx_enh_data_valid and write data to the TX FIFO based on the FIFO status signals.

Figure 35. MAC Sending Valid Data (6-lane Interface)

2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine

Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the transmitter of the link partner, PCB, medium, and local receiver PMA.

Implement a multi-lane alignment deskew state machine to control the RX FIFO operation based on available RX FIFO status flags and control signals.

Figure 36. State Flow of the RX FIFO Deskew

Each lane's rx_enh_fifo_rd_en should remain deasserted before the RX FIFO deskew is completed. After frame lock is achieved (indicated by the assertion of rx_enh_frame_lock; this signal is not shown in the above state flow), data is written into the RX FIFO after the first alignment word (SYNC word) is found on that channel. Accordingly, the RX FIFO partially empty flag (rx_enh_fifo_pempty) of that channel is asserted. The state machine monitors the rx_enh_fifo_pempty and rx_enh_fifo_pfull signals of all channels. If the rx_enh_fifo_pempty signals from all channels deassert before any channels rx_enh_fifo_pfull assert, which implies the SYNC word has been found on all lanes of the link, the MAC layer can start reading from all the RX FIFO by asserting rx_enh_fifo_rd_en simultaneously. Otherwise, if the rx_enh_fifo_pfull signal of any channel asserts high before the rx_enh_fifo_pempty signals deassertion on all channels, the state machine needs to flush the RX FIFO by asserting rx_enh_fifo_align_clr high for 4 cycles and repeating the soft deskew process.

The following figure shows one RX deskew scenario. In this scenario, all of the RX FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted. This indicates the deskew is successful and the FPGA fabric starts reading data from the RX FIFO.

Figure 37. RX FIFO Deskew

2.5.3. How to Implement Interlaken in Arria 10 Transceivers

You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the Interlaken protocol PHY layer.

Arria 10 devices provide three preset variations for Interlaken in the IP Parameter Editor:

Interlaken 10x12.5 Gbps
Interlaken 1x6.25 Gbps
Interlaken 6x10.3 Gbps

Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog (Installed IP > Library > Interface Protocols > Transceiver PHY > Arria 10 Transceiver Native PHY).
Refer to Select and Instantiate the PHY IP Core for more details.
Select Interlaken from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Interlaken Transceiver Configuration Rules. Or you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
Click Generate to generate the Native PHY IP (this is your RTL file).

Figure 38. Signals and Ports of Native PHY IP for Interlaken
Configure and instantiate your PLL.
Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation.
Connect the Native PHY IP to the PLL IP and the reset controller.

Figure 39. Connection Guidelines for an Interlaken PHY Design
This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel^® FPGA Wiki website.

For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in the design example. The white blocks are your test logic or MAC layer logic.
Simulate your design to verify its functionality.

Figure 40. 24 Lanes Bonded Interlaken Link, TX Direction To show more details, three different time segments are shown with the same zoom level.

24 lanes bonded Interlaken link, TX direction

Figure 41. 24 Lanes Bonded Interlaken Link, RX Direction To show more details, three different time segments are shown with different zoom level.

2.5.4. Design Example

Intel provides a PHY layer-only design example to help you integrate an Interlaken PHY into your complete design.

The TX soft bonding logic is included in the design example. Intel recommends that you integrate this module into your design.

The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design Examples Wiki page.

Note: The design examples on the Wiki page provide useful guidance for developing your own designs, but they are not guaranteed by Intel^® . Use them with caution.

2.5.5. Native PHY IP Parameter Settings for Interlaken

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Table 75. General and Datapath Parameters
Parameter	Value
Message level for rule violations	error warning
Transceiver configuration rules	Interlaken
PMA configuration rules	basic
Transceiver mode	TX / RX Duplex TX Simplex RX Simplex
Number of data channels	1 to 96
Data rate	Up to 17.4 Gbps for GX devices (Depending on Enhanced PCS to PMA interface width selection)
Enable datapath and interface reconfiguration	On / Off
Enable simplified data interface	On / Off
Provide separate interface for each channel	On / Off

Table 76. TX PMA Parameters
Parameter	Value
TX channel bonding mode	Not bonded PMA-only bonding PMA and PCS bonding
PCS TX channel bonding master	If TX channel bonding mode is set to PMA and PCS bonding, then: Auto, 0, 1, 2, 3 through [Number of data channels – 1]
Actual PCS TX channel bonding master	If TX channel bonding mode is set to PMA and PCS bonding, then: 0, 1, 2, 3 through [Number of data channels – 1]
TX local clock division factor	If TX channel bonding mode is not bonded, then: 1, 2, 4, 8
Number of TX PLL clock inputs per channel	If TX channel bonding mode is not bonded, then: 1, 2, 3, 4
Initial TX PLL clock input selection	0
Enable tx_pma_clkout port	On / Off
Enable tx_pma_div_clkout port	On / Off
tx_pma_div_clkout division factor	When Enable tx_pma_div_clkout port is On, then: Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port	On / Off
Enable tx_pma_qpipullup port (QPI)	Off
Enable tx_pma_qpipulldn port (QPI)	Off
Enable tx_pma_txdetectrx port (QPI)	Off
Enable tx_pma_rxfound port (QPI)	Off
Enable rx_seriallpbken port	On / Off

Table 77. RX PMA Parameters
Parameter	Value
Number of CDR reference clocks	1 to 5
Selected CDR reference clock	0 to 4
Selected CDR reference clock frequency	Select legal range defined by the Quartus Prime software
PPM detector threshold	100, 300, 500, 1000
CTLE adaptation mode	manual,
DFE adaptation mode	adaptation enabled, manual, disabled
Number of fixed dfe taps	3, 7, 11
Enable rx_pma_clkout port	On / Off
Enable rx_pma_div_clkout port	On / Off
rx_pma_div_clkout division factor	When Enable rx_pma_div_clkout port is On, then: Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port	On / Off
Enable rx_pma_qpipulldn port (QPI)	Off
Enable rx_is_lockedtodata port	On / Off
Enable rx_is_lockedtoref port	On / Off
Enable rx_set_locktodata and rx_set_locktoref ports	On / Off
Enable rx_seriallpbken port	On / Off
Enable PRBS verifier control and status ports	On / Off

Table 78. Enhanced PCS Parameters
Parameter	Value
Enhanced PCS / PMA interface width	32, 40, 64
FPGA fabric / Enhanced PCS interface width	67
Enable 'Enhanced PCS' low latency mode	Allowed when the PMA interface width is 32 and preset variations for data rate is 10.3125 Gbps or 6.25 Gbps; otherwise Off
Enable RX/TX FIFO double-width mode	Off
TX FIFO mode	Interlaken
TX FIFO partially full threshold	8 to 15
TX FIFO partially empty threshold	1 to 8
Enable tx_enh_fifo_full port	On / Off
Enable tx_enh_fifo_pfull port	On / Off
Enable tx_enh_fifo_empty port	On / Off
Enable tx_enh_fifo_pempty port	On / Off
RX FIFO mode	Interlaken
RX FIFO partially full threshold	from 10-29 (no less than pempty_threshold+8)
RX FIFO partially empty threshold	2 to 10
Enable RX FIFO alignment word deletion (Interlaken)	On / Off
Enable RX FIFO control word deletion (Interlaken)	On / Off
Enable rx_enh_data_valid port	On / Off
Enable rx_enh_fifo_full port	On / Off
Enable rx_enh_fifo_pfull port	On / Off
Enable rx_enh_fifo_empty port	On / Off
Enable rx_enh_fifo_pempty port	On / Off
Enable rx_enh_fifo_del port (10GBASE-R)	Off
Enable rx_enh_fifo_insert port (10GBASE-R)	Off
Enable rx_enh_fifo_rd_en port	On
Enable rx_enh_fifo_align_val port (Interlaken)	On / Off
Enable rx_enh_fifo_align_clr port (Interlaken)	On

Table 79. Interlaken Frame Generator Parameters
Parameter	Value
Enable Interlaken frame generator	On
Frame generator metaframe length	5 to 8192 (Intel recommends a minimum metaframe length of 128)
Enable frame generator burst control	On
Enable tx_enh_frame port	On
Enable tx_enh_frame_diag_status port	On
Enable tx_enh_frame_burst_en port	On

Table 80. Interlaken Frame Synchronizer Parameters
Parameter	Value
Enable Interlaken frame synchronizer	On
Frame synchronizer metaframe length	5 to 8192 (Intel recommends a minimum metaframe length of 128)
Enable rx_enh_frame port	On
Enable rx_enh_frame_lock port	On / Off
Enable rx_enh_frame_diag_status port	On / Off

Table 81. Interlaken CRC-32 Generator and Checker Parameters
Parameter	Value
Enable Interlaken TX CRC-32 generator	On
Enable Interlaken TX CRC-32 generator error insertion	On / Off
Enable Interlaken RX CRC-32 checker	On
Enable rx_enh_crc32_err port	On / Off

Table 82. Scrambler and Descrambler Parameters
Parameter	Value
Enable TX scrambler (10GBASE-R / Interlaken)	On
TX scrambler seed (10GBASE-R / Interlaken)	0x1 to 0x3FFFFFFFFFFFFFF
Enable RX descrambler (10GBASE-R / Interlaken)	On

Table 83. Interlaken Disparity Generator and Checker Parameters
Parameter	Value
Enable Interlaken TX disparity generator	On
Enable Interlaken RX disparity checker	On
Enable Interlaken TX random disparity bit	On / Off

Table 84. Block Sync Parameters
Parameter	Value
Enable RX block synchronizer	On
Enable rx_enh_blk_lock port	On / Off

Table 85. Gearbox Parameters
Parameter	Value
Enable TX data bitslip	Off
Enable TX data polarity inversion	On / Off
Enable RX data bitslip	Off
Enable RX data polarity inversion	On / Off
Enable tx_enh_bitslip port	Off
Enable rx_bitslip port	Off

Table 86. Dynamic Reconfiguration Parameters
Parameter	Value
Enable dynamic reconfiguration	On / Off
Share reconfiguration interface	On / Off
Enable Native PHY Debug Master Endpoint	On / Off
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE	On / Off
Enable capability registers	On / Off
Set user-defined IP identifier:	0 to 255
Enable control and status registers	On / Off
Enable prbs soft accumulators	On / Off

Table 87. Configuration Files Parameters
Parameter	Value
Configuration file prefix	—
Generate SystemVerilog package file	On / Off
Generate C header file	On / Off
Generate MIF (Memory Initialization File)	On / Off
Include PMA analog settings in configuration files	On / Off

Table 88. Configuration Profiles Parameters
Parameter	Value
Enable multiple reconfiguration profiles	On / Off
Enable embedded reconfiguration streamer	On / Off
Generate reduced reconfiguration files	On / Off
Number of reconfiguration profiles	1 to 8
Selected reconfiguration profile	1 to 7

2.6. Ethernet

The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates. The 1G/10GbE and 10GBASE-KR PHY IP Core enables Ethernet connectivity at 1 Gbps and 10 Gbps over backplanes. The 10GBASE-KR PHY IP is also known as the Backplane Ethernet PHY IP. It includes link training and auto negotiation to support the IEEE Backplane Ethernet standard.

Data Rate	Transceiver Configuration Rule/IP
1G	Gigabit Ethernet Gigabit Ethernet 1588
10G	10GBASE-R 10GBASE-R 1588 10GBASE-R with KR FEC 10GBASE-KR PHY IP
1G/10G	1G/10G Ethernet PHY IP

2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2

Gigabit Ethernet (GbE) is a high-speed local area network technology that provides data transfer rates of about 1 Gbps. GbE builds on top of the ethernet protocol, but increases speed tenfold over Fast Ethernet. IEEE 802.3 defines GbE as an intermediate (or transition) layer that interfaces various physical media with the media access control (MAC) in a Gigabit Ethernet system. Gigabit Ethernet PHY shields the MAC layer from the specific nature of the underlying medium and is divided into three sub-layers shown in the following figure.

Figure 42. GbE PHY Connection to IEEE 802.3 MAC and RS

Figure 43. Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2

Note: The Native PHY only supports basic PCS functions. The Native PHY does not support auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in the FPGA fabric or external circuits.

GbE with IEEE 1588v2

GbE with IEEE 1588v2 provides a standard method to synchronize devices on a network with submicrosecond precision. To improve performance, the protocol synchronizes slave clocks to a master clock so that events and time stamps are synchronized in all devices. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.

The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.

2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2

The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is sent to the PMA.

The IEEE 802.3 specification requires GbE to transmit Idle ordered sets (/I/) continuously and repetitively whenever the gigabit media-independent interface (GMII) is Idle. This transmission ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted.

For the GbE protocol, the transmitter replaces any /Dx.y/ following a /K28.5/ comma with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity. The exception is when the data following the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the beginning running disparity immediately preceding transmission of the Idle code. This sequence ensures a negative running disparity at the end of an Idle ordered set. A /Kx.y/ following a /K28.5/ does not get replaced.

Note: /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for I1 and I2 ordered sets). D21.5 (/C1/) is not replaced.

Figure 44. Idle Ordered-Set Generation Example

2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2

After deassertion of tx_digitalreset, the transmitters automatically transmit at least three /K28.5/ comma code groups before transmitting user data on the tx_parallel_data port. This transmission could affect the synchronization state machine behavior at the receiver.

Depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /Dx.y/ code groups transmitted between the last of the three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the synchronization sequence. If there is an even number of /Dx.y/code groups received between these two /K28.5/ code groups, the first /K28.5/ code group of the synchronization sequence begins at an odd code group boundary. The synchronization state machine treats this as an error condition and goes into the loss of synchronization state.

Figure 45. Reset Condition

2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2

The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in automatic synchronization state machine mode. The Intel^® Quartus^® Prime Pro Edition software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered sets.

The GbE PHY IP core signals receiver synchronization status on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects three invalid code groups separated by less than three valid code groups or when it is reset.

Table 89. Synchronization State Machine Parameter Settings for GbE
Synchronization State Machine Parameter	Setting
Number of word alignment patterns to achieve sync	3
Number of invalid data words to lose sync	3
Number of valid data words to decrement error count	3

The following figure shows rx_syncstatus high when three consecutive ordered sets are sent through rx_parallel_data.

Figure 46. rx_syncstatus High

2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2

The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data value and 1-bit control value as output.

Figure 47. Decoding for GbEDx.y(0x8d), Dx.y(0xa4), K28.5(0xbc), and Dx.y(0x50) are received at rx_parallel_data. /K28.5/ is set as the word alignment pattern. rx_patterndetect goes high whenever it detects /K28.5/(0xbc). rx_datak is high when bc is received, indicating that the decoded word is a control word. Otherwise, rx_datak is low. rx_runningdisp is high for 0x8d, indicating that the decoded word has negative disparity and 0xa4 has positive disparity.

2.6.1.4. Rate Match FIFO for GbE

The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125 MHz ± 100 ppm difference.

Note: 200 ppm total is only true if calculated as (125 MHz + 100 ppm) - (125 MHz - 100 ppm) = 200 ppm. By contrast, (125 MHz + 0 ppm) - (125 MHz - 200 ppm) is out of specification.

The GbE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps (IPG) adhering to the rules listed in the IEEE 802.3-2008 specification.

The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate matcher deletes or inserts both symbols /K28.5/ and /D16.2/ of the /I2/ ordered sets as a pair in the operation to prevent the rate match FIFO from overflowing or underflowing. The rate match operation can insert or delete as many /I2/ ordered sets as necessary.

The following figure shows a rate match deletion operation example where three symbols must be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes two /I2/ ordered sets (four symbols deleted).

Figure 48. Rate Match FIFO Deletion

The following figure shows an example of rate match FIFO insertion in the case where one symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered sets, it inserts one /I2/ ordered set (two symbols inserted).

Figure 49. Rate Match FIFO Insertion

rx_std_rmfifo_full and rx_std_rmfifo_empty are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions.

The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts the rx_std_rmfifo_full flag for at least two recovered clock cycles to indicate rate match FIFO full. The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer.

Figure 50. Rate Match FIFO Full Condition

The rate match FIFO does not insert code groups to overcome the FIFO empty condition. It asserts the rx_std_rmfifo_empty flag for at least two recovered clock cycles to indicate that the rate match FIFO is empty. The following figure shows the rate match FIFO empty condition when the read pointer is faster than the write pointer.

Figure 51. Rate Match FIFO Empty Condition

In the case of rate match FIFO full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver PCS blocks.

2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.

Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core.
Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
Use the parameter values in the tables in Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. Use the GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE 1588. You can then modify the setting to meet your specific requirements.
Click Generate to generate the Native PHY IP core top-level RTL file.

Figure 52. Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2Generating the IP core creates signals and ports based on your parameter settings.
Instantiate and configure your PLL.
Instantiate a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP core.
Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in the figure below to connect the ports.

Figure 53. Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design
Simulate your design to verify its functionality.

2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Table 90. General and Datapath OptionsThe first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Parameter	Value
Message level for rule violations	error warning
Transceiver configuration rules	GbE (for GbE) GbE 1588 (for GbE with IEEE 1588v2)
Transceiver mode	TX/RX Duplex TX Simplex RX Simplex
Number of data channels	1 to 96
Data rate	1250 Mbps
Enable datapath and interface reconfiguration	On/Off
Enable simplified data interface	On/Off

Table 91. TX PMA Parameters
Parameter	Value
TX channel bonding mode	Not bonded
TX local clock division factor	1, 2, 4, 8
Number of TX PLL clock inputs per channel	1, 2, 3, 4
Initial TX PLL clock input selection	0 to 3
Enable tx_pma_clkout port	On/Off
Enable tx_pma_div_clkout port	On/Off
tx_pma_div_clkout division factor	Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port	On/Off
Enable tx_pma_qpipullup port (QPI)	On/Off
Enable tx_pma_qpipulldn port (QPI)	On/Off
Enable tx_pma_txdetectrx port (QPI)	On/Off
Enable tx_pma_rxfound port (QPI)	On/Off
Enable rx_seriallpbken port	On/Off

Table 92. RX PMA Parameters
Parameter	Value
Number of CDR reference Clocks	1 to 5
Selected CDR reference clock	0 to 4
Selected CDR reference clock frequency	Select legal range defined by the Quartus Prime software
PPM detector threshold	100, 300, 500, 1000
CTLE adaptation mode	manual
DFE adaptation mode	disabled
Number of fixed dfe taps	N/A
Enable rx_pma_clkout port	On/Off
Enable rx_pma_div_clkout port	On/Off
rx_pma_div_clkout division factor	Disabled, 1, 2, 33, 40, 66
Enable rx_pma_iqtxrx_clkout port	On/Off
Enable rx_pma_clkslip port	On/Off
Enable rx_pma_qpipulldn port (QPI)	Off
Enable rx_is_lockedtodata port	On/Off
Enable rx_is_lockedtoref port	On/Off
Enable rx_set_locktodata and rx_set_locktoref ports	On/Off
Enable rx_seriallpbken port	On/Off
Enable PRBS verifier control and status ports	On/Off

Table 93. Standard PCS Parameters
Parameters	Value
Standard PCS / PMA interface width	10
FPGA fabric / Standard TX PCS interface width	8
FPGA fabric / Standard RX PCS interface width	8
Enable Standard PCS low latency mode	Off
TX FIFO mode	low latency (for GbE) register_fifo (for GbE with IEEE 1588v2)
RX FIFO mode	low latency (for GbE) register_fifo (for GbE with IEEE 1588v2)
Enable tx_std_pcfifo_full port	On/Off
Enable tx_std_pcfifo_empty port	On/Off
Enable rx_std_pcfifo_full port	On/Off
Enable rx_std_pcfifo_empty port	On/Off
TX byte serializer mode	Disabled
RX byte deserializer mode	Disabled
Enable TX 8B/10B encoder	On
Enable TX 8B/10B disparity control	On/Off
Enable RX 8B/10B decoder	On
RX rate match FIFO mode	gige (for GbE) disabled (for GbE with IEEE 1588v2)
RX rate match insert / delete -ve pattern (hex)	`0x000ab683` (/K28.5/D2.2/) (for GbE) `0x00000000` (disabled for GbE with IEEE 1588v2)
RX rate match insert / delete +ve pattern (hex)	`0x000a257c` (/K28.5/D16.2/) (for GbE) `0x00000000` (disabled for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_full port	On/Off (option disabled for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_empty port	On/Off (option disabled for GbE with IEEE 1588v2)
*PCI Express Gen3 rate match FIFO mode**	Bypass
Enable TX bit slip	Off
Enable tx_std_bitslipboundarysel port	On/Off
RX word aligner mode	Synchronous state machine
RX word aligner pattern length	7
RX word aligner pattern (hex)	`0x000000000000007c` (Comma) (for 7-bit aligner pattern length), `0x000000000000017c` (/K28.5/) (for 10-bit aligner pattern length)
Number of word alignment patterns to achieve sync	3
Number of invalid data words to lose sync	3
Number of valid data words to decrement error count	3
Enable fast sync status reporting for deterministic latency SM	On/Off
Enable rx_std_wa_patternalign port	Off
Enable rx_std_wa_a1a2size port	Off
Enable rx_std_bitslipboundarysel port	Off
Enable rx_bitslip port	Off
Enable TX bit reversal	Off
Enable TX byte reversal	Off
Enable TX polarity inversion	On/Off
Enable tx_polinv port	On/Off
Enable RX bit reversal	Off
Enable rx_std_bitrev_ena port	Off
Enable RX byte reversal	Off
Enable rx_std_byterev_ena port	Off
Enable RX polarity inversion	On/Off
Enable rx_polinv port	On/Off
Enable rx_std_signaldetect port	On/Off
All options under *PCIe Ports**	Off

2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants

10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Arria 10 transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2, and with forward error correction (FEC).

The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) that interfaces with the Media Access Control (MAC), which has the optional Reconciliation Sub-layer (RS).

Figure 54. 10GBASE-R PHY as Part of the IEEE802.3-2008 Open System Interconnection (OSI)

10GBASE-R is a single-channel protocol that runs independently. You can configure the transceivers to implement 10GBASE-R PHY functionality by using the presets of the Native PHY IP. The 10GBASE-R PHY IP is compatible with the 10-Gbps Ethernet MAC Intel^® FPGA IP Core Function. The complete PCS and PHY solutions can be used to interface with a third-party PHY MAC layer as well.

The following 10GBASE-R variants area available from presets:

10GBASE-R
10GBASE-R Low Latency
10GBASE-R Register Mode
10GBASE-R w/ KR-FEC

Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core.

Figure 55. Transceiver Channel Datapath and Clocking for 10GBASE-R

10GBASE-R with IEEE 1588v2

When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and RX FIFO are set to register mode. The output clock frequency of tx_clkout and rx_clkout to the FPGA fabric is based on the PCS-PMA interface width. For example, if the PCS-PMA interface is 40-bit, tx_clkout and rx_clkout run at 10.3125 Gbps/40-bit = 257.8125 MHz.

The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data is running at 156.25 MHz interfacing with the MAC layer.

The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10 transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as:

Distributed systems in telecommunications
Power generation and distribution
Industrial automation
Robotics
Data acquisition
Test equipment
Measurement

The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.

Figure 56. Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2

10GBASE-R with FEC

Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR PHY. This provides a coding gain to increase the link budget and BER performance on a broader set of backplane channels as defined in Clause 69. It provides additional margin to account for variations in manufacturing and environment conditions. The additional TX FEC sublayer:

Receives data from the TX PCS
Transcodes 64b/66b words
Performs encoding/framing
Scrambles and sends the FEC data to the PMA

The RX FEC sublayer:

Receives data from the PMA
Performs descrambling
Achieves FEC framing synchronization
Decodes and corrects data where necessary and possible
Recodes 64b/66b words and sends the data to the PCS

The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS and PMA sublayers of the 10GBASE-R physical layer.

Figure 57. Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC

The CMU PLL or the ATX PLLs generate the TX high speed serial clock.

Figure 58. Clock Generation and Distribution for 10GBASE-R with FEC SupportExample using a 64-bit PCS-PMA interface width.

2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R

The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit wide control character. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz interface clock.

The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control single data rate (SDR) interface between the MAC/RS and the PCS.

Figure 59. XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R Configurations

Note: Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the 10GBASE-R PCS and the Ethernet MAC/RS.

The dedicated reference clock input to the variants of the 10GBASE-R PHY can be run at either 322.265625 MHz or 644.53125 MHz.

For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of TX phase compensation FIFO (PCS data) and the write clock of TX phase compensation FIFO (XGMII data in the FPGA fabric). This can be achieved by using the same reference clock as the transceiver dedicated reference clock input as well as the reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock. The same core PLL can be used to drive the RX XGMII data. This is because the RX clock compensation FIFO is able to handle the frequency PPM difference of ±100 ppm between RX PCS data driven by the RX recovered clock and RX XGMII data.

Note: 10GBASE-R is the single-channel protocol that runs independently. Therefore Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly. If it is being configured through the Native PHY IP, the channel bonding option should be disabled. Enabling the channel bonding for multiple channels could degrade the link performance in terms of TX jitter eye and RX jitter tolerance.

2.6.2.1.1. TX FIFO and RX FIFO

In 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO.

In 10GBASE-R with 1588 configuration, both the TX FIFO and the RX FIFO are used in register mode. The TX phase compensation FIFO and the RX clock compensation FIFO are constructed in the FPGA fabric by the PHY IP automatically.

In 10GBASE-R with KR FEC configuration, you use the TX FIFO in phase compensation mode and the RX FIFO behaves as a clock compensation FIFO.

2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers

You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture, and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE 1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.

You must design your own MAC and other layers in the FPGA to implement the 10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver Configuration Rule using the Native PHY IP.

Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core for more details.
Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the Transceiver configuration rule list located under Datapath Options, depending on which protocol you are implementing.
Use the parameter values in the tables in Transceiver Native PHY Parameters for the 10GBASE-R Protocol as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. Select 10GBASE-R Register Mode for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet your specific requirements.
Click Generate to generate the Native PHY IP core RTL file.

Figure 60. Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FECGenerating the IP core creates signals and ports based on your parameter settings.
Instantiate and configure your PLL.
Create a transceiver reset controller. You can use your own reset controller or use the Arria 10 Transceiver Native PHY Reset Controller IP.
Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.

Figure 61. Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design

Figure 62. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
Simulate your design to verify its functionality.

2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Table 94. General and Datapath ParametersThe first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath options to customize the transceiver.
Parameter	Range
Message level for rule violations	error, warning
Transceiver Configuration Rule	10GBASE-R 10GBASE-R 1588 10GBASE-R with KR FEC
Transceiver mode	TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels	1 to 96
Data rate	10312.5 Mbps
Enable datapath and interface reconfiguration	Off
Enable simplified data interface	On Off

Table 95. TX PMA Parameters
Parameter	Range
TX channel bonding mode	Not bonded
TX local clock division factor	1, 2, 4, 8
Number of TX PLL clock inputs per channel	1, 2, 3, 4
Initial TX PLL clock input selection	0

Table 96. RX PMA Parameters
Parameter	Range
Number of CDR reference clocks	1 to 5
Selected CDR reference clock	0 to 4
Selected CDR reference clock frequency ³⁵	156.25 MHz, 322.265625 MHz, and 644.53125 MHz
PPM detector threshold	100, 300, 500, 1000
CTLE adaptation mode	manual
DFE adaptation mode	adaptation enabled, manual, disabled
Number of fixed DFE taps	3, 7, 11

Table 97. Enhanced PCS Parameters
Parameter	Range
Enhanced PCS/PMA interface width	32, 40, 64 Note: 10GBASE-R with KR-FEC allows 64 only.
FPGA fabric/Enhanced PCS interface width	66
Enable Enhanced PCS low latency mode	On Off
Enable RX/TX FIFO double-width mode	Off
TX FIFO mode	Phase Compensation (10GBASE-R and 10GBASE-R with KR FEC) Register or Fast register (10GBASE-R with 1588)
TX FIFO partially full threshold	11
TX FIFO partially empty threshold	2
RX FIFO mode	10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC) Register (10GBASE-R with 1588)
RX FIFO partially full threshold	23
RX FIFO partially empty threshold	2

Table 98. 64B/66B Encoder and Decoder Parameters
Parameter	Range
Enable TX 64B/66B encoder	On
Enable RX 64B/66B decoder	On
Enable TX sync header error insertion	On Off

Table 99. Scrambler and Descrambler Parameters
Parameter	Range
Enable TX scrambler (10GBASE-R / Interlaken)	On
TX scrambler seed (10GBASE-R / Interlaken)	0x03ffffffffffffff
Enable RX descrambler (10GBASE-R / Interlaken)	On

Table 100. Block Sync Parameters
Parameter	Range
Enable RX block synchronizer	On
Enable rx_enh_blk_lock port	On Off

Table 101. Gearbox Parameters
Parameter	Range
Enable TX data polarity inversion	On Off
Enable RX data polarity inversion	On Off

Table 102. Dynamic Reconfiguration Parameters
Parameter	Range
Enable dynamic reconfiguration	On Off
Share reconfiguration interface	On Off
Enable Native PHY Debug Master Endpoint	On Off
De-couple reconfig_waitrequest from calibration	On Off

Table 103. Configuration Files Parameters
Parameter	Range
Configuration file prefix	—
Generate SystemVerilog package file	On Off
Generate C header file	On Off
Generate MIF (Memory Initialization File)	On Off

Table 104. Generation Options Parameters
Parameter	Range
Generate parameter documentation file	On Off

³⁵ The CDR reference clock frequency depends on your design settings. Intel recommends that you verify the link datarates to ensure the CDR locking capability before production.

2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations

Figure 63. High BERThis figure shows the rx_enh_highber status signal going high when there are errors on the rx_parallel_data output.

Figure 64. Block Lock AssertionThis figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation.

The following figures show Idle insertion and deletion.

Figure 65. IDLE Word InsertionThis figure shows the insertion of IDLE words in the receiver data stream.

Figure 66. IDLE Word DeletionThis figure shows the deletion of IDLE words from the receiver data stream.

Figure 67. OS Word DeletionThis figure shows the deletion of Ordered set word in the receiver data stream.

2.6.3. 10GBASE-KR PHY IP Core

The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet standards:

Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3 2008 Standard. The 10GBASE-KR Ethernet PHY IP Function can auto negotiate between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC.
10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the IEEE 802.3 2008 Standard. In addition to the link-partner TX tuning as defined in Clause 72, this PHY also automatically configures the local device RX interface to achieve less than 10^-12 bit error rate (BER) target.
Gigabit Media Independent Interface (GMII) to connect PHY with media access control (MAC) as defined in Clause 35 of the IEEE 802.3 2008 Standard
Forward Error Correction (FEC) as defined in Clause 74 of the IEEE 802.3 2008 Standard

The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules to enable operation over a backplane:

Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the link-partner TX PMDs for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between 1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std 802.3ap-2007.
Forward Error Correction (FEC)—FEC function is an optional feature defined in Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism.

2.6.3.1. 10GBASE-KR PHY Release Information

Table 105. 10GBASE-KR PHY Release Information
Item	Description
Version	19.1
Release Date	April 2019
Ordering Codes	IP-10GBASEKRPHY (IP) IPR-10GBASEKRPHY (Renewal)
Product ID	0106
Vendor ID	6AF7

2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization

This topic provides performance and resource utilization for the IP.

The following table shows the typical expected resource utilization for selected configurations using the Quartus Prime software v15.1 for Arria 10 devices. The numbers of ALMs and logic registers are rounded up to the nearest 100.

Table 106. 10GBASE-KR PHY Performance and Resource Utilization
Variant	ALMs	ALUTs	Registers	M20K
10GBASE-KR PHY	2400	3750	3100	1