Ethernet Design Example Components User Guide
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 19.3 |
IP Version 19.2.0 |
1. Time-of-day Clock
The Time-of-day (TOD) Clock streams 96-bit and 64-bit time-of-day to one or more timestamping units in an IEEE 1588v2 solution. The time-of-day consist of the following fields.
Field | 96-bit Timestamp Format | 64-bit Timestamp Format |
---|---|---|
Second | 48 bits | — |
Nanosecond | 32 bits | 48 bits |
Fractional nanosecond | 16 bits | 16 bits |
This component supports coarse and fine adjustments, and period correction. It also supports configurable period adjustment and offset adjustment.
You can instantiate the TOD clock through the Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP in the Intel® Quartus® Prime software.
1.1. Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.2.0 |
Intel® Quartus® Prime Version | 19.3 |
Release Date | September 2019 |
Supported Devices |
|
1.2. Resource Utilization
Configuration | ALMs | Combinational ALUTs | Logic Registers | Memory (M20K/MLAB) |
---|---|---|---|---|
PERIOD_CLOCK_FREQUENCY = 0 OFFSET_JITTER_WANDER_EN = 0 |
727 | 733 | 1041 | 0 |
PERIOD_CLOCK_FREQUENCY = 1 OFFSET_JITTER_WANDER_EN = 0 |
764 | 736 | 1224 | 0 |
PERIOD_CLOCK_FREQUENCY = 0 OFFSET_JITTER_WANDER_EN = 1 |
1782 | 2406 | 2297 | 0 |
Configuration | ALMs | Combinational ALUTs | Logic Registers | Memory (M20K Blocks) |
---|---|---|---|---|
PERIOD_CLOCK_FREQUENCY = 0 OFFSET_JITTER_WANDER_EN = 0 |
716 | 741 | 942 | 0 |
PERIOD_CLOCK_FREQUENCY = 1 OFFSET_JITTER_WANDER_EN = 0 |
689 | 734 | 1233 | 0 |
PERIOD_CLOCK_FREQUENCY = 0 OFFSET_JITTER_WANDER_EN = 1 |
1961 | 2735 | 2530 | 0 |
1.3. Configuring the TOD Clock
In the Intel® Quartus® Prime software, instantiate the TOD clock by selecting Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the following parameters.
Name | Value | Default Value | Description |
---|---|---|---|
PERIOD_CLOCK_FREQUENCY | 0 or 1 | 1 |
Set this parameter to 0 if the MAC connected to the TOD clock requires low period clock frequency, such as the Triple-speed Ethernet or legacy 10G Ethernet MAC. For this setting, the nanosecond field in the Period and AdjustPeriod registers is 9 bits wide. Set this parameter to 1 if the MAC connected to the TOD clock requires high period clock frequency, such as Low-latency 10G Ethernet or 40G/100G Ethernet MAC. For this setting, the nanosecond field in the Period and AdjustPeriod registers is 4 bits wide. |
OFFSET_JITTER_WANDER_EN | 0 or 1 | 0 | Set this parameter to 1 to enable the offset, jitter, and wander timers; 0 otherwise. This parameter is enabled only when PERIOD_CLOCK_FREQUENCY is set to 0. |
DEFAULT_NSEC_PERIOD | 0 – n | 0x0006 | The reset value of the nanosecond field in the Period register. n is 0xF if the nanosecond field is 4 bits wide. Otherwise, n is 0x1FF. |
DEFAULT_FNSEC_PERIOD | 0 – 0xFFFF | 0x6666 | The reset value of the fractional nanosecond field in the Period register. |
DEFAULT_NSEC_ADJPERIOD | 0 – n | 0x0006 | The reset value of the nanosecond field in the AdjustPeriod register. n is 0xF if the nanosecond field is 4 bits wide. Otherwise, n is 0x1FF. |
DEFAULT_FNSEC_ADJPERIOD | 0 – 0xFFFF | 0x6666 | The reset value of the fractional nanosecond field in the AdjustPeriod register. |
1.4. Using the TOD Clock
Follow these guidelines when using the TOD clock:
- 96-bit timestamp format—load the time-of-day using the time_of_day_96b_load_data[] bus or the SecondsH, SecondsL, and NanoSec registers. The bus value always takes precedence over the register values. When loading the time-of-day through the time_of_day_96b_load_data[] bus, the output is available in the time_of_day_96[] bus after one clock cycle. Hence, Intel® recommends that you add one clock cycle to the value of the time_of_day_96b_load_data[] bus to accommodate the latency.
- 64-bit timestamp format—load the time-of-day using the time_of_day_64b_load_data[] bus. The output is available in the time_of_day_64[] bus after one clock cycle. Hence, Intel® recommends that you add one clock cycle to the value of the incoming time-of-day to accommodate the latency.
- The TOD clock does not synchronize the 96-bit and 64-bit timestamp format.
- The drift, jitter, and wander timers restart each time a new time-of-day is loaded, either through the signal or configuration registers.
1.4.1. Adjusting TOD Drift
You can use the DriftAdjust and DriftAdjustRate registers to correct drifts in the TOD clock due to insufficient binary representation of the 16-bit fractional nanosecond field in the Period register.
- DriftAdjust = 0x02, which sets the nanosecond field to 0x0 and the fractional nanosecond field to 0x2.
- DriftAdjustRate = 0x5.
1.4.2. Adjusting Offset, Jitter, and Wander
- Offset—you can use the OffsetNS and OffsetFNS registers to adjust large offsets in assisting faster system convergence. The offset can be positive or negative. The maximum correction is (109 - 50) ns.
- Jitter—you can use the JitterTimer and JitterAdjust registers to achieve small time scales (milliseconds or microseconds) frequency correction.
The jitter adjustment can either be a positive or negative adjustment per unit time. This helps achieve better frequency corrections. For very low values of the jitter, such as 1 ns correction for every second, the timer must be larger and the adjustment value must be smaller.
For example, to achieve 1 ns correction every second in a clock domain of 3.2 ns period, configure the registers as follow:- JitterTimer = 0x12A05F20, which is the hexadecimal value of (1000000000/3.2).
- JitterAdjust = 0x10000, which sets the nanosecond field to 0x1 and the fractional nanosecond field to 0x0.
- Wander—you can use the WanderTimeLSB, WanderTimeMSB, and WanderAdjust registers to achieve large time scale correction.
The wander adjustment can either be a positive or negative adjustment per unit time. Wander adjustments are typically on larger time scales such as per hour. For very low values of the wander such as 1 ns per 24 hours, the timer must be larger and the adjustment value must be smaller.
For example, to achieve 1 ns correction every 24 hours in a clock domain of 3.2 ns period, configure the registers as follow:- WanderTimerLSB[29:1] = 0x2D68_B000
- WanderTimerMSB[15:0] = 0x06239
1.4.3. Correcting TOD Offset
You can use the AdjustPeriod and AdjustCount registers to correct TOD offset. AdjustPeriod register value is used as effective period value when AdjustCount register is a non-zero value.
- set AdjustPeriod to '8+b' ns
- set AdjustCount to 'c'
By setting a = 16 ns, b = 2 ns, and c = 8, the logic produces TOD with effective period value of 10 ns in the next 8 clock cycles. After 8 clock cycles, the logic resumes the normal operation where effective period value = 8 ns.
Similarly, to correct negative TOD offset, set AdjustPeriod to '<Period register value> – b'.
1.5. Interface Signals
1.5.1. Avalon-MM Signals
Name | Direction | Width | Description |
---|---|---|---|
csr_address[] | In | n | Use this bus to specify the register address you want to read from or
write to. By default, the width of this signal is 4. When the OFFSET_JITTER_WANDER_EN parameter is set to 1, the width of this signal is 5. |
csr_read | In | 1 | Assert this signal to request a read. |
csr_readdata[] | Out | 32 | Data read from the specified register. |
csr_write | In | 1 | Assert this signal to request a write. |
csr_writedata[] | In | 32 | Data to be written to the specified register. |
clk | In | 1 | Clock for the Avalon-MM interface, whose frequency is not more than 100 MHz. |
rst_n | In | 1 | Active-low reset signal for the clk domain. Synchronous to clk. |
1.5.2. Time-of-day Signals
Name | Direction | Width | Description |
---|---|---|---|
time_of_day_96[] | Out | 96 | 96-bit time of day streamed by the TOD clock. |
time_of_day_64[] | Out | 64 | 64-bit time of day streamed by the TOD clock. |
time_of_day_96b_load_valid | In | 1 | Assert this signal for one clock cycle to indicate that the time_of_day_96b_load_data[] bus is valid. It indicates that the 96-bit time of day is synchronized and loaded into the TOD clock. |
time_of_day_64b_load_valid | In | 1 | Assert this signal for one clock cycle to indicate that the time_of_day_64b_load_data[] bus is valid. It indicates that the 64-bit time of day is synchronized and loaded into the TOD clock. |
time_of_day_96b_load_data[] | In | 96 | 96-bit time of day from the master TOD clock. |
time_of_day_64b_load_data[] | In | 64 | 64-bit time of day from the master TOD clock. |
period_clk | In | 1 | Clock for the TOD clock. Ensure that this clock is in the same clock domain as the TX and RX clock signals of the MAC IP. |
period_rst_n | In | 1 | Active-low reset signal for the period_clk domain. Synchronous to period_clk. |
1.6. Configuration Registers
Byte Offset | Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x00 | SecondsH | The upper 16-bit second field of the 96-bit TOD. The value occupies bits 0 to 15. Bits 16 to 31 are not used. Read the TOD registers in this sequence: NanoSec, SecondsL, and SecondsH. Write the TOD registers in this sequence: SecondsH, SecondsL, and NanoSec. Reading the SecondsH, SecondsL, and NanoSec registers does not necessarily return the last values written to these registers. |
RW | 0x0 |
0x01 | SecondsL | The lower 32-bit second field of the 96-bit TOD. To read from or write to the TOD registers, refer to the guidelines provided in the SecondsH register description. |
RW | 0x0 |
0x02 | NanoSec | The 32-bit nanosecond field of the 96-bit TOD. Loading this register with a value equal to or larger than a billion leads to an incorrect timestamp. To read from or write to TOD registers, refer to the guidelines provided in the SecondsH register description. |
RW | 0x0 |
0x03 | Reserved | – | – | – |
0x04 | Period | The period for the frequency adjustment.
The reset value of this register, n, is determined by the value of the DEFAULT_NSEC_PERIOD and DEFAULT_FNSEC_PERIOD parameters. |
RW | n |
0x05 | AdjustPeriod | The period for the offset adjustment.
The reset value of this register, n, is determined by the value of the DEFAULT_NSEC_PERIOD and DEFAULT_FNSEC_PERIOD parameters. |
RW | n |
0x06 | AdjustCount |
|
RW | 0x0 |
0x07 | DriftAdjust | The value that the TOD clock uses to periodically adjust the time of day.
|
RW | 0x0 |
0x08 | DriftAdjustRate |
Writing a value other than 0 to this register triggers the drift adjustment. |
RW | 0x0 |
0x09 | OffsetNS |
Writing a value other than 0 to this register triggers the offset in the time of day. |
RW | 0x0 |
0x0A | OffsetFNS |
|
RW | 0x0 |
0x0C | JitterTimer |
Periodic jitter adjustment is disabled when this register is set to 0. Writing a value other than 0 to this register enables period jitter adjustment. Hence, write to this register last. |
RW | 0x0 |
0x0D | JitterAdjust |
|
RW | 0x0 |
0x10 | WanderTimerLSB |
Writing a value other than 0 to this register enables wander timer adjustment. Hence, write to the WanderTimerLSB and WanderTimerMSB registers last. |
RW | 0x0 |
0x11 | WanderTimerMSB |
|
RW | 0x0 |
0x12 | WanderAdjust |
|
RW | 0x0 |
2. Time-of-day Synchronizer
- Master and slave TOD clocks that operate at the same frequency, between 125 MHz and 390.625 MHz. The synchronizer also supports different clock phases and PPM.
- Master and slave TOD clocks that operate at different frequencies: 62.5 MHz, 125 MHz, 156.25 MHz, 312.5 MHz, or 390.625 MHz.
You can instantiate the TOD synchronizer through the Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP in the Intel® Quartus® Prime software.
2.1. Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.2.0 |
Intel® Quartus® Prime Version | 19.3 |
Release Date | 2019.09.30 |
Supported Devices |
|
2.2. Resource Utilization
Configuration | ALMs | Combinational ALUTs | Logic Registers | Memory (M20K Blocks) |
---|---|---|---|---|
Default Mode | 563 | 636 | 1678 | 3 |
2.3. Configuring the TOD Synchronizer
In the Intel® Quartus® Prime software, instantiate the TOD Synchronizer by selecting Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the following parameters.
Name | Valid Values | Description |
---|---|---|
TOD_MODE | 0, 1 | Specifies the format of the time of day.
|
SYNC_MODE | 0 – 15 | Specifies the synchronization type between the master and slave TOD clocks.
The default value is 1. |
PERIOD_NSEC | 0 – 4'hF | Specifies the respective 4-bit nanosecond field for the reset value
for the following clock frequencies:
|
PERIOD_FNSEC | 0 – 16h'FFFF | Specifies the respective 16-bit fractional nanosecond field for the
reset value for the following clock frequencies:
|
SAMPLE_SIZE | 64, 128, or 256 | Specifies the number of samples to use in calculating the FIFO buffer’s fill level.
More samples results in a more accurate estimation of the fill
level. However, the calculation time increases with the number of
samples. The default value is 64. |
2.4. Using the TOD Synchronizer
The TOD synchronizer uses a dual-clock FIFO buffer to receive the time of day from the master TOD clock and transmits it to the slave TOD clock. To ensure that the synchronization is accurate, the transfer latency must be taken into consideration. The sampling clock (clk_sampling) samples the fill level of the FIFO buffer and calculates the latency. Derive this clock signal from the same source as the master TOD clock or the slave TOD clock using a PLL.
2.4.1. Sampling Clock Frequency
To achieve the recommended frequency for the sampling clock, follow these steps:
- The SYNC_MODE and SAMPLE_SIZE parameters determine the sampling clock factor, which is then used to determine the required PLL settings. Use the Table 11 to identify the sampling clock factor for your configuration.
- Use the sampling clock factor identified in the previous step to determine the PLL settings. Table 12 lists the settings for Stratix® V PLL Intel® FPGA IP.
SYNC_MODE | Reference Clock Frequency (MHz) |
Sampling Clock Factor | ||
---|---|---|---|---|
SAMPLE_SIZE = 64 | SAMPLE_SIZE = 128 | SAMPLE_SIZE = 256 | ||
0, 1 | 125 | 16/63 | 32/33 | 64/63 |
156.25 | 64/315 | 128/155 | 256/375 | |
2 | Master/slave frequency | 64/63 | 128/153 | 256/375 |
3, 4 | 156.25 | 64/63 | 128/153 | 256/375 |
312.5 | 32/33 | 64/63 | 128/153 | |
5, 6 | 125 | 32/63 | 64/63 | 128/63 |
312.5 | 64/315 | 128/155 | 256/375 | |
7, 8 | 125 | — | — | 32/13 |
390.625 | — | — | 256/375 | |
9, 10 | 156.25 | 32/33 | 64/31 | 128/63 |
390.625 | 64/155 | 128/185 | 256/375 | |
11, 12 | 312.5 | 16/15 | 32/33 | 64/63 |
390.625 | 64/75 | 128/185 | 256/253 | |
13 | 62.5 | 64/63 | 128/153 | 256/253 |
125 | 32/33 | 64/63 | 128/153 | |
14 | 62.5 | 32/33 | 64/63 | 128/153 |
156.25 | 64/155 | 128/155 | 256/375 | |
15 | 62.5 | 64/63 | 128/153 | 256/253 |
312.5 | 64/155 | 128/155 | 256/375 |
Sampling Clock Factor | PLL Counter | ||
---|---|---|---|
M | N | C | |
16/15 | 16 | 5 | 3 |
16/63 | 16 | 3 | 21 |
32/13 | 32 | 13 | 1 |
32/33 | 32 | 3 | 11 |
32 | 11 | 3 | |
32/63 | 32 | 3 | 21 |
64/31 | 64 | 31 | 1 |
64/63 | 64 | 9 | 7 |
64 | 21 | 3 | |
64/75 | 64 | 25 | 3 |
64/155 | 64 | 31 | 5 |
64/315 | 64 | 21 | 15 |
128/63 | 128 | 21 | 3 |
128/153 | 128 | 51 | 3 |
128 | 17 | 9 | |
128 | 9 | 17 | |
128/155 | 128 | 31 | 5 |
128/185 | 128 | 37 | 5 |
256/253 | 256 | 11 | 23 |
256/375 | 256 | 75 | 5 |
256 | 25 | 15 |
2.5. Interface Signals
Name | Direction | Width | Description |
---|---|---|---|
Clock and Reset Signals | |||
clk_master | In | 1 | Master TOD clock domain. |
reset_master | In | 1 | Synchronous reset signal in the master TOD clock domain. |
clk_slave | In | 1 | Slave TOD clock domain. |
reset_slave | In | 1 | Synchronous reset signal in the slave TOD clock domain. |
clk_sampling | In | 1 | Sampling clock to measure the transfer latency. |
Interface Signals | |||
start_tod_sync | In | 1 | Assert this signal to start the synchronization process. Synchronization continues as long as this signal is asserted. |
tod_master_data[] | In | 64 or 96 | Carries the 64-bit or 96-bit time of day from the master TOD clock. The width of this signal is determined by the TOD_MODE parameter |
tod_slave_valid | Out | 1 | When asserted, the signal indicates that the data on the tod_data_slave bus is valid and ready for transfer in the following cycle. This signal stays asserted for only 1 clock cycle. |
tod_slave_data[] | Out | 64 or 96 | Carries the 64-bit or 96-bit time of day for the slave TOD clock. This time of day is synchronized to the master TOD clock with an additional one clock cycle because it takes one clock cycle to transfer the time of day to the slave TOD clock. The width of this signal is determined by the TOD_MODE parameter. |
3. Packet Classifier
The Packet Classifier decodes the packet type of incoming PTP packets, and returns the decoded information to the MAC IP core. The decoded information is aligned to the start of packet of the corresponding PTP packet.
You can instantiate the packet classifier through the Ethernet Packet Classifier Intel® FPGA IP in the Intel® Quartus® Prime software.
3.1. Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.2.0 |
Intel® Quartus® Prime Version | 19.3 |
Release Date | September 2019 |
Supported Devices |
|
3.2. Resource Utilization
Configuration | ALMs | Combinational ALUTs | Logic Registers | Memory (M20K Blocks) |
---|---|---|---|---|
Default Mode | 212 | 297 | 179 | 8 |
3.3. Configuring the Packet Classifier
In the Intel® Quartus® Prime software, instantiate the Packet Classifier by selecting Ethernet Packet Classifier Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the parameters in the following table.
Name | Value | Default | Description |
---|---|---|---|
TSTAMP_FP_WIDTH | 1 – 32 | 4 | The width of the timestamp fingerprint. |
SYMBOLSPERBEAT | 1, 4, or 8 | 8 | The number of symbols transferred in a clock cycle. |
BITSPERSYMBOL | 8 | 8 | The number of bits per symbol transferred in a clock cycle. |
3.4. Interface Signals
3.4.1. Clock and Reset Signals
Name | Direction | Width | Description |
---|---|---|---|
clk | In | 1 | Reference clock for the packet classifier. Connect this signal to the MAC TX clock. |
reset | In | 1 | Synchronous reset signal for the packet classifier. |
3.4.2. Avalon -ST Interface Signals
Name | Direction | Width | Description |
---|---|---|---|
data_sink_sop | In | 1 | Assert this signal to indicate the beginning of the packet. |
data_sink_eop | In | 1 | Assert this signal to indicate the end of the packet. |
data_sink_valid | In | 1 | Assert this signal to indicate that the data_sink_data[] signal and other signals on this interface are valid. |
data_sink_ready | Out | 1 | When asserted, this signal indicates that the packet classifier is ready to accept data. |
data_sink_data[] | In | n 1 | The input packet. |
data_sink_empty[] | In | 2, 3 | Use this signal to specify the number of empty
bytes in the cycle that contain the end of packet. The width of this signal is 2 when the SYMBOLSPERBEAT parameter is 4; 3 when the parameter is 8. This signal does not exist when the SYMBOLSPERBEAT is 1. |
data_sink_error | In | 1 | Assert this signal to indicate that the current input packet contains errors. |
data_src_sop | Out | 1 | When asserted, this signal indicates the beginning of the packet. |
data_src_eop | Out | 1 | When asserted, this signal indicates the end of the packet. |
data_src_valid | Out | 1 | When asserted, this signal indicates that the data_src_data[] signal and other signals on this interface are valid. |
data_src_ready | In | 1 | Assert this signal when the receiving component is ready to accept data. |
data_src_data[] | Out | n 1 | The output data. |
data_src_empty[] | Out | 2, 3 | Contains the number of empty bytes in the cycle
that contain the end of packet. The width of this signal is 2 when the SYMBOLSPERBEAT parameter is 4; 3 when the parameter is 8. This signal does not exist when the SYMBOLSPERBEAT is 1. |
data_src_error | Out | 1 | When asserted, this signal indicates that the current output packet contains errors. |
3.4.3. Control Signals
Name | Direction | Width | Description |
---|---|---|---|
tx_etstamp_ins_ctrl_in_ingress_timestamp_96b | In | 96 | The 96-bit timestamp received from the MAC RX, aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_in_ingress_timestamp_64b | In | 64 | The 64-bit timestamp received from the MAC RX, aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_out_ingress_timestamp_96b | Out | 96 | The 96-bit timestamp to the MAC TX, aligned to the corresponding output PTP packet. |
tx_etstamp_ins_ctrl_out_ingress_timestamp_64b | Out | 64 | The 64-bit timestamp to the MAC TX, aligned to the start of packet of the corresponding output PTP packet. |
tx_egress_timestamp_request_in_valid | In | 1 | Assert this signal to indicate that a timestamp is required for the packet. This signal must align to the start of an input packet. |
tx_egress_timestamp_request_in_fingerprint | In | TSTAMP_FP_WIDTH | The timestamp's fingerprint for the input packet. |
tx_egress_timestamp_request_out_valid | Out | 1 | Assert this signal when timestamp is required for the particular frame. This signal is aligned to the start of packet of the corresponding output PTP packet. |
tx_egress_timestamp_request_out_fingerprint | Out | TSTAMP_FP_WIDTH | The timestamp's fingerprint for the output packet. |
clock mode | In | 2 | Specify the clock mode:
|
pkt_with_crc | In | 1 | Use this signal to indicate whether or not the incoming packet
contains 4-byte CRC field.
|
tx_etstamp_ins_ctrl_in_residence_time_calc_format | In | 1 | Use the following values to specify the format of the timestamp
to use when calculating the residence time.
|
tx_etstamp_ins_ctrl_out_residence_time_calc_format | Out | 1 | The format of the timestamp used to calculate the residence time.
|
tx_etstamp_ins_ctrl_out_checksum_zero | Out | 1 | When asserted, indicates that the checksum field of the PTP packet is set to zero. This signal is aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_out_checksum_correct | Out | 1 | When asserted, indicates that the checksum of the PTP packet is corrected by updating the checksum correction offset. This signal is aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_out_timestamp_format | Out | 1 | The format of the timestamp.
|
tx_etstamp_ins_ctrl_out_timestamp_insert | Out | 1 | When asserted, indicates that an egress timestamp must be inserted into the corresponding PTP packet. This signal is aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_out_residence_time_update | Out | 1 | When asserted, indicates that the residence time is added to the correction field of the PTP packet. This signal is aligned to the start of packet of the corresponding PTP packet. |
tx_etstamp_ins_ctrl_out_offset_timestamp | Out | 16 | The location of the timestamp field, relative to the first byte of the packet. |
tx_etstamp_ins_ctrl_out_offset_correction_field | Out | 16 | The location of the correction field, relative to the first byte of the packet. |
tx_etstamp_ins_ctrl_out_offset_checksum_field | Out | 16 | The location of the checksum field, relative to the first byte of the packet. |
tx_etstamp_ins_ctrl_out_offset_checksum_correction | Out | 16 | The location of the checksum correction field, relative to the first byte of the packet. |
4. Ethernet Design Example Components User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
IP Core Version | User Guide |
---|---|
19.2.0 | Ethernet Design Example Components User Guide |
18.0 | Ethernet Design Example Components User Guide |
16.0 | Ethernet Design Example Components User Guide |
5. Document Revision History for the Ethernet Design Example Components User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2019.09.30 | 19.3 | 19.2.0 |
|
2019.07.01 | 19.2 | 19.2.0 |
|
2018.12.03 | 18.0 | 18.0 |
|
Date | Version | Changes |
---|---|---|
March 2017 | 2017.03.08 |
|
May 2016 | 2016.05.02 | Initial release. |