Remote Hardware Debugging over TCP/IP for Altera SoC
You can perform remote debugging of your system with System
Console. Debug equipment deployed in the field through an existing TCP/IP
Run a network stack on either a Nios II processor or a hard
processor system (HPS) and piggyback on an existing remote administration
setup. This application note focuses on the case of using an Altera SoC.
Historically, the Altera System-Level Debugging (SLD)
communication solution was based on the Altera JTAG Interface (AJI) which
interfaced with the JTAG TAP controller (hard atom in Altera devices which
implements the JTAG protocol).
The SLD tools (SignalTap II Logic Analyzer, In-System Sources
and Probes (ISSP), In-System Memory Content Editor) and the Nios II on-chip
instrumentation (OCI) use the JTAG channel for communication between software
and hardware. To support communication via TCP/IP, the SLD Hub Controller
replaces the JTAG TAP controller.
Figure 1. TCP/IP Communication Channel Block Diagram
Why would you use this feature?
To debug a device when you
cannot access the JTAG connections (due to mechanical restrictions or
To debug a device remotely,
such as at a customer site.
In a team-based situation
with several people working on a single device.
Quartus II software version
13.0 or later installed on your local PC
Familiarity with networking
SLD Hub Controller Linux
driver (for SoC device)
Linux running on the HPS
SLD Hub Controller
Microprocessor connected to
the Altera FPGA (either internally or externally)
Altera SoC with the HPS
connected to an Ethernet port
Programming device connected
to an Ethernet cable at the remote location
Altera SoCs integrate an ARM-based hard processor system
consisting of a processor, peripherals, and memory interfaces with the FPGA
fabric using a high-bandwidth interconnect backbone.
This application note assumes the HPS in the FPGA is running
the Linux kernel. This simplifies the remote debugging feature. The processor
monitors a TCP/IP socket for incoming transactions. The data bytes in these
transactions are extracted and written directly to the SLD Hub Controller
system hardware without modification. For outgoing data, the SLD Hub Controller
system produces data that the processor packages into TCP/IP packets and
transmits over the socket without modification.
SLD Hub Controller
The SLD Hub Controller component converts Avalon-ST packets to
JTAG operations. This component connects most Altera SLD applications to
hardware through a non-JTAG channel when used together with an appropriate
driver in System Console.
Note: You cannot remote debug hardware using a JTAG connection through
the JTAG TAP controller after instantiating the SLD Hub Controller component.
The SLD Hub enables multiple nodes to share access to the user
debug interface. The remote debugging feature supports the following system
debugging tools over TCP/IP.
Supported System Debugging Tools
SignalTap II Logic Analyzer
In-System Sources and Probes
In-System Memory Content
Logic Analyzer Interface
Figure 3. Connecting SLD Hub to Adapter
How to Remote Debug with the SignalTap II Logic Analyzer
To implement remote debugging for the SignalTap II Logic
Analyzer over TCP/IP, follow these steps:
Verify your design can run a TCP server with memory-mapped access
to the device.
For Altera SoC, the Linux kernel handles the TCP/IP connection.
SLD Hub Controller System component from the
Figure 4. SLD Hub Controller System
Generate the Qsys
Tap some nodes
using SignalTap II Logic Analyzer.
Using the existing
remote configuration setup, update the remote board with firmware which
contains the SLD Hub Controller System instantiated in the FPGA over the TCP
server (enabled to listen for incoming debug connections).
Console in JTAG server mode using the Tcl script in the Reference Design or
using a custom script.
to .sof><IP><port number>
start the SignalTap II Logic Analyzer. You should see a System Console cable as
an option under
Figure 5. Successfully Connected in SignalTap II Logic
1 The SLD Hub Controller
Avalon Memory Mapped Slave connects to h2f AXI Master
Getting the Source Code for the SLD Hub Controller Driver
The SLD Hub Controller driver provided with Application Note 693 is only compatible
with Linux kernel 3.8.0-00069-g54902df-dirty. You can get the source code for the
sld_hub.ko driver from the RocketBoards.org website.
RocketBoards is an open source community that provides resources for embedded
solutions that allow you to explore and prototype applications for Altera SoC.
You can find detailed instructions to use the git repository on the RocketBoards
website. The following is a high-level flow for using the git repository:
Clone the Linux kernel git tree.
Checkout the appropriate branch.
Configure the kernel to enable the
driver. Use the following commands.
Note: Navigate to the Device Drivers/Character Devices/Altera MM Debug
Link Driver and click M to compile the
driver as a loadable module.
Compile the Linux kernel.
The user-mode app mmlink bridges between TCP/IP and the mm-debug-link device driver.
The default device driver has permissions 0600, which can prevent you from opening
the driver. If you encounter an error when you run the mmlink with these permissions
in the driver, you may see an error such as below:
failed to init driver: 13 (Permission denied)
The permissions of the driver can be modified, and the error avoided, by adding a
udev rules file as follows: