AN 307: Intel FPGA Design Flow for Xilinx Users
Introduction to Intel FPGA Design Flow for Xilinx Users
This document is intended for Xilinx® designers who are familiar with the Xilinx® Vivado® software and want to convert existing Vivado® designs to the Intel® Quartus® Prime Pro Edition software environment.
This application note starts with a description of the current Xilinx® and Intel® FPGA technologies and compares devices available for three different process technologies. It further highlights unique features of Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices supported in the latest edition of the Intel® Quartus® Prime Pro Edition software.
The next chapter draws a parallel between the design flows in the Intel® Quartus® Prime Pro Edition software and Xilinx® Vivado® software, comparing features whenever possible.
The following chapter provides guidelines to convert Vivado® designs to the Intel® Quartus® Prime Pro Edition software, including Xilinx® IP Catalog modules and instantiated primitives. The last part of the chapter demonstrates how to translate device and design constraints.
This application note uses the latest information available for the Intel® Quartus® Prime Pro Edition software version 17.1 and Xilinx® Vivado® Design Suite version 2017.2, supporting the latest programmable chips.
Technology Comparison
Intel FPGAs
Intel® FPGAs are ideal for a wide variety of applications, from high-volume applications to state-of-the-art products. Each FPGA series include different features, such as embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, or high-speed I/O pins, to cover a broad range of end products. Intel® has four classes of FPGAs to meet market needs from the industry’s highest density and performance to the most cost effective:
- Stratix® FPGA and SoC family enables you to deliver high-performance, state-of-the-art products to market faster with lower risk and higher productivity
- Arria® family delivers optimal performance and power efficiency in the midrange.
- Cyclone® FPGA series is built to meet your low-power, cost-sensitive design needs, enabling you to get to market faster.
The latest Intel® Stratix® 10 FPGAs and SoCs are built on the Intel® ’s 14 nm Tri-Gate process, and introduces the heterogenous 3D system-in-package (SiP) technology. The SiP technology enables in-package integration of a range of components such as analog, memory, ASIC, CPU, etc. while keeping the FPGA fabric monolithic. In addition, Intel® Stratix® 10 FPGAs integrate transceiver die or tiles from different process nodes in the same package. This unique solution addresses these challenges: higher bandwidth, lower power, smaller form factor, and increased functionality and flexibility. For more information about SiP, refer to the Enabling Next-Generation Platforms Using Intel® ’s 3D System-in-Package Technology white paper.
Intel® SoCs bring high integration and advanced system, power, and security management capabilities to Intel® ’s product portfolio. Industry-standard Arm® tools, along with a broad ecosystem of operating systems and development tools, support Intel® SoCs.
Xilinx FPGAs
Xilinx® UltraScale+® family of FPGAs, 3D ICs and MPSoCs are built on TSMC’s 16nm process and use a homogeneous integration technology which breaks the FPGA fabric into multiple dice. This approach uses Stacked1 Silicon Interconnect (SSI) to connect the die tiles. For more information refer to the Xilinx® website.
Comparison Table
The following table lists different range devices available in last 3 process technologies for Intel® and Xilinx® :
Process Technology | 20 nm | 16 nm | 14 nm | |||
---|---|---|---|---|---|---|
Intel® | Xilinx® | Intel® | Xilinx® | Intel® | Xilinx® | |
Best Performance Or Fastest, Most Powerful |
- |
Virtex® UltraScale® |
- |
Virtex® UltraScale+® Zynq® UltraScale+® 2 |
Intel® Stratix® 10 3 | - |
Best Price/performance/watt Or Balance of cost, power, performance |
Intel® Arria® 10 3 |
Kintex UltraScale® |
- |
Kintex UltraScale+® Zynq® UltraScale+® MPSoC |
- | - |
Cost-Optimized Or Low system cost plus performance |
Intel® Cyclone® 10 GX | - | - | - | - | - |
Intel FPGA Device Features
Performance | A speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available Intel® FPGA IP Evaluation Mode designs. |
Power | Intel® Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs |
Industry’s only |
|
Applications | FPGAs and SoCs deliver the integration needed to address a wide range of applications for many industries, including communications, defense, broadcast, high-performance computing, test, and medical |
Performance | Built on the Intel® 14 nm Tri-Gate process, Intel® Stratix® 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power. 5 |
Power | Take advantage of heterogeneous 3D system-in-package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package. |
Floating-point operations |
|
Processor | Highly efficient quad-core Arm® Cortex® -A53 processor cluster optimized for ultra-high performance per watt, which reduces power consumption up to 70% over previous-generation SoC FPGAs.5 |
Applications | Uniquely positioned to address next-generation, high-performance systems in the most demanding applications including communications, datacenter acceleration, high performance computing, radar processing, ASIC prototyping, and many more. |
Industry’s first | Low-cost FPGA with IEEE 754-compliant hard floating-point DSP blocks |
Applications | Optimized for high-bandwidth, performance applications such as Industrial Vision, Robotics, and Automotive Infotainment. |
FPGA Tools Comparison
The Intel® Quartus® Prime design software delivers the highest performance, optimum logic utilization, and fastest compile times for high-end FPGA designs. New algorithms and technologies enable the Intel® Quartus® Prime Pro Edition software to scale the range of densities and features that next-generation FPGAs offer.
The Intel® Quartus® Prime Pro Edition software allows you to implement a FPGA design either by using command-line executables and scripting, or by using the Intel® Quartus® Prime GUI.
Hardware and Software Tools for FPGA Design
Xilinx® | Intel® | Description |
---|---|---|
Vivado®
HL
Design Edition
|
Intel®
Quartus® Prime Pro Edition
|
Optimized to support the advanced features in next generation FPGAs and SoCs. |
ISE®
Design Suite for:
|
Intel®
Quartus® Prime Standard Edition for:
|
Supports older generation device families. Note:
Intel®
recommends using newer version of
Intel®
Quartus® Prime for new designs.
|
Vivado® HL WebPACK Edition | Intel® Quartus® Prime Lite Edition |
|
SDAccel Environment
|
Intel® FPGA SDK for OpenCL™
|
Development environment for OpenCL |
SDSoC Environment | Intel® SoC FPGA Embedded Development Suite | Comprehensive tool suite for embedded software development on SoCs. You can code, build, debug, and optimize in single IDE. |
Software Development Kit | Nios® II Embedded Design Suite (EDS) | Comprehensive development package to develop and debug code for SoCs |
System Generator6 for DSP | DSP Builder for Intel® FPGAs 7 8 | DSP Design Tool |
Vivado® High-Level Synthesis | Intel HLS Compiler | High-Level synthesis tool that takes in untimed software code as input and generates register-transfer level code for FPGAs. |
FPGA Design Flow Using Command Line Scripting
Automating the FPGA design process saves time and increases productivity. The Vivado® software and the Intel® Quartus® Prime Pro Edition software provide the tools necessary to automate your FPGA design flow.
The compilation flow is the sequence and methods by which the software translates design files, maps the translated design to device-specific elements, places and routes the design in the device, and generates programming files. The Intel® Quartus® Prime Pro Edition software performs these functions through stages such as Analysis and Synthesis, Fitter, Assembler, and Timing Analyzer. If you are familiar with the command-line flow in the Vivado® software, you can detect parallels with the Intel® Quartus® Prime Pro Edition software.
The following figure shows the typical stages of the compilation flow and the corresponding Xilinx® Vivado® and Intel® FPGA Intel® Quartus® Prime Pro Edition command line instructions for each stage.
The Hyper-Aware Design Flow
The Hyper-Aware Design Flow allows you to take full advantage of the Intel® Stratix® 10 Intel® Hyperflex™ architecture. This flow combines automated register retiming (Hyper-Retiming), with implementation of target timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for Intel® Stratix® 10 designs:
- Hyper-Retiming:
A key innovation of the Intel® Stratix® 10 architecture is the addition of multiple Hyper- Registers in every routing segment and block input. Maximizing the use of Hyper-Registers improves design performance. The prevalence of Hyper-Registers improves balance of time delays between registers and mitigates critical path delays.
- Fast Forward Compilation:
If you require optimization beyond Hyper-Retiming, run Fast Forward compilation to generate timing closure recommendations that break key performance bottlenecks. Fast Forward compilation shows precisely where to make the most impact with RTL changes, and reports the performance benefits you can expect from each change.
Command-Line Executable Equivalents
The table and following sections describe and compare the two software flows using command line executables. The examples belong to the fir_filter design, included in the Intel® Quartus® Prime Pro Edition installation.
Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software | Description | |
---|---|---|---|
Non-Project Mode | Project Mode | ||
read_ip |
add_files
import_files |
quartus_ipgenerate | IP generation |
synth_design
opt_design |
launch_runs synth_1 | quartus_syn | Elaboration checks for design files and project
errors. Translates project design files (for example, RTL or EDA netlist), and maps design elements to device resources. |
place_design
phys_opt_design 9 route_design phys_opt_design 9 |
launch_runs impl_1 |
quartus_fit (full compile) OR quartus_fit --plan quartus_fit --early_place 9 quartus_fit --place quartus_fit --route quartus_fit --finalize |
Places and routes the device resources into the FPGA. |
Not Available | quartus_fit --retime 10 | Enabled by default, and runs before finalizing. Moves existing registers into Hyper-Registers for fine-grained performance improvement. | |
Not Available | quartus_fit --fastforward 10 | Disabled by default. Runs after retime but before finalize. Generates detailed reports that estimate performance gains achievable by making specific RTL modifications. | |
report_timing | quartus_sta | Performs a static timing analysis on the design. | |
write_bitstream | quartus_asm | Generates programming file from post-place-and-route design. | |
report_power | quartus_pow | Performs power estimation on the design. | |
write_sdf
write_verilog write_vhdl |
quartus_eda | Generates output netlist files for use with other EDA tools. | |
write_checkpoint | quartus_cdb | Saves the snapshot of the design database. | |
Not Available | quartus_sh --flow compile | Automates the compilation flow. |
For command line help on any of the Intel® Quartus® Prime executables, type <command-line executable> --help at the command prompt. A GUI-enabled help browser is also available that covers all Intel® Quartus® Prime command-line executables.

synth_design
The following command runs logic synthesis and technology mapping of a design named filtref:
quartus_syn filtref --rev=<revision-name>
In addition, you can recompile11 only the partitions that you change, instead of compiling the whole design.
quartus_sh --flow recompile filtref
For command line help, type quartus_syn --help at the command prompt.
place_design/route_design
- Plan—places all periphery elements (such as I/Os and PLLs) and determines a legal clock plan, without core placement or routing.
- Early Place—places all core elements in an approximate location to facilitate design planning. Finalizes clock planning for Intel® Stratix® 10 designs.
- Place—places all core elements in a legal location.
- Route—creates all routing between the elements in the design.
- Retime 12 —performs register retiming and moves existing registers into Hyper-Registers to increase performance by removing retiming restrictions and eliminating critical paths.
- Finalize—for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, converts unnecessary tiles to High-Speed or Low-Power. For Intel® Stratix® 10 devices, performs post-route.
- Fast Forward12—generates detailed reports that estimate performance gains achievable by making specific RTL modifications.
You can run each Fitter stage standalone by providing the appropriate argument to the quartus_fit executable. For more information, run quartus_fit --help.
The following example performs place-and-route by fitting the logic of the Intel® Quartus® Prime Pro Edition filtref project:
quartus_fit filtref
For command line help, type quartus_fit --help at the command prompt.
report_timing
To specify timing constrains, the Intel® Quartus® Prime Pro Edition software uses the industry standard Synopsys® Design Constraint (SDC) file format. The Xilinx® 's Design Constraint File (.xdf) constraint format is based on the SDC format. For details on converting XDC to SDC files, refer to the Timing Constraints section.
This example performs timing analysis on the filtref project using the SDC timing constraints file, filtref.sdc, to determine whether the design meets the timing requirements:
quartus_sta filtref --sdc=filtref.sdc
For command line help, type quartus_sta --help at the command prompt.
write_bitstream
The following example creates the filtref.sof programming file for the filtref project:
quartus_asm filtref
For command line help, type quartus_asm --help at the command prompt.
write_sdf/write_verilog/write_vhdl
The following example creates the filtref.vo simulation Verilog HDL netlist file, that you can use to simulate the filtref project with ModelSim® :
quartus_eda filtref --simulation=on --format=verilog --tool=modelsim
For command line help, type quartus_eda --help at the command prompt.
report_power
The following example uses a .vcd file as input to perform power analysis and filter glitch on the filtref project:
quartus_pow filtref --input_vcd=<vcd filename> --vcd_filter_glitches=on
For command line help, type quartus_pow --help at the command prompt.
write_checkpoint
In addition, the quartus_cdb executable allows you to import and export version-compatible databases. This ability simplifies design migration between versions of the Intel® Quartus® Prime Pro Edition software; you can import a database from a version of the Intel® Quartus® Prime Pro Edition into another version of the software, without the need of full compilation. After import, you only need to rerun timing analysis or simulation with the updated timing models.
Run Complete Design Flow
The following example runs compilation, timing analysis, and programming file generation with a single command:
quartus_sh --flow compile filtref
For command line help, type quartus_sh --help=flow at the command prompt.
Programming and Configuration File Support in the Intel Quartus Prime Pro Edition Software
The table lists the programming and configuration file formats that the Intel® FPGAs, CPLDs, and configuration devices support.
File Format | FPGA | CPLD | Configuration Device | Serial Configuration Device |
---|---|---|---|---|
SRAM Object File (.sof) | Yes | — | — | — |
Programmer Object File (.pof) | — | Yes | Yes | Yes |
JEDEC JESD71 STAPL Format File (.jam) | Yes | Yes | Yes | — |
Jam Byte Code File (.jbc) | Yes | Yes | Yes | — |
FPGA Design Flow Using Tools with GUIs
The Intel® Quartus® Prime Pro Edition and the Vivado® software GUIs address the major FPGA design steps in different ways.
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Project Creation | New Project | New Project Wizard |
Design Entry | HDL Editor | HDL Editor |
EDA Netlist | EDA Netlist | |
- | Schematic/Block Editor | |
- | State Machine Editor | |
IP Catalog | IP Catalog and Parameter Editor | |
IP Integrator | Platform Designer System Integration Tool | |
IP Packager | Platform Designer Component Editor | |
IP Status | Report IP Status | Upgrade IP Components |
Design Constraints | Device, Physical and Timing Constraints window |
Assignment Editor, Timing Analyzer Text Editor |
Synthesis | Synthesis | Analysis and Synthesis |
Third-Party EDA Synthesis | Third-Party EDA Synthesis | |
Design Implementation | Implementation | Fitter (Plan, Early Place, Place, Route, Retime0 and Finalize) |
Finalize Pinout |
Byte Planner for memory banks Device Window and Package Window in I/O Planning View Layout |
Interface Planner Pin Planner |
Viewing and Editing Design Placement |
Device Window (in I/O Planner View Layout) Package Window (in I/O Planner View Layout) |
Chip Planner |
Static Timing Analysis | Report Timing | Timing Analyzer |
Generation of Device Programming Files | Hardware Manager | Assembler |
Power Analysis |
Xilinx® Power Estimator (XPE) Report Power |
Early Power Estimation (EPE) Power Analyzer |
Simulation | Vivado® Simulator | ModelSim® - Intel® FPGA Starter Edition |
Third-Party Simulation Tools | Third-Party Simulation Tools | |
Hardware verification | Hardware Manager | System Console |
Integrated Logic Analyzer (ILA) and System ILA IP | Signal Tap Logic Analyzer | |
Xilinx® Virtual Input Output (VIO) | In-System Sources and Probes | |
JTAG-to-AXI Master | System Console | |
IBERT IP and Serial I/O Analyzer Tool | Transceiver Toolkit | |
Memory Calibration Debug Tool |
EMIF Debug Toolkit EMIF Debug GUI |
|
Remote Debug using Xilinx® Virtual Cable (XVC) | Remote Debug using existing TCP/IP connection | |
- |
Signal Probe 14 In-System Memory Content Editor Logic Analyzer Interface (LAI) |
|
View Netlist |
Schematic Window (Elaborated) Schematic Window (Synthesized) Schematic Window (Implemented) |
RTL Viewer (Post Synthesis) Technology Map Viewer (Post-Mapping) Technology Map Viewer (Post-Fitting) Fast Forward Viewer (Post-Fitting) |
Design Optimization | - | Hyper-Aware Design Flow15 |
Physical Optimization | Physical Synthesis Optimization | |
Techniques to improve productivity | Incremental Compile | Rapid Recompile16 |
Hierarchical Design | Block-Based Design Flows | |
- | Design Space Explorer II (DSE) | |
Partial Reconfiguration | Yes | Yes |
Output Products | Design Checkpoints | Export Design Partitions |
Add-On Development Tools | Vivado® High-Level Synthesis | High-Level Synthesis Compiler |
Project Creation
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Project Creation | New Project | New Project Wizard |
Similar to the New Project command in the Vivado® software, the Intel® Quartus® Prime Pro Edition software provides the New Project Wizard tool (File > New Project Wizard), which guides you through specifying a project name and directory, top-level design entity, any EDA tools you are using, and a target device.
Comparison
After creating a new project, the Intel® Quartus® Prime Pro Edition software automatically generates the following project files necessary for successful compilation:
Intel® Quartus® Prime Pro Edition | Xilinx® Vivado® | |||
---|---|---|---|---|
File Type | Description | File Type | Description | |
Project File | Intel® Quartus® Prime Project File (.qpf) | Project and revision name | Xilinx® Project File (.xpr) | XML file with list of files. Contains the information about target device or design files. |
Project Settings | Intel® Quartus® Prime Settings File (.qsf) | Lists design files, entity settings, target device, synthesis directives, placement constraints | Xilinx® Design Constraints File (.xdc) | Contains Synthesis, placement and timing constraints |
Features
Design Entry
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Design Entry | HDL Editor | HDL Editor |
EDA Netlist | EDA Netlist | |
- | Schematic/Block Editor | |
- | State Machine Editor | |
IP Catalog | IP Catalog and Parameter Editor | |
IP Integrator | Platform Designer System Integration Tool | |
IP Packager | Platform Designer Component Editor |
Managing Project Files
In the Xilinx® Vivado® software, you use the Add Source dialog box to add or remove existing design files. To add or remove existing design files from a project in the Intel® Quartus® Prime software:
- Click Assignments > Settings to open the Settings dialog box.
- In the Category list, select Files to open the Files page. This page allows you to add or remove files.
HDL Editor
In the Vivado® software you create a new HDL design file using the New Source Wizard on the Project menu. To create a new HDL design file in the Intel® Quartus® Prime Pro Edition software, click File > New, and then select the type of file you want to create.
- To assist you in creating HDL designs, the Intel® Quartus® Prime software provides design example templates for VHDL and Verilog HDL, including language constructs examples to help you get started on a design.
- The Intel® Quartus® Prime Text Editor offers syntax coloring for highlighting HDL reserved words and comments.
Schematic/Block Editor
- To create a block design file from a VHDL or Verilog HDL design file, click File > Create/Update, and click Create Symbol Files for Current File.
- To create a new schematic file (*.bdf) in the Intel® Quartus® Prime Pro Edition software, point to File > New and select the Block Diagram/Schematic File.
- To insert block symbols into the schematic, double-click the schematic file and choose the appropriate block symbols.

State Machine Editor
- Click File > New.
- In the New dialog box, expand the Design Files list, and then select State Machine File.
IP Catalog and Parameter Editor
Features of the IP Catalog
- Allows you to create custom IP cores that are optimized for the design's target device.
- Intel® provides a library-of parameterized-modules (LPM). This library offers architecture-independent functions for all devices that the Intel® Quartus® Prime Pro Edition supports.
- The IP Catalog is also available from Platform Designer. The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IPs that are available only if you access the IP Catalog from Platform Designer. To open Platform Designer from the Intel® Quartus® Prime Pro Edition software, click Tools > Platform Designer . To display the IP Catalog from Platform Designer, click View > IP Catalog.
Platform Designer System Integration Tool
Features
Platform Designer enables the use of processors (such as the Intel® FPGA Nios® II embedded processor), interfaces to off-chip processors, standard peripherals, IP cores, on-chip memory, off-chip memory, and user-defined logic into a custom system module.
Platform Designer generates a single system module that instantiates these components and automatically generates the necessary interconnect logic to bind them together.
Migration
- Xilinx® uses AMBA® AXI as the standard bus interface for communication between IPs. Consequently, custom IPs that you build with Vivado® software use the AMBA® 4 AXI protocol.
- Even though Intel® FPGA uses Avalon® as the standard bus interface, Platform Designer supports multiple AMBA® AXI interfaces. For details about interface support, refer to the Intel® Quartus® Prime Pro Edition Handbook Volume 1 .
Alternatively, Platform Designer makes the migration easier by allowing conversion from Avalon® to AMBA® AXI interface via AMBA® AXI Agents and AMBA® AXI translators.
For more information about system design with Platform Designer and AMBA® AXI Protocol Support in Platform Designer, refer to the Intel® Quartus® Prime Pro Edition Handbook Volume 1 .
Platform Designer Component Editor
- To create a new component using the Component Editor, in the Platform Designer main window click File > New Component.
- When you define a component with the Component Editor, Platform Designer writes the information to an _hw.tcl file. This file contains the component's description, interfaces, and HDL files.
- If the component requires custom features that the Platform Designer Component Editor does not support, for example, an elaboration callback, you can use the Component Editor to create the _hw.tcl file, and then manually edit the file to complete the component definition.
IP Status
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
IP Status | Report IP Status | Upgrade IP Components |
When you open a project containing outdated IP, the Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project > Upgrade IP Components to upgrade outdated IP cores.
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for IP cores in your design. You must upgrade IP cores that require upgrade before you can compile the IP variation in the current version of the Intel® Quartus® Prime Pro Edition software. The upgrade process preserves the original IP variation file in the project directory as <my_variant>_BAK.qsys
Design Constraints
The Vivado® software provides GUI editors (Device/Physical/Timing windows) to create and edit design constraints. Xilinx® designs store all the constraints and attributes in Xilinx® Design Constraint (.xdc) files, including timing and device constraints. You can also edit .xdc files with a text editor.
Intel® FPGA designs use separate files for device (.qsf) and timing (.sdc) constraints, and stores timing constraints in Synopsys® Design Constraints (SDC) format. To view and edit pin assignments, device options, and logic options, use the Assignment Editor. To view and edit timing constraints, use the Text Editor in the Timing Analyzer GUI.
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Design Constraints | Device, Physical and Timing Constraints window |
Assignment Editor, Timing Analyzer Text Editor |
Features
The table summarizes the file format and assignment types that the tools in the Intel® Quartus® Prime Pro Edition software set.
Assignment Type | File Format | Tools to Make Assignments |
---|---|---|
Timing | SDC | Timing Analyzer |
I/O-related | TCL | Interface Planner |
QSF | Pin Planner, Interface Planner | |
Others | Assignment Editor |
With separate constraint files, you avoid searching for timing constraints among other device constraints. Additionally, you can modify the timing constraints and check for validity without recompiling. In place of the I/O Planning in the Vivado® software, Intel® Quartus® Prime Pro Edition software offers the Interface Planner to plan interfaces and device periphery, and the Pin Planner to edit, validate, and export pin assignments.
For equivalence between design constraints, refer to the Set Equivalent Xilinx® Design Constraints section.
Assignment Editor
The Intel® Quartus® Prime software dynamically validates changes that you make through the editor, and issues errors or warnings for invalid assignments.
The System tab of the Intel® Quartus® Prime message window acknowledges adding or changing assignments.

Create Timing Constraints with the Timing Analyzer GUI
To create timing constraints with the Timing Analyzer GUI:
- Create a timing netlist by clicking Netlist > Create Timing Netlist.
- Click File > New SDC File to open a new SDC file.
-
From the Constraints
menu, select the constraint you want to add..
The selected constraint's dialog box opens, and allows you to set the constraint's parameters.
Figure 5. Example: Create Clock Dialog Box - Enter the values in the dialog box, and click Insert to insert the SDC command into the open SDC file.
- Save the updated SDC file.
The constraints are available on the Constraint menu are:
|
|
Create Timing Constraints with the Timing Analyzer Text Editor
- To create a new SDC file from the Timing Analyzer, click File > New SDC File.
-
To apply templates for SDC constraints, click Edit > Insert Template command.
The Timing Analyzer Text Editor uses syntax coloring for SDC reserved words and comments.
Figure 6. Timing Analyzer Text Editor
Synthesis
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Synthesis | Synthesis | Analysis and Synthesis |
Third-Party EDA Synthesis | Third-Party EDA Synthesis |
Features
The Intel® Quartus® Prime Pro Edition Synthesis engine enforces strict industry-standard HDL structures. For the 17.1 release, The Intel® Quartus® Prime Pro Edition Synthesis supports the following enhancements:
- Support for modules with System Verilog Interfaces
- Improved support for VHDL2008
- New RAM inference engine that infers RAMs from GENERATE statements or array of integers
- Stricter syntax/semantics check for improved compatibility with
other EDA tools
- Does not support the third-party netlists as input, but can generate netlist that other EDA tools use
At the end of synthesis, the Compiler generates an atom netlist, which is a database of the atom elements that design synthesis requires to implement the design in silicon. The Analysis & Synthesis module of the Compiler creates one or more project databases for each design partition. You can specify various settings that affect synthesis processing.
Access
The Assignments > Settings > IP Settings dialog box allows you to control the IP regeneration stage for synthesis or simulation
The Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) dialog box allows you to set options that affect the analysis and synthesis stage of the compilation flow. These options include Optimization Technique, State Machine Processing, Restructure Multiplexers, and others.
Design Implementation
The implementation flow in the Vivado® software places and routes the netlist onto the FPGA device resources based on the constraints of the design. The Finalize flow in the Intel® Quartus® Prime Pro Edition software consists of the Plan, Place, Route, Retime 17, and Finalize compilation stages. Start the Finalize flow by clicking Fitter in the Compilation Dashboard.
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Design Implementation | Implementation | Fitter (Plan, Early Place, Place, Route, Retime17 and Finalize) |
Features
The Intel® Quartus® Prime Pro Edition Compiler offers unique features, such as:
- Incremental Fitter Optimizations—run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports. You can view detailed report data and analyze the timing of each stage while downstream stages are still running.
- Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Intel® Stratix® 10 devices.
You can start each phase in the compilation flow independently either from GUI or from the command line. The Compilation Dashboard allows you to use the tools and features of the software and monitor progress from a flow-based layout.
Access
The Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) dialog box allows you customize the place and route of the compilation flow.
Finalize Pinout
In the Vivado® software, you can use the I/O Planning View Layout to finalize the pinout. For I/O planning of Memory Interfaces, the Vivado® software uses the Memory Bank/Byte Planner.
Intel® Quartus® Prime Pro Edition Software provides the Interface Planner and the Pin Planner to help you with the I/O Planning.
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Finalize Pinout |
Byte Planner for memory banks Device Window and Package Window in I/O Planning View Layout |
Interface Planner Pin Planner |
Pin Planner

Interface Planner
The Vivado® software supports I/O exploration and assignment via the I/O Planning View Layout.
- Prototype interface implementations
- Plan clocks
- Rapidly define a legal device floorplan
Viewing and Editing Design Placement
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Viewing and Editing Design Placement |
Device Window (in I/O Planner View Layout) Package Window (in I/O Planner View Layout) |
Chip Planner |
With the Chip Planner, you can view post-compilation placement, connections, and routing paths. You can also make assignment changes, such as creating and deleting resource assignments.

To open the Chip Planner, click Tools > Chip Planner.
Static Timing Analysis
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Static Timing Analysis | Report Timing | Timing Analyzer |
The Intel® FPGA Timing Analyzer is an easy-to-use, second-generation, ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format.

The major difference between performing timing analysis with the Report Timing Summary in Vivado® and the Intel® FPGA Timing Analyzer is that in the Vivado® software, a change in timing constraint triggers a recompile. In contrast, the Timing Analyzer GUI allows you to experiment with timing constraints and timing model without recompiling.
Access
Static timing analysis with the Timing Analyzer is part of the full compilation flow, but you can also run the module separately.
To run the Timing Analyzer over a post-fit netlist, click Processing > Start > Start Timing Analyzer .
To open the Timing Analyzer GUI, click Tools > Timing Analyzer .
Generation of Device Programming Files
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Generation of Device Programming Files | Hardware Manager | Assembler |
Features
The Assembler converts the Fitter’s device, logic cell, and pin assignments into a programming image for the device, in the form of one or more Programmer Object Files (.pof) or SRAM Object Files (.sof) for the target device. You use a .sof file to program Intel® FPGA devices and a .pof file to configure Intel® FPGA CPLD devices.
Assembler is a stage of the Intel® Quartus® Prime Pro Edition full compilation flow. You can also run Assembler separately, by clicking Processing > Start > Start Assembler.
Power Analysis
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Power Analysis |
Xilinx® Power Estimator (XPE) Report Power |
Early Power Estimation (EPE) Power Analyzer |
The EPE is a spreadsheet tool that helps you estimate power consumption at early design concept. You download the EPE tool from the Early Power Estimators (EPE) and Power Analyzer page in the Altera website.
The Intel® Quartus® Prime Pro Edition Power Analyzer tool performs post-fitting power analysis and generates a report that details power consumption of the design by block type and entity. To open the Power Analyzer tool, click Processing > Power Analyzer Tool.
Simulation
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Simulation | Vivado® Simulator | ModelSim® - Intel® FPGA Starter Edition |
Third-Party Simulation Tools | Third-Party Simulation Tools |
Access
- Click Assignments > Settings.
- In Category, click EDA Tool Settings.
- Under Simulation select the simulation tool.
You can also specify third-party simulation tools in the New Project Wizard.
Simulation Models for Designs Containing LPMs or IP Cores
Functional Simulation
The Intel® Quartus® Prime Pro Edition software provides functional simulation models that allow you to perform functional/behavioral simulation on designs containing LPMs or Intel® FPGA IP cores.
Verilog HDL | VHDL | |
---|---|---|
LPM | 220model.v |
220pack.vhd 220model.vhd |
Intel® FPGA IP cores | altera_mf.v |
altera_mf.vhd altera_mf_components.vhd |
Gate-level Functional Simulation
To perform gate-level functional simulation on a design, the Intel® Quartus® Prime Pro Edition software generates output netlist files containing information about how the design was placed into device-specific architectural blocks.
Extension | |
---|---|
Verilog HDL output file | .vo |
VHDL output file | .vho |
You can perform simulations with pre-compiled model libraries by using the ModelSim® - Intel® FPGA Edition simulator included in the Intel® Quartus® Prime Pro Edition software. You can also compile your own selection of model libraries with the Simulation Library Compiler tool in the Intel® Quartus® Prime Pro Edition software.
Hardware Verification
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Hardware verification | Hardware Manager | System Console |
Integrated Logic Analyzer (ILA) and System ILA IP | Signal Tap Logic Analyzer | |
Xilinx® Virtual Input Output (VIO) | In-System Sources and Probes | |
JTAG-to-AXI Master | System Console | |
IBERT IP and Serial I/O Analyzer Tool | Transceiver Toolkit | |
Memory Calibration Debug Tool |
EMIF Debug Toolkit EMIF Debug GUI |
|
Remote Debug using Xilinx® Virtual Cable (XVC) | Remote Debug using existing TCP/IP connection | |
- |
Signal Probe 18 In-System Memory Content Editor Logic Analyzer Interface (LAI) |
System Console
Xilinx® Vivado® software's Hardware Manager provides a TCL console to interact with the debug IP on the hardware. Similarly, in the Intel® Quartus® Prime Pro Edition Software, you can perform the same tasks using the System Console.
Features | Typical Usage |
---|---|
|
You need to perform system-level debugging. For example, if you have an Avalon® -MM slave or Avalon® -ST interfaces, you can debug the design at a transaction level. |
Signal Tap Logic Analyzer
Features | Typical Usage |
---|---|
|
You have spare on-chip memory and you want functional verification of a design running in hardware. |
In-System Sources and Probes
Features | Typical Usage |
---|---|
Provides an easy way to drive and sample logic values to and from internal nodes using the JTAG interface. | You want to prototype the FPGA design using a front panel with virtual buttons. |
Transceiver Toolkit
The Vivado® software uses IBERT IP along with the serial I/O analyzer tool to evaluate and monitor the transceivers in UltraScale® devices. In the Intel® Quartus® Prime Pro Edition software, the Transceiver Toolkit allows you to check and improve signal integrity of high-speed serial links in Intel® FPGAs.
Features | Typical Usage |
---|---|
|
You need to debug or optimize signal integrity of a board layout even before finishing the design. |
EMIF Debug Toolkit
Features | Typical Usage |
---|---|
|
You want to debug hardware failures by accessing information gathered during calibration. |
Remote Debugging
- For information about setting up a Nios® II system with the System Console to perform remote debugging, refer to Application Note 624
- For information about setting up an Intel FPGA SoC to perform remote debugging with the Intel® Quartus® Prime SLD tools, refer to Application Note 693.
Other Intel FPGA Debugging Tools
Signal Probe
Features | Typical Usage |
---|---|
Incrementally routes internal signals to I/O pins while preserving results from the last place-and-routed design. | You have spare I/O pins and you want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope. |
Logic Analyzer Interface
Features | Typical Usage |
---|---|
|
You have limited on-chip memory and a large set of internal data buses to verify using an external logic analyzer. Logic analyzer vendors, such as Tektronics® and Agilent®, provide integration with the tool to improve usability. |
In-System Memory Content Editor
Features | Typical Usage |
---|---|
Displays and allows you to edit on-chip memory. |
You want to view and edit the contents of on-chip memory that is not connected to a Nios® II processor. You can also use the tool when you do not want to have a Nios® II debug core in your system. |
View Netlist
Similar to the Netlist Window and Schematic Window features available in the Vivado® software to generate logical or physical hierarchy, the Intel® Quartus® Prime Pro Edition RTL Viewer and Technology Map Viewer provide powerful ways to view initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
View Netlist |
Schematic Window (Elaborated) Schematic Window (Synthesized) Schematic Window (Implemented) |
RTL Viewer (Post Synthesis) Technology Map Viewer (Post-Mapping) Technology Map Viewer (Post-Fitting) Fast Forward Viewer (Post-Fitting) |
RTL Viewer
- Click Processing > Start > Start Analysis & Elaboration to generate a RTL netlist
- To open the RTL Viewer, click Tools > Netlist Viewers (RTL Viewer).
Alternatively, you can perform a full compilation on any Intel® Quartus® Prime Pro Edition flow that includes the initial Analysis and Elaboration stage.
Technology Map Viewer
The Technology Map Viewer is a detached window that provides a graphical representation of the schematic. To run the Technology Map Viewer for an Intel® Quartus® Prime Pro Edition project:
- Click Processing > Start > Start Analysis & Synthesis to synthesize and map the design to the target technology.
- Click Tools > Netlist Viewers > Technology Map Viewer (Post-Mapping) to view the post mapping netlist.
-
Click Processing > Start > Start Fitter.
After completing the Fitter stage, the Technology Map Viewer displays how the Fitter modified the netlist as a result of optimizations. After completing the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.
- Click Tools > Netlist Viewers > Technology Map Viewer (Post-Fitting) to view the post fitting netlist.
To find cells by name, click Edit > Find, type the cell name, and click List.
Design Optimization
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Design Optimization | - | Hyper-Aware Design Flow19 |
Physical Optimization | Physical Synthesis Optimization |
Hyper-Aware Design Flow
Use the Hyper-Aware design flow to shorten design cycles and optimize performance for designs targeting Intel® Stratix® 10 devices. The Hyper-Aware design flow combines automated register retiming (Hyper-Retiming), with implementation of targeted timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for Intel® Stratix® 10 designs.
Physical Synthesis Optimization
- Optimizations that occur during the synthesis stage change the netlist to improve either area or speed, depending on the optimization technique and effort level that you select.
- Technology mapper optimizes the design to achieve maximum speed performance, minimum area usage, or balances high performance and minimal logic usage, according to the setting of the Optimization Technique option. You can set this option to Speed or Balanced.
- Optimizations that occur during the Fitter stage of the Intel® Quartus® Prime Pro Edition compilation flow make placement-specific changes to the netlist that improve speed performance results for a specific Intel® FPGA device
To view and modify synthesis netlist optimization options:
- Click Assignments > Settings > Compiler Settings.
- To enable physical synthesis, click Advanced Settings (Fitter), and then enable Advanced Physical Synthesis.
- View physical synthesis results in the Netlist Optimizations report.
Techniques to Improve Productivity
GUI Feature | Xilinx® Vivado® Software | Intel® Quartus® Prime Pro Edition Software |
---|---|---|
Techniques to improve productivity | Incremental Compile | Rapid Recompile20 |
Hierarchical Design | Block-Based Design Flows | |
- | Design Space Explorer II (DSE) |
Rapid Recompile
In Xilinx® Vivado® designs, the Incremental Compile design flow speeds up place and route runtime. For reduced compilation time, the Intel® Quartus® Prime Pro Edition provides Rapid Recompile.
Block-Based Design Flow
In the Vivado® software, the Hierarchical Design flow allows you to partition a design into smaller modules that you process independently. These flows are based on the ability to implement a partitioned module out-of-context (OOC) from the rest of the design. A similar feature in Intel® Quartus® Prime Pro Edition software is the Block-Based Design Flow, which supports preservation and reuse of design blocks in one or more projects.
The Block-Based Design Flow allows you to reuse synthesized, placed, or final design blocks within the same project, or export the block to other projects. Reusable design blocks can include device core or periphery resources.
You can define a logical design partition in a project, and then empty, preserve, or export the contents of that design partition after compilation. The Intel® Quartus® Prime Pro Edition software supports the following block-based design flows:
- Incremental Block-Based Compilation—preserve or empty a core design partition within a project. This flow works only with core resources, and requires no additional files or floorplanning. You can empty the partition, or preserve it at synthesis, placement, or final compilation stages.
- Design Block Reuse—export a core or periphery design partition and reuse it in another project. Core partition reuse preserves the placement and routing of timing-critical modules with specific optimized functionality or algorithms, such as modules for encryption, encoding, image processing, or other functions. Periphery partition reuse preserves the placement and routing of the periphery.
Xilinx® Hierarchical Design Flows | Intel® Quartus® Prime Pro Edition Block-Based Design Flows | Description |
---|---|---|
Bottom-Up Reuse | Design Block Reuse | Build a verified module (such as a piece of IP) which is placed, routed and you can reuse in other designs. |
Top-Down Reuse | Periphery Reuse | Build a verified top-level design with details about the pinout, floorplan and timing requirements. |
For more information about design planning and different design approaches, refer to Block-Based Design Flows in the Intel® Quartus® Prime Pro Edition Handbook Volume 1 .
Design Space Explorer II
Design Space Explorer II (DSE II) processes a design using combinations of setting and constraints, and reports the best settings for the design. DSE II attempts multiple seeds to identify one meeting your requirements. DSE II can compile on multiple computers in parallel to streamline timing closure.
If the design is close to meeting timing or area requirements, you can try different seeds with the DSE II, and find one seed that meets timing or area requirements.
Cross-Probing in the Intel Quartus Prime Pro Edition Software
For example, you can locate design elements from the RTL Viewer to the Assignment Editor. This eliminates the search time for node names and pin names when applying design constraints in the Assignment Editor. To locate design elements, use the right mouse click button.
Additional Intel Quartus Prime Pro Edition Features
Scripting with Tcl in the Intel Quartus Prime Pro Edition Software
The Intel® Quartus® Prime Pro Edition software provides support for Tcl to help facilitate project assignments, compilation, and constraints.
The Intel® Quartus® Prime Pro Edition software contains Tcl application program interface (API) functions that you can use to automate a variety of common tasks, such as making assignments, compiling designs, analyzing timing, and controlling simulation. You can run your Tcl scripts in the following ways:
- Running Scripts from the DOS or UNIX Prompt
- Running Scripts in Batch Mode from a Shell
- Running Tcl Commands Directly from the Command Line
You can use the --tcl_eval option to directly evaluate the rest of the command line arguments as one or more Tcl commands. - Running Tcl Commands Interactively from the Shell
Using the -s or --shell switch option starts an interactive Tcl shell session, replacing the normal command line prompt with tcl, as shown in the following example: - The Intel Quartus Prime Tcl Console Window
Running Scripts from the DOS or UNIX Prompt
The following command runs the Intel® Quartus® Prime Tcl shell and uses the Tcl file specified by the -t option as the input Tcl script:
quartus_sh -t <script_name>.tcl
The Intel® Quartus® Prime Tcl interpreter reads and executes the Tcl commands in the Tcl script file and then exits back to the command-line prompt.
Running Scripts in Batch Mode from a Shell
You can run Tcl scripts in a Tcl shell by typing:
source <script_name>.tcl
Running Tcl Commands Directly from the Command Line
quartus_sh --tcl_eval puts Hello\; puts World
Results in the following output:
Hello World
The Tcl evaluate option allows external scripting programs (such as make, perl, and sh) to access information from the Intel® Quartus® Prime Pro Edition software. You can use these programs to obtain device family information for a targeted part.
The --tcl_eval option also provides Tcl help information directly from the command-line prompt.
Running Tcl Commands Interactively from the Shell
-
In a console, type:
quartus_sh -s
When entering the console, you get the welcome message:Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.0 Internal Build 167 08/21/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu Aug 31 12:50:32 2017 Info: ******************************************************************* Info: The Quartus Prime Shell supports all TCL commands in addition Info: to Quartus Prime Tcl commands. All unrecognized commands are Info: assumed to be external and are run using Tcl's "exec" Info: command. Info: - Type "exit" to exit. Info: - Type "help" to view a list of Quartus Prime Tcl packages. Info: - Type "help <package name>" to view a list of Tcl commands Info: available for the specified Quartus Prime Tcl package. Info: - Type "help -tcl" to get an overview on Quartus Prime Tcl usages. Info: ******************************************************************* tcl>
-
Enter any Tcl command.
The Intel® Quartus® Prime Tcl interpreter directly evaluates everything that you type in the Tcl shell.
The Tcl shell includes a history list of previously-entered commands.
The Intel Quartus Prime Tcl Console Window
You can execute Tcl commands directly in the Intel® Quartus® Prime Tcl Console window. To open the Tcl Console window, click View > Tcl Console.
Tcl Script
This example uses design files from the fir_filter tutorial in tutorial design in the <quartus-installation-directory>/qdesigns directory. The script performs these tasks:
- Opens the fir_filter project, if it exists. If the project does not exist, the script creates the project.
- Sets the project to target an Intel® Stratix® 10 1SG280HU2F50E2VG device.
- Assigns the clk pin to the physical pin AW10.
- Compiles the project.
# This Tcl file works with quartus_sh.exe # This Tcl file will compile the Quartus Prime tutorial fir_filter design # set the project_name to fir_filter # set compiler setting to filtref set project_name fir_filter set csf_name filtref # Create a new project and open it # Project_name is project name if {![project_exists $project_name]} { project_new -family Stratix10 -part 1SG280HU2F50E2VG -cmp $csf_name $project_name ; } else { project_open -cmp $csf_name $project_name; } # assign pin clk to pin location AW10 set_location_assignment -to clk PIN_AW10 # The project is compiled here package require ::quartus::flow execute_flow -compile project_close
Xilinx to Intel FPGA Design Conversion
- Replacing Xilinx® primitives with Intel® FPGA primitives, IP cores, or constraints.
- Replacing Vivado® IP Catalog modules with IP cores generated with the Intel® FPGA IP Catalog.
- Expressing timing, device, and placement constraints found in the Xilinx® design with their counterpart in the Intel® Quartus® Prime software.
- If applicable, setting up the simulation environment.
Replacing Xilinx Primitives
The following table lists common Xilinx® primitives and describes the equivalent Intel® FPGA design element.
Xilinx® Primitive | Description | Intel® FPGA Equivalent | Conversion Method |
---|---|---|---|
IBUF | Single Input Buffer | wire/signal Assignment | HDL |
OBUF | Single Output Buffer | wire/signal Assignment | |
BUFG | Global Clock Buffer | wire/signal and Global Signal Assignment | HDL and Assignment Editor |
IBUFG_<selectable I/O standard> 21 | Input Global Buffer with selectable interface | wire/signal, I/O Standard, and Global Signal Assignment 22 | |
IBUF_<selectable I/O standard> 21 | Input buffer with selectable interface | wire/signal and I/O Standard Assignment22 | |
IOBUF_<selectable I/O standard> 21 | Bidirectional buffer with selectable interface | wire/signal and I/O Standard Assignment22 | |
OBUFG_<selectable I/O standard> 21 | Output Global Buffer with selectable interface | wire/signal and I/O Standard Assignment22 | |
OBUF_<selectable I/O standard> 21 | Output buffer with selectable interface | wire/signal and I/O Standard Assignment22 | |
IBUFDS, OBUFDS | Differential I/O Buffer | wire/signal and I/O Standard Assignment22 | |
SRL16 | 16-bit Shift Register | AUTO_SHIFT_REGISTER_RECOGNITION | Assignment Editor |
Converting I/O Buffers
- Remove all buffer primitives from the Xilinx® design in the HDL code.
- Replace the primitives with wire or signal assignments in the HDL code.
-
In the Assignment Editor, perform assignments depending on the
type of buffer:
Type of Buffer Assignment to use Buffers with selectable I/O standard I/O Standard Global buffers Global Signal Global buffer with I/O Standard I/O Standard
Example of Converting I/O Buffer
Converting BUFG, IBUFG, and OBUF in Verilog HDL.
Original Verilog HDL Code in the Vivado® Software
module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_buf, clk_buf; BUFG inst1 (.O (clk_buf), .I (clk)); IBUFG #("FALSE", "SSTL12") inst2 (.O (a_buf), .I (a)); IBUFG #("FALSE", "SSTL18_I") inst3 (.O (b_buf), .I (b)); OBUF inst4 (.O (c), .I (c_buf)); always @ (posedge clk_buf) c_buf <= a_buf & b_buf; endmodule
Converted Verilog HDL Code in the Intel® Quartus® Prime Pro Edition Software
module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_buf, clk_buf; assign clk_buf = clk; assign a_buf = a; assign b_buf = b; assign c = c_buf; always @ (posedge clk_buf) c_buf <= a_buf & b_buf; endmodule
Converting BUFG, IBUFG, and OBUF in VHDL.
Original VHDL Code in the Vivado® Software
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY buf_top IS PORT( a, b : IN STD_ULOGIC; clk : IN STD_ULOGIC; c : OUT STD_ULOGIC); END buf_top; ARCHITECTURE Behave OF buf_top IS SIGNAL a_buf, b_buf, c_buf, clk_buf : STD_ULOGIC; COMPONENT BUFG PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; COMPONENT IBUFG generic(IBUF_LOW_PWR : boolean := FALSE; IOSTANDARD : String := "DEFAULT"); PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; COMPONENT OBUF PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; BEGIN inst1 : BUFG PORT MAP (O => clk_buf, I => clk); inst2 : IBUFG generic map( IBUF_LOW_PWR => FALSE, IOSTANDARD => "SSTL12") PORT MAP (O => a_buf,I => a); inst3 : IBUFG generic map( IBUF_LOW_PWR => FALSE, IOSTANDARD => "SSTL18_I") PORT MAP (O => b_buf, I => b); inst4 : OBUF PORT MAP (O => c, I => c_buf); PROCESS(clk_buf) BEGIN IF (clk_buf'event and clk_buf = '1') THEN c_buf <= a_buf AND b_buf; END IF; END PROCESS; END Behave;
Converted VHDL Code in the Intel® Quartus® Prime Pro Edition Software
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Top IS PORT( a, b: IN STD_ULOGIC; clk: IN STD_ULOGIC; c: OUT STD_ULOGIC); END Top; ARCHITECTURE Behave OF Top IS SIGNAL a_buf, b_buf, c_buf, clk_buf: STD_ULOGIC; BEGIN PROCESS (a, b, c_buf, clk) BEGIN clk_buf <= clk; a_buf <= a; b_buf <= b; c <= c_buf; END PROCESS; PROCESS(clk_buf) BEGIN IF (clk_buf'event and clk_buf = '1') THEN c_buf <= a_buf AND b_buf; END IF; END PROCESS; END Behave;
To set the ports with specific assignments in the Intel® Quartus® Prime Pro Edition software, use the Assignment Editor.

In the figure, inputs a, b, and clk are assigned as global signals, with clk as the global clock. Input ports a and b are assigned with specific I/O standards, while other ports are automatically assigned with the device-specific default I/O standard.
Changing Default I/O Standard for Pins
The default I/O standard for pins on the target device in the Intel® Quartus® Prime Pro Edition software is device-specific. To change the default I/O standard:
- Click Assignments > Device.
- On the Device dialog box, click Device and Pin Options.
- In the Category list, select Voltage and then select the desired I/O standard.
Converting IP Cores
Converting Memory Blocks
To convert Xilinx® memory blocks to Intel® FPGA memory blocks, you must consider the embedded memory blocks in the target device, address the differences between memories in Intel® FPGA and Xilinx® devices, and perform port mapping.
- Single Port RAM
- Simple Dual Port RAM
- True Dual Port RAM
- Single Port ROM
- Dual Port ROM
For information about memory blocks present in Intel® FPGA devices, refer to the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide or the Intel® Stratix® 10 Embedded Memory User Guide .
Embedded Memory Blocks
The following table lists the memory blocks that Intel FPGA devices support:
Device | Types of Memory Blocks |
---|---|
Intel® Arria® 10 and Intel® Stratix® 10 | MLAB blocks M20K blocks |
For information about memory features and memory specification, refer to the appropriate Embedded Memory Blocks chapter for the target device.
Differences Between Xilinx Memory and Intel FPGA Memory
Memory Mode
Xilinx® memory and Intel® FPGA memory support single-port RAM, simple dual-port RAM, true dual-port RAM, single-port ROM, and dual-port ROM.
In addition, Intel® FPGA supports simple quad-port RAM, which allows user to perform two read and two write operations to different locations in a single clocking mode. Xilinx® memory does not have a built-in simple quad-port RAM.
Clocking Mode
In Intel® FPGAs, the clock mode depend on which embedded memory block you select:
Intel® FPGA Clocking Mode | Description | Comment | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Single | All ports share the common clock. | ||||||||||
Input/output | A separate clock is available for input ports and output ports. |
Xilinx® memories do not differentiate these two clocking modes. However, the clocking mode behavior with simple dual-port RAM can be identical to Intel® FPGA clocking mode in the following situations:
|
|||||||||
Read/write | A separate clock is available for read ports and write ports. |
For more information about supported clocking modes, refer to the Intel® Stratix® 10 Embedded Memory User Guide.
Write and Read Operation Triggering
Ensure to resolve potential write contentions external to the RAM, because writing to the same address location at both ports results in unknown data storage at that location. Therefore, knowing when the write operation was triggered is crucial.
The write operation in Intel® FPGA memory can occur at either falling clock edges or rising clock edges, depending on the type of embedded memory block. To avoid delta delay, do not trigger control signals together with clock signals.
Read-During-Write Operation at the Same Address
There are two types of read-during-write operations: same-port operations and mixed-port operations.
- a single-port RAM
- the same port of a true-dual port RAM
- the same port a of simple quad-port RAM
- simple-dual port
- true-dual port
- simple-quad port mode
Intel® FPGA RAM and Xilinx® RAM support both read-during-write port modes. However, they have different output options. These options vary depending on the operation mode and type of embedded memory block or device that you select.
Intel® FPGA RAMs support configurations with output options of NEW_DATA (flow-through), OLD_DATA, DONT_CARE, or NEW_A_OLD_B. Xilinx® RAMs support configurations with output options READ_FIRST, WRITE_FIRST, or NO_CHANGE.
Description | Output after Read-During-Write operation | Types of RAM Output | |
---|---|---|---|
Xilinx® | Intel® FPGA | ||
Output reflects the new data at that address. | New data | WRITE_FIRST | NEW_DATA |
Outputs reflect the old data at that address before the new data is written into memory. | Old data | READ_FIRST | OLD_DATA |
Outputs reflect the previous read data and remains unaffected by the write operation. | Unaffected | NO_CHANGE | Not supported23 |
Read-during-write writes new data into memory, and the output displays unknown values. | Unknown | Not supported | DONT_CARE 24 |
For simple quad port, the
read-during-write operation behaves differently for each port:
|
Port A: New data Port B: Old data |
Not supported | NEW_A_OLD_B |
In Intel® FPGA RAMs, the output choices depend on the operation mode and the type of embedded memory block. For information about output choices for same-port and mixed-port read-during-write modes, refer to the Embedded Memory Blocks chapter in the corresponding device handbook.
Error Correction Code (ECC)
Xilinx® and Intel® FPGA RAMs use Error Correction Code (ECC) to detect errors in the memory array, and present the corrected single-bit error data on the output.
Intel® FPGA | Xilinx® | |
---|---|---|
ECC support |
|
For UltraScale+® and 7-series devices in simple dual-port RAM. |
Status Signal | Indicates the status of the M20K block using a three-bit status flag eccstatus[1..0] | Indicates the status of the data read using two status
outputs:
|
ECC Parity Flip ( Intel Stratix® 10 Devices only)
When the ECC Encoder Bypass (eccencbypass) port is high, the built-in ECC encoder values are XOR-ed with the 8 parity bits through the parity ports to generate a new set of encoder value. When the ECC Encoder Bypass port is low, the encoder generates the parity bits according to the data input during a write process.
The following table shows an example to construct an 8-bit data width for the parity port.
Parity Bit Sequence | ECC Feature | Is the ECC Decoder able to Recognize and Correct the Data Bit? |
---|---|---|
00000001 | Single-error correction | Yes |
00000001 | Double-adjacent-error correction | Yes |
00000111 | Triple-adjacent-error correction | Yes |
00000101 | Triple-adjacent-error correction | Yes |
00010011 | Non-adjacent double/triple correction/detection | No guarantee |
For more information about ECC, refer to the chapter about Embedded Memory Blocks in your target device handbook.
Byte Enable
The following table compares byte enable implementation in Xilinx® and Intel® FPGA RAMs
Differences | Xilinx® RAM | Intel® FPGA RAM | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Controlling signals |
The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. |
Uses two signals, write_enable and byte_enable. To control which byte to write, assert the write_enable signal and the specific bit of the
byte_enable signal. For example, in a RAM
block in x16 mode:
|
|||||||||
Input data width support | Support multiples of 8 or 9 bits. | Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation.25 | |||||||||
Output value of masked byte when performing read-during-write to the same location. | Output depends on read-during-write
configuration:
|
Output depends on the type of memory block:
|
Address Clock Enable
Intel® FPGA memory supports the address clock enable feature. The address clock enable holds the previous address value for as long as addressstall is enabled. Xilinx® RAM blocks support an equivalent feature, called Address Enable.
For more information about the address clock enable feature, refer to the Embedded Memory Blocks chapter in your target device handbook.
Parity Bit Support
Embedded memory blocks in Intel® FPGAs have built-in parity-bit support for each byte. While Xilinx® memories support separate input and output buses for parity bits, the embedded memory blocks in Intel® Stratix® 10 devices allow you to inject parity bits through the ECC encoder bypass feature.
The amount of memory in each RAM block includes the parity bits. No parity function is actually performed on the parity bits. You can use the parity bits for purposes other than ensuring data integrity; for example, to store user-specified control bits.
For more information about using the parity bit to detect memory errors, refer to the Using Parity to Detect Errors White Paper.
Memory Initialization
In Intel® FPGA devices, all embedded memory blocks support memory initialization, and initialize memory contents through memory initialization files (.mif) or Hexadecimal ( Intel® -Format) files (.hex). You can create these files with the Intel® Quartus® Prime Pro Edition software. You specify the initialization file name while configuring your memory IP core through the IP Catalog/Parameter Editor.
Xilinx® devices use a memory coefficient (COE) file for initialization. Alternatively, you can use the default data option
Output Synchronous Set/Reset
Xilinx® memory supports optional synchronous set/reset pins that control the reset operation of the last register in the output stage. This ability initializes the memory's output to a user-defined value.
Intel® FPGA memory also supports asynchronous clear and synchronous clear on output latches and output registers. If the RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear (aclr). The aclr signal is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the aclr signal asserts, the outputs are cleared and stay clear until the next read cycle.
Determining Memory Block and Mapping Ports
-
If you are not sure which memory block to select, or are not
particular about the memory block type, select AUTO in the IP Catalog/Parameter
Editor.
This option allows the Intel® Quartus® Prime software to determine the memory block type at compile time.
- To find the type of memory block that the Intel® Quartus® Prime software assigned to your design, check the Intel® Quartus® Prime Fitter RAM Summary Report.
-
Otherwise, build the memory blocks in the IP Catalog/Parameter Editor using
the proper plug-in.
The available plug-ins are:
Table 45. Memory Modes/Functions and Related Plug-In Memory Modes/Function Plug-In Single-port RAM RAM:1-PORT Simple dual-port RAM RAM:2-PORT True dual-port RAM RAM:2-PORT Simple quad-port RAM ( Intel® Stratix® 10 only) RAM:4-PORT Single-port ROM ROM:1-PORT Dual-port ROM ROM:2-PORT For information about memory options, and how to build the memory function through the IP Catalog/Parameter Editor, refer to the embedded memory user guide.
- Identify the port-mapping from Xilinx® memory ports to Intel® FPGA memory ports.
Memory Port Mapping
The following table lists the memory ports that the Vivado® ’s IP Catalog generates, and their corresponding mapping to Intel® FPGA memory ports for different memory modes.
Port Description | Xilinx® Ports | Port-Mapping to Intel® FPGA Ports in Different Memory Modes | ||||
---|---|---|---|---|---|---|
Single-Port RAM | Simple Dual-Port RAM | True Dual-Port RAM | Single-Port ROM | Dual-Port ROM | ||
Port A: address | addra | address | wraddress | wraddress/ address_a | address | address_a |
Port A: data input | dina | data | data | data/ data_a | — | — |
Port A: parity data input | dinpa | — | ||||
Port A: clock enable for the input register | ena | inclocken/ clken | inclocken/ wrclocken/ enable | inclocken/ wrclocken/ enable | inclocken/ clken | enable |
Port A: clock enable for the last output register | regcea, ena | outclocken/ clken | enable | outclocken/ enable | outclocken/clken | enable |
Port A: write enable | NA | wren | wren | wren/ wren_a | NA | NA |
Port A: byte enable26 | wea | byteena | byteena_a | byteena_a | NA | NA |
Port A: asynchronous clear | NA | outaclr/ aclr | NA | out_aclr/ rd_aclr/ aclr | outaclr/aclr | aclr |
Port A: synchronous set/reset | rsta/ rstrega | sclr | NA | sclr | sclr | sclr |
Port A: read enable | ena (in SDP 27 mode) | rden | NA | rden_a/ rden | rden | rden_a |
Port A: in clock | clka | inclock/ clock | inclock/ wrclock/ clock | inclock/ wrclock/ clock | inclock/ clock | clock |
Port A: out clock | NA | outclock/ clock | NA | NA | outclock/ clock | NA |
Port A: data output | douta | q | NA | q/ q_a | q | q_a |
Port A: parity data output | doutpa | — | ||||
Port A: address enable | addrena 28 | addressstall_a | wr_addressstall | wr_addressstall/ addressstall_a | addressstall_a | addressstall_a |
Port B: address | addrb | NA | rdaddress | rdaddress/ address_b | NA | address_b |
Port B: data input | dinb | NA | NA | data_b | NA | NA |
Port B: parity data input | dinpb | — | ||||
Port B: clock enable for the input register | enb | NA | NA | inclocken/enable | NA | enable |
Port B: clock enable for the last output register | regceb, enb | NA | outclocken/ rdoutclocken | outclocken/enable | NA | enable |
Port B: write enable | enb (in SDP27 mode) | NA | NA | wren_b | NA | NA |
Port B: byte enable | web | NA | NA | byteena_b | NA | NA |
Port B: asynchronous clear | — | NA | out_aclr/ rd_aclr/ aclr | rd_aclr/ out_aclr | NA | aclr |
Port B: synchronous set/reset | rstb/ rstregb | NA | sclr | sclr | NA | sclr |
Port B: read enable | — | NA | rden | rden_b | NA | rden_b |
Port B: clock | clkb | outclock/ clock | outclock/ rdclock/ clock | outclock/ rdclock | outclock/ clock | clock |
Port B: data output | doutb | NA | q | q/ q_b | NA | q_b |
Port B: address enable | addrenb | NA | rd_addressstall | rd_addressstall/ addressstall_b | NA | addressstall_b |
Port B: parity data output | doutpb | — | ||||
Single bit error | sbiterr | NA | eccstatus[1:0] | NA | NA | NA |
Double bit error | dbiterr | NA | NA | NA | NA | |
ECC encoder bypass port | ‒ | NA | eccencbypass | NA | NA | NA |
ECC parity flip port | ‒ | NA | eccncparity[7:0] | NA | NA | NA |
Inject single bit error | injectsberr | NA | ||||
Inject double bit error | injectdbiterr | NA |
You can also infer RAM in HDL. For more information, refer to the Recommended HDL Coding Styles in the Intel® Quartus® Prime Pro Edition Handbook Volume 1.
Example: Converting Simple Dual-Port RAM
In this example, the top-level entity test instantiates sdp_ram, a Xilinx® simple dual-port RAM generated through Block Memory Generator, with the following properties:
Input data width | 16 bits |
Memory depth | 8 words |
Clocking Mode | Different input and output clocks |
ECC feature | Selected |
Out data registered status | Output registered (one stage pipeline) |
Read-during-write | WRITE_FIRST (New Data) |
The original Verilog HDL Code in the Vivado® Software is:
module test( input clka, input ena, input [0:0]wea, input [2:0]addra, input [15:0]dina, input clkb, input enb, input [2:0]addrb, output [1 5:0]doutb, output sbiterr, output dbiterr, output [2:0]rdaddrecc); simple dual port ip i1( .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .clkb(clkb), .enb(enb), .addrb(addrb), .doutb(doutb), .sbiterr(sbiterr), .dbiterr(dbiterr), .rdaddrecc(rdaddrecc)); endmodule
The original VHDL Code in the Vivado® Software is:
LIBRARY ieee; USE ieee.STD_LOGIC 1164.all; LIBRARY work; ENTITY test IS port ( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; enb: IN STD_LOGIC; addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END test; ARCHITECTURE arch OF test IS component simple dual port ip PORT( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; enb: IN STD_LOGIC; addrb: IN STD_LOGIC VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC vector ( 2 DOWNTO 0) end component; BEGIN il: simple_dual_port_ip PORT MAP( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, clkb => clkb, enb => enb, addrb => addrb, doutb => doutb, dbiterr => dbiterr, sbiterr => sbiterr, rdaddrecc => rdaddrecc); END;
To convert a Xilinx® Simple Dual Port RAM to Intel® FPGA:
- Create an Intel® FPGA simple dual-port RAM through the Intel® Quartus® Prime software IP Catalog/Parameter Editor.
-
Configure the RAM with the following options:
Table 48. Parameters of Simple Dual-Port RAM How will you be using the dual port RAM? Specifies how you use the dual port RAM. With one read port and one write port Read/Write Ports Specifies the width of the input and output ports. How wide should the 'q_a' output bus be? 16 bits How wide should the 'q_b' output bus be? 16 bits What should the memory type be? Specifies the memory block type. The available memory blocks depend on the target device. RAM Block Type M20K What clocking method do you want to use? Specifies the clocking method to use. Dual clock: use separate ‘read’ and ‘write’ clock A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers. ECC Checking Enable Error Correction Check (ECC) On Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory Enable ECC Pipeline Registers On Specifies whether to enable the ECC pipeline registers before the output decoder to achieve that same performance as non-ECC mode at the expense of one cycle of latency Clock Enables Specifies whether to create clock enables for read and write registers. Use different clock enables for registers On Use clock enable for write input registers On Use clock enable for output registers On Note: Intel® FPGA RAMs do not support read-during-write ‘old data’ mode when the ECC feature is enabled. Therefore, when you convert a Xilinx® RAM to an Intel® FPGA RAM, you can expect to see a ‘don't care’ value when read-during-write to the same address occurs. The workaround to get the read-during-write ‘old data’ mode behavior is to add additional logic to retain its previous read data when read-during-write to the same address occurs. -
Instantiate the new
Intel®
FPGA RAM. to replace the
Xilinx®
RAM.
The converted Verilog HDL code in the Intel® Quartus® Prime Software after instantiating the new RAM:
module test( input clka, input ena, input [0:0]wea, input [2:0]addra, input [15:0]dina, input clkb, input enb, input [2:0]addrb, output [15:0]doutb, output sbiterr, output dbiterr, output [2:0]rdaddrecc); simple_dual_port_ip i1( .wrclock (clka), .wrclocken (ena), .wren (wea), .wraddress (addra), .data (dina), .rdclock (clkb), .rdoutclocken (regceb | enb), .rdaddress (addrb), .q (doutb), .eccstatus ({dbiterr, sbiterr}) ); endmodule
The converted VHDL code in the Intel® Quartus® Prime Software:
LIBRARY ieee; USE ieee.STD_LOGIC_1164.all; LIBRARY work; ENTITY test IS port ( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; end: IN std_Iogic; addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END test, ARCHITECTURE arch OF test IS component simple_dual_port_ip PORT( wrclock: IN STD_LOGIC; wrclocken: IN STD_LOGIC; wren: IN STD_LOGIC_VECTOR(0 DOWNTO 0); wraddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0); data: IN STD_LOGIC_VECTOR(15 DOWNTO 0); rdclock: IN STD_LOGIC; rdaddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); eccstatus: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); end component; signal eccstatus_o: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN dbiterr <= eccstatus_o(1); sbiterr <= eccstatus_o(0); i1: simple_dual_port_ip PORT MAP( wrclock => clka, wrclocken => ena, wren => wea, wraddress => addra, data => dina, rdclock => clkb, rdaddress => addrb, q => doutb, eccstatus => eccstatus_o); END;
Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL)
You can convert MMCMs to PLLs in Intel® FPGA devices with the IP Catalog/Parameter Editor by using the Intel® FPGA IOPLL IP core, which allows you to create custom PLLs targeting to Intel® FPGA devices.
Xilinx® MMCMs require specific input buffers to feed into the source clock port; for example, IBUF, IBUFG, or BUFGMUX. In contrast, PLLs in Intel® FPGA devices do not require input buffers when using the IP Catalog/Parameter Editor.
Feature Comparison
The following table compares MMCM features in UltraScale+® with PLL features in Intel® Stratix® 10 devices.
Features |
Xilinx®
MMCM ( UltraScale+® ) |
Intel®
FPGA
IOPLL
( Intel® Stratix® 10) |
|
---|---|---|---|
Frequency Synthesis | Clock Multiplication and Division | Yes | Yes |
Phase Shifting | Yes | Yes | |
Clock Duty Cycle | Yes | Yes | |
MMCM Deskew Adjust | Internal Feedback | Yes | |
Spread Spectrum | Yes | Yes | |
System Synchronous Normal Mode |
Yes | Yes | |
Source Synchronous | Yes | Yes | |
Zero Delay Buffer | Yes | Yes | |
No Compensation | Yes (CMT to CMT connection) | Yes (Direct compensation)29 | |
External Feedback | Yes | Yes | |
Others | Input Clock Switchover | Yes | Yes |
Dynamic re-configuration | Yes | Yes | |
Single or Differential Clock Inputs | Yes | Yes |
Port Mapping Reference
The following table shows the mapping between MMCM UltraScale® ports, created with the Xilinx® IP Catalog, and PLL ports in Intel® Stratix® 10 device, created with the IP Catalog.
Xilinx® MMCM Core Port | Intel® FPGA Intel® FPGA IOPLL IP Core Port | Description |
---|---|---|
clk_in1 | refclk | First clock input |
clk_in2 | refclk1 | Second clock input |
clkfb_in | fbclk | External clock feedback |
clkfbout | fboutclk | Feeds into the feedback port |
— | activeclk | Output signal that indicates which reference clock source the I/O PLL uses |
clk_in_sel | extswitch | Switch between input clock ports |
reset | rst | Asynchronous reset port |
clk_out1, clk_out2, clk_outX | outclk_[] | Clock frequency output ports. Xilinx® MMCM has fixed settings for most outputs, and you can configure the Intel® FPGA IOPLL IP core to suit them. |
clkinstopped | clkbad[1..0] | Indicates whether the clock input signal stopped switching |
clkfb_stopped | — | Specifies whether the feedback clock stopped |
locked | locked | Specifies whether the PLL is locked |
— | adjpllin | Input signal that feeds from upstream I/O PLL |
— | cascade_out | Output signal that feeds into downstream I/O PLL |
— | zdbfbclk |
Bidirectional port that connects to the mimic circuitry. You connect this port to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL. The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode. |
Xilinx® MMCM Core Port | Dynamic Phase Shift Ports in Intel® FPGA IOPLL | Description |
---|---|---|
psclk | scanclk | Specifies clock that drives the dynamic phase shift operation |
psen | phase_en | Start dynamic phase-shift operation |
psincdec | updn | Specifies direction of phase shift operation |
— | cntsel | Specifies counter for dynamic phase shift operation |
— | num_phase_shift | Specifies number of phase shifts per dynamic phase shift operation |
psdone | phase_done | Specifies completion of dynamic phase shift operation |
power_down | — | Enables power_down input port for user selection |
For more information about using dynamic PLL reconfiguration, refer to the Phase-Locked Loops ( Intel® FPGA IOPLL) IP Core User Guide.
Example: Converting Xilinx MMCM into an Intel PLL
This example uses a mymmcm module generated with the Xilinx® IP Catalog. The top module instantiates the mymmccm module with i1. The parameters are:
Parameter | Value |
---|---|
Input Clock Frequency | 100 MHz |
Clock frequency output port clk_out1 | Divide by 2 (50 MHz). |
Clock frequency output port clk_out2 | Multiply by 4 (400 MHz). |
module top( // Clock out ports output clk_out1, output clk_out2, // Status and control signals input reset, output locked, // Clock in ports input clk_in1 ); mymmcm i1 ( .reset(reset), .clk_in1(clk_in1), .locked(locked), .clk_out1(clk_out1), .clk_out2(clk_out2) ); endmodule
To recreate the same behavior using Intel® FPGA software:
-
In the IP Catalog/Parameter Editor, point to Library > Basic Functions > Clocks, PLLs and Resets > PLL, and double-click
Intel®
FPGA
IOPLL.
Figure 13. Intel® FPGA IOPLL on IP Catalog
- Generate an IP variant named mypll.
-
In the Parameter Editor, set the following parameters:
Table 52. Parameters of mypll General Reference Clock Frequency 100 MHz Output Clocks Number of Clocks 2 Specifies the number of clocks that your design requires outclk0 Clock Name clk_out11 Desired Frequency 50 MHz outclk1 Clock Name clk_out2 Desired Frequency 400 MHz - Click Finish.
- Create a top module, and instantiate the mypll module with i1.
module top(output clk_out1, output clk_out2, input reset, output locked, input clk_in1); mypll i1(.rst(reset), .refclk(clk_in1), .locked (locked), .outclk_0 (clk_out1), .outclk_1(clk_out2)); end module
Converting Multipliers
- The LPM_MULT IP core, which performs multiply functions only.
- The Intel® FPGA Multiply Adder IP core, which performs multiply, multiply-add, or multiply-accumulate functions.
- In the original code, identify whether the dataa and datab ports have the same sign.
- If the ports have the same sign, replace the Xilinx® Multiplier Core with the LPM_MULT IP core,
- Otherwise, replace with the Intel® FPGA Multiply Adder IP core.
- In the IP Catalog, click the selected IP core.
- Assign the parameters and generate HDL Intel® FPGA IP core.
Feature Comparison
- In the LPM_MULT IP core, the dataa and datab ports must have the same sign. If your design does not meet this requirement, you can use the Intel® FPGA Multiply Adder IP core to replace the Xilinx® Multiplier Core.
The following table compares the Xilinx® Multiplier Core and the Intel® FPGA LPM_MULT IP core.
Feature | Xilinx® Multiplier Core Generator Module | Intel® FPGA LPM_MULT IP Core |
---|---|---|
Constant Coefficient | Yes | Yes |
Signed and Unsigned Data | Yes | Yes |
Configurable Pipeline Latency | Yes | Yes |
Area versus Speed Trade-off | Yes | Yes |
Asynchronous Clear | — | Yes |
Synchronous Clear | Yes | Yes |
Port A and Port B support different sign | Yes | — Consider using the Intel® FPGA LPM_MULT IP core to replace the Xilinx® Multiplier Core. |
Port Mapping
The following table shows the port mapping between the Xilinx® Multiplier Core and the Intel® FPGA LPM_MULT IP core.
Xilinx® Multiplier Core Port | Intel® FPGA LPM_MULT IP Core Port | Description |
---|---|---|
A [] | dataa [] | Data Input Port A |
B [] | datab [] | Data Input Port B |
CLK [] | clock | Clock Port |
CE | clken | Clock Enable Port |
SCLR | sclr | Synchronous Clear Port |
N/A | aclr | Asynchronous Clear Port |
P [] | result [] | Multiplication Result Port |
Example: Converting to the LPM_MULT IP Core
Parameter | Value |
---|---|
Multiplier Type | Parallel multiplier where neither of the on the input buses is a constan value |
Input data width | 18 bits |
Input data type | Signed |
Output result width | Restricted to 36 bits |
Number o pipeline stages | 2 |
Implemented using Multipliers and optimized for Speed |
module top( input clk, input [17:0] a, input [17:0] b, input ce, input sclr, output [35:0] p ); mymult i1 ( .CLK(clk), .A(a), // Bus [17: 0] .B(b), // Bus [17: 0] .CE(ce), .SCLR(sclr), .P(p)); // Bus [35: 0] endmodule
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN STD_LOGIC_VECTOR(17 downto 0); sclr: IN STD_LOGIC; ce: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult PORT( CLK: IN STD_LOGIC; A: IN STD_LOGIC_VECTOR(17 downto 0); B: IN STD_LOGIC_VECTOR(17 downto 0); CE: IN STD_LOGIC; SCLR: IN STD_LOGIC; P: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult PORT MAP(CLK => clk, A => a, B => b, CE => ce, SCLR => sclr, P => p); END;
module test( input clk, input [17:0] a, input [17:0] b, input ce, input sclr, output [35:0] p ); mymult i1 ( .clock(clk), .dataa(a), // Bus [17: 0] .datab(b), // Bus [17: 0] .clken(ce), .sclr(sclr), .result(p)); // Bus [35: 0] endmodule
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN STD_LOGIC_VECTOR(17 downto 0); ce: IN STD_LOGIC; sclr: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult PORT(clock: IN STD_LOGIC; dataa: IN STD_LOGIC_VECTOR(17 downto 0); datab: IN STD_LOGIC_VECTOR(17 downto 0); clken: IN STD_LOGIC; sclr: IN STD_LOGIC; result: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult PORT MAP(clock => clk, dataa => a, datab => b, clken => ce, sclr => sclr, result => p); END;
Example: Converting to the Intel FPGA Multiply Adder IP core
The following example shows VHDL multipliers compiled in the Intel® Quartus® Prime Pro Edition Software after the conversion. The IP Catalog implements the Multiply Adder IP core by creating the mymult_add module.
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk:IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN STD_LOGIC_VECTOR(17 downto 0); ce: IN STD_LOGIC; sclr: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult_add PORT( clock0: IN STD_LOGIC; dataa_0: IN STD_LOGIC_VECTOR(17 downto 0); datab_0: IN STD_LOGIC_VECTOR(17 downto 0); ena0: IN STD_LOGIC; sclr0: IN STD_LOGIC; result: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult_add PORT MAP(clock0 => clk, dataa_0 => a, datab_0 => b, ena0 => ce, sclr0 => sclr, result => p); END;
Setting Equivalent Xilinx Design Constraints
Xilinx® designs store all the constraints and attributes in Xilinx® Design Constraint (.xdc) files, including timing and device constraints. Intel® FPGA designs use separate files for device (.qsf) and timing (.sdc) constraints. The Design Constraints section in FPGA Tools Comparison lists the appropriate GUIs to enter design constraints.
Device Constraints
The following table summarizes the most common Xilinx® device constraints and Intel® FPGA equivalent device constraints.
Xilinx® Constraint | Intel® FPGA Constraint | Description | |
---|---|---|---|
Assignment Name | QSF Variable | ||
DRIVE | Current Strength | CURRENT_STRENGTH_NEW | Controls the output pin current value |
SLEW | Slew Rate | SLEW_RATE | Turns on Fast Slew Rate Control. |
IOB | Fast Input Register Fast Output Register |
FAST_INPUT_REGISTER
FAST_OUTPUT_REGISTER |
Specifies whether the Compiler places a register in the device's IOB. |
IOSTANDARD | IO Standard | IO_STANDARD | Specifies the I/O standard for an I/O pin |
KEEP | Implement as Output of Logic Cell |
"attribute keep" (VHDL)
"synthesis keep" (Verilog) |
Prevents a net from either being absorbed by a block or synthesized out. |
To set or modify a device constraint, use the Intel® Quartus® Prime Assignment Editor. Alternatively, you can edit the .qsf file.
DRIVE
The following example shows how to set the equivalent DRIVE constraint with 12 mA to the output “q1”.
Example of XDC command:
# Set drive strength 12 mA to q1 set_property DRIVE 12 [get_ports q1];
Equivalent QSF command:
# Set drive strength 12 mA to q1 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to q1
For more information about the current strength feature in the device, refer to the specific device handbook and the Intel® Quartus® Prime Help.
SLEW
The following example shows how to set the equivalent SLEW constraint to the output “q1”.
Example of XDC command:
# set fast slew rate to q1 set_property SLEW FAST [get_ports q1]
Equivalent QSF command:
# set programmable slew rate to q1 set_instance_assignment -name SLEW_RATE 1 -to q1
For more information about the slew rate feature in the device, refer to the specific device handbook.
IOB
The following example shows how to set the equivalent IOB constraint to the input “d1” or the output “q1”.
Example of XDC command:
# Set IOB to input d1 set_property IOB TRUE [get_ports d1]; # Set IOB to output q1 set_property IOB TRUE [get_ports q1];
Equivalent QSF command:
# Set FAST_INPUT_REGSITER to input d1 set_instance_assignment -name FAST_INPUT_REGISTER ON -to d1 # Set FAST_OUTPUT_REGSITER to output q1 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to q1
For more information about the slew fast input and output register features in the device, refer to the specific device handbook and the Intel® Quartus® Prime Help.
IOSTANDARD
The following example shows how to set the equivalent IOSTANDARD constraint (Differential SSTL-2 Class I) to the “q2” output.
Example XDC command:
# Set Differential SSTL18_I I/O Standard to q2 set_property IOSTANDARD SSTL18_I [get_ports q2];
Equivalent QSF command:
# Set Differential SSTL-18 Class I I/O Standard to q2 set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to q2
KEEP
The following example shows how both VHDL and Verilog HDL set the equivalent KEEP constraint (Differential SSTL-2 Class I) to the my_wire signal.
Verilog HDL example in the Vivado® software:
(* KEEP = "TRUE" *) wire my_wire
Equivalent Verilog HDL example in the Intel® Quartus® Prime software:
( *preserve*) wire my_wire;
VHDL example in the Vivado® software:
signal my_wire: bit; attribute keep: string; attribute keep of my_wire: signal is "TRUE";
Equivalent VHDL example in the Intel® Quartus® Prime software:
signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true;
Placement Constraints
The following table compares the most common Xilinx® placement constraints with the Intel® FPGA equivalent placement constraints:
Xilinx® Constraint | Intel® FPGA Constraint | Description | |
---|---|---|---|
Assignment Name | QSF Variable | ||
PBLOCK | Logic Lock Region | CORE_ONLY_PLACE_REGION | Specifies whether the placement region only applies to core logic. |
FLOATING_REGION | Specifies the type of floating region | ||
PLACE_REGION | Specifies the target and bounding boxes of a placement region | ||
REGION_NAME | Specifies the region name of a design instance. | ||
RESERVE_PLACE_REGION | Specifies whether the placement region prevents the Fitter from placing other logic in that region. | ||
ROUTE_REGION | Specifies the target and bounding boxes of a routing region. | ||
PACKAGE_PIN <Pin Number> | Location Assignment | PIN_<Pin number> | Assigns a location on the device for the current nodes or pins. |
LOC (for primitive cell such as SLICE, RAMB) | Location Assignment | <Location> <Value> | Assigns a location on the device for the current nodes or pins. |
BEL (for registers, LUT, SRL, LUTRAM) | Location Assignment | <Location> <Value> | Assigns a location on the device for the current nodes or pins. |
PROHIBIT | NA | NA | NA |
To set or modify placement constraints, use the Intel® Quartus® Prime Assignment Editor. Alternatively, you can edit the .qsf file.
PBLOCK
- EXCLUDE_PLACEMENT—directs the Fitter to place only pblock's logic in the device resources within the pblock region.
- CONTAIN_ROUTING—directs the Fitter to route signals in the pblock area using only resources available within the pblock area.
XDC Command:
create_pblock pblock_uut_inst add_cells_to_pblock [get_pblocks pblock_uut_inst] [get_cells -quiet [list uut_inst]] resize_pblock [get_pblocks pblock_uut_inst] -add {SLICE_X218Y284:SLICE_X220Y346} resize_pblock [get_pblocks pblock_uut_inst] -add {RAMB18_X12Y114:RAMB18_X12Y137} resize_pblock [get_pblocks pblock_uut_inst] -add {RAMB36_X12Y57:RAMB36_X12Y68} set_property CONTAIN_ROUTING 1 [get_pblocks pblock_uut_inst] set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_uut_inst]
Equivalent QSF Command:
set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to uut_inst set_instance_assignment -name RESERVE_PLACE_REGION ON -to uut_inst set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to uut_inst set_instance_assignment -name REGION_NAME uut_inst -to uut_inst set_instance_assignment -name ROUTE_REGION "X1 Y1 X20 Y20" -to uut_inst
set_instance_assignment -name REGION_NAME uut_inst -to uut_inst
set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to uut_inst
set_instance_assignment -name RESERVE_PLACE_REGION ON -to uut_inst
set_instance_assignment -name ROUTE_REGION "X1 Y1 X20 Y20" -to uut_inst
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to uut_inst
Differences Between PBLOCK and Logic Lock Regions
- When you assign a module to a Logic Lock region, the resources within the Logic Lock region become available to the module automatically. In the Vivado® software, you must manually assign the resources that the module can use to the PBLOCK region.
PACKAGE_PIN
The following example shows how to set the location for a clock pin on the device.
Example of XDC Command:
# Assign location for the clock pin set_property PACKAGE_PIN B26 [get_ports clock]
Equivalent QSF Command:
# Assign location for the clock pin set_location_assignment PIN_AU33 -to clock
LOC & BEL
The following example shows how to constraint the location for a current node on the device.
Example of XDC Command:
# Assign location for an internal register set_property LOC SLICE_X0Y0 [get_cells uut_inst/dout_reg]
Equivalent QSF Command:
# Assign location for an internal register set_location_assignment FF_X60_Y119_N55 -to uut_inst|dout_reg
PROHIBIT
Timing Constraints
The following table summarizes the most common Vivado® XDC timing constraints and the equivalent SDC timing constraints. You can set the constraints by either modifying the .sdc file or by using the Timing Analyzer GUI.
Vivado® XDC Timing Constraint | Timing Analyzer SDC Command | Description |
---|---|---|
create_clock
create_generated_clock set_max_delay set_false_path |
Defines all the clocks and their relationship in a design. | |
NA | derive_pll_clocks | Automatically creates a generated clock
constraint on each output of the PLLs in a design. Note: Only
Intel®
Arria® 10
devices support this command
|
NA | derive_clock_uncertainty | Calculates clock-to-clock uncertainties within the FPGA due to characteristics like PLL jitter, clock tree jitter, etc. The Timing Analyzer generates a warning if the command is not present in the SDC files |
set_input_delay | Input timing constraint that you use to define the Pad-to-Setup timing requirement in a design. | |
set_output_delay | Defines the global Clock to Pad timing requirement in a design. | |
set_max_delay | Combinational path that constrains all combinational pin to pin paths. | |
set_false_path | Eliminates the paths from timing consideration during Place and Route and timing analysis. | |
set_clock_groups w/- include_generated_clocks | set_clock_groups | Cuts timing between clocks in different groups. |
NA | derive_pll_clocks | Vivado® tools auto-derive the generated clocks; therefore, XDC files do not require these constraints. |
NA | derive_clock_uncertainty |
For more information about using the SDC commands and their usage, refer to the Timing Analyzer User Guide: Intel® Quartus® Prime Pro Edition .
set_clock_groups
In the Xilinx® Vivado® software, the set_clock_groups constraint supports an additional switch named include_generated_clocks, to include generated clocks of a specific member in a clock group. However, in Intel® Quartus® Prime Pro Edition, you must add the generated clocks by name.
# Assign adc_clk, clocks generated from adc_clk and sys_clk, clocks generated from sys_clk to different clock groups set_clock_groups -asynchronous \ -group [get_clocks -include_generated_clocks adc_clk] \ -group [get_clocks -include_generated_clocks sys_clk]
# Assign adc_clk, clocks generated from adc_clk and sys_clk, clocks generated from sys_clk to different clock groups set_clock_groups -asynchronous \ -group [get_clocks {adc_clk \ the_adc_pll| Intel® FPGA IOPLL_component_autogenerated|pll|clk[0] \ the_adc_pll| Intel® FPGA IOPLL_component_autogenerated|pll|clk[1] \ the_adc_pll| Intel® FPGA IOPLL_component_autogenerated|pll|clk[2] \ }] \ -group [get_clock {sys_clk \ the_system_pll| Intel® FPGA IOPLL_component_autogenerated|pll|clk[0] \ the_system_pll| Intel® FPGA IOPLL_component_autogenerated|pll|clk[1] \ } ]
Retimer Constraints
Setting Up the Simulation Environment
Intel® Quartus® Prime Pro Edition software supports RTL and gate-level design simulation in the EDA simulators listed in the table. Unless you use a simulator specific to Xilinx® , the simulation environment in the Intel® Quartus® Prime Pro Edition is similar. The Xilinx® environment also supports all the following EDA simulators:
Vendor | Simulator | Version | Platform |
---|---|---|---|
Aldec® | Active-HDL® | 10.3 | Windows® |
Aldec® | Riviera-PRO® | 2016.10 | Windows, Linux |
Cadence® | Incisive Enterprise® | 15.20 | Linux |
Mentor Graphics® | ModelSim® - Intel® FPGA Edition | 10.5c | Windows, Linux |
Mentor Graphics® | ModelSim® PE | 10.5c | Windows |
Mentor Graphics® | ModelSim® SE | 10.5c | Windows, Linux |
Mentor Graphics® | QuestaSim® | 10.5c | Windows, Linux |
Synopsys® |
VCS® VCS MX |
2016,06-SP-1 | Linux |
For more information about ModelSim® - Intel® FPGA Edition Products, refer to the Altera website.
For more information about supported simulation levels, refer to the Intel® Quartus® Prime Pro Edition Handbook Volume 3 .
Simulation Levels
If you use the ModelSim® - Intel® FPGA Edition Simulator in a design that includes deep levels of hierarchy, turn off the Maintain hierarchy EDA tools option. This action prevents the Compiler to generate a large number of module instances in post-fit or post-map netlist, thus exceeding the ModelSim® - Intel® FPGA Edition instance limitation. To access this option, click Assignments > Settings > EDA Tool Settings > More Settings.
For information about ModelSim® - Intel® FPGA Edition Products, refer to the ModelSim® - Intel® FPGA Edition page in the Altera website.
For information about supported simulation levels, refer to the Intel® Quartus® Prime Pro Edition Handbook Volume 3.
HDL Support for EDA Simulators
The Intel® Quartus® Prime Pro Edition software provides the following HDL support for EDA simulators:
- VHDL 1987 (IEEE Standard 1076-1987)
- VHDL 1993 (IEEE Standard 1076-1993)
- VHDL 2008 (IEEE Standard 1076-2008)
- Verilog-1995 (IEEE Standard 1364-1995)
- Verilog-2001 (IEEE Standard 1364-2001)
- SystemVerilog-2005 (IEEE Standard 1800-2005)
- SystemVerilog-2009 (IEEE Standard 1800-2009)
Value Change Dump (VCD) Support
All the EDA simulators that the Intel® Quartus® Prime Pro Edition software support, besides other third-party simulators can generate .vcd files. The Intel® Quartus® Prime Pro Edition Power Analyzer tool can read .vcd files for power measurements.
Simulating Intel FPGA IP Cores
The Intel® Quartus® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows.
Conclusion
Programmable logic design and compilation flow is very similar between Intel® Quartus® Prime software and Xilinx® Vivado® software, and in most cases, you can easily import a Vivado® design into the Intel® Quartus® Prime software design environment. You can improve your design conversion experience by following the design conversion guidelines and considerations discussed in this application note, including migrating a design targeted at a Xilinx® device to one that is compatible with an Intel® FPGA device.
Document Revision History for Intel FPGA Design Flow for Xilinx Users
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.03.20 | 17.1.0 |
|
Date | Version | Changes |
---|---|---|
May 2015 | 2015.05.11 |
|
March 2013 | 7.0 |
|
November 2009 | 6.2 | Corrected set_max_delay constraint equivalents for OFFSET IN BEFORE and OFFSET OUTPUT AFTER UCF commands in Timing Constraints section. |
April 2009 | 6.2 | Added Appendix A: Design Example and Appendix B |
July 2008 | 6.0 | Revised and restructured content for software versions ISE 10.1 and Quartus II 8.0 |
June 2005 | 5.0 |
|
February 2004 | 4.0 |
|
January 2004 | 3.1 | Updated terminology |
October 2003 | 3.0 |
|
July 2003 | 2.0 |
|
November 2002 | 1.0 | Initial release. |