This document provides requirements and design guidelines to enable
Arria® 10 devices to meet HDMI 2.1 Compliance Test Specifications (CTS) requirements. The system design guide demonstrates how a reference design utilizes
Arria® 10 GX development kit with a specifically designed daughtercard to support signal conditioning.
Arria® 10 GX development kit with Daughtercard
3. Scope of System Design Guidelines
Intel® recommends that you consider the prerequisites listed below:
Understand all HDMI 2.1 CTS requirements per HDMI.Org and strive to meet both Protocol and Electrical Specifications.
Refer to all existing platform level requirements (eg: Development Kit Guides, Platform Design Guides (PDG), Application Notes (AN) and all available resources).
You can use an existing development kit together with this system design guide to enable a HDMI 2.1 capable system. If you require an accelerated Time to Market (TTM) product roadmap, you have the option to adopt the daughtercard design recommendations and Intel development kit. If you choose to create a proprietary design, you can use the guidelines to assist you develop a design that meets compliance more easily, saving time and costs.
The reference design implemented on the daughtercard has passed HDMI 2.1 CTS testsuite. Electrical attributes have been characterized by Electrical Validation. The settings are optimized per correlation to development kit setup.
Electrostatic Discharge (ESD) is needed to protect the silicon from being damaged due to ESD events from a typical usage model.
Arria® 10 devices that use the application of redrivers/retimers do not require additional ESD clamp circuitry. However, you must assess the ESD requirements per your design needs.
The recommendations are results from the HDMI 2.1 daughtercard development iterations, but are also applicable to other board topologies. Thus, in the subsequent chapters, the document uses the PCB panel to describe the design in general.
4. System Design Guide Requirements
4.1. Enabling PCB panel design
The following guidelines and requirements target general PCB panels. FR4 stack-up can be an option to reduce cost. Otherwise, Rogers or other more advanced materials are also applicable by independently evaluating stack-up requirements based on the attributes below. Rogers is commonly used for better signaling on larger panels.
You must ensure the cables meet HDMI 2.1 certification. HDMI.org provides a list of compliant connectors provider as well as HDMI 2.1 compliant cable. HDMI IP running 12 Gbps FRL is tested with Belkin cables.
Table 2. Summary of daughtercard PCB general design guidelines
90-100 Ω Length matched
FR4, microstrip top/bottom layer
Keep stack-up targeting 90 Ω; to minimize reflection loss.
Connectors & Cables
Apply compliant connectors.
Belkin HDMI2.1 cable.
Reduce void by placement optimization.
Lowest Z possible
Partial to full Ground reference; full reference whenever possible.
Lowest plane Z
Full reference for signals.
HDMI 2.1 accommodates both Transition Minimized Differential Signaling (TMDS) and Fixed Rate Link (FRL) modes. TMDS targets support for legacy HDMI devices running on 3 data lanes and 1 clock lane while FRL runs on 4 data lanes.
On the RX, the TMDS clock path shares the FRL data lane. Thus, a fanout buffer is needed to demultiplex/split incoming RX signal to drive both paths to support both TMDS and FRL on the PCB panel with Intel FPGA. At the schematic level, one of the design approaches is to go with external fanout buffer. However, the additional fanout buffer increases system costs. Another option is to use an integrated fanout buffer option with redriver. The redriver is required at the RX side to recover signals at 16dB up to 12 Gbps.
HDMI 2.1 operates up to 12 Gbps with cable loss of up to 16dB. For cost optimization, use the redriver at the transmitter side.
Below is a summary of the redrivers for
Table 3. Redriver loss compensation and attributes
Insertion loss @12 Gbps
RX redriver, integrated Fanout buffer
Intel recommends trace impedance (Z) target to be in range 90-100 Ω; do not exceed 100 Ω (not considering fabrication tolerance). This ensures best possible reach on both trace length and signal integrity
Figure 2. Daughtercard panel size
Note: The reference design uses FR4 material due to it is low cost.
The daughtercard panel size is small with high speed traces within 10 inches. If you target larger margin and desire for larger panel, you can opt for Meg6 material. Intel recommends a flex cable topology for signals up to 12 Gbps.
For design with 4 layer (SGPS) FR4 stackup, refer below parameters for microstrip/top layer:
Outline below are list of applicable generic guidelines albeit not mandatory.
Power (VDD) and ground (GND) pins must connect to corresponding power planes of the printed circuit board directly without passing through any resistor.
You can minimize the thickness of the PCB dielectric layer so that the VDD and GND planes create low inductance paths.
One low-ESR 0.1uF decoupling capacitor must mount at each VDD pin. Capacitors of smaller body size, for example 0402 package, is preferable as the insertion loss is lower. Place the capacitor closest to the VDD pin.
Incorporate one capacitor with capacitance in the range of 4.7uF to 10uF in the power supply decoupling. You can use an ultra-low ESR ceramic. This capacitor can be placed further away from the FPGA than the 0.1uF VDD decoupling capacitors.
In addition to the list above, below are some guidelines on the PCB trace design.
Route the high-speed TMDS traces on the top layer to avoid the use of vias (and the introduction of their inductances). This allows for clean interconnects from the HDMI connectors to the redriver inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew (Refer to HDMI 2.1 CTS requirements for the measurement).
Place a solid ground plane next to the high-speed single layer to establish controlled impedance (targetted Z) for transmission link interconnects and provides a better low–inductance path for the return current flow.
Route slower control signals on the bottom layer to allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias thus higher insertion loss. Separate the signals with low voltage swing and single ended types from high speed differential pairs with larger (3x) spacing to minimize attenuation.
Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. You can place the power and ground plane of each power system closer together, thus increasing the high frequency bypass capacitance significantly.
HDMI 2.1 supports the PCA (power over cable assembly). Evaluate the voltage drop on the 5V rail at both TX and RX. In general, the widening traces for 5V rail can tolerate higher current load since nominal voltage remains at 5V.
Evaluate the HDMI connector footprint carefully to ensure you use compliant connectors. Strap the Ground pins to the nearest ground plane and do not leave the pins dangling. A good ground reference is critical to have the desired impedance control.
Note: If there is significant change in Loss Profile, Intel recommends to simulate on Advanced Link Analyzer (ALA) for optimized TX/RX settings.
4.3. System Link Budgeting Recommendation
Platform link budgeting helps improve your experience by allocating sufficient loss on main board (with
Arria® 10 FPGA), PCB panel or daughtercard and HDMI connector (including cables).
Apply a generic redriver primarily to meet Insertion Loss at 12 Gbps. Cable loss estimated at 18dB includes 2 connector, in a typical use case scenario.
TX on FPGA with below settings is recommended. Both FPLL and ATXPLL applies, generally ATX PLL has a slightly better margin compared to FPLL, although this may not be a dominant factor for
Table 6. FPGA TX Recommended Settings
Vod output swing ctrl
Pre emp sign 1st post tap
Fir post 1t neg
Pre emp sign 2nd post tap
Fir post 2t neg
Pre emp switching ctrl 1st post tap
Pre emp switching ctrl 2nd post tap
Pre emp sign pre tap 1t
Fir pre 1t post
Pre emp sign pre tap 2t
Fir pre 2t neg
Pre emp switching ctrl pre tap 1t
Pre emp switching ctrl pre tap 2t
Slew rate ctrl
TX slew rate is set to r5 to ensure all 4 data channels (TMDS has 3 data channel and 1 clock) is within bonding requirements of 2UI at Test Point 1 (TP1) to meet inter-lane skew requirements.
TX redriver setting is dependent on PCB design profile. Intel recommends to keep VOD setting at 1.0 at the TX redriver. Any lower setting can cause more signal degradation.
You must use a redriver on the PCB panel to meet the compliance for RX CTS and HDMI 2.1 cable loss. Non-compliant cables are not supported. The equalization is dependent on overall system reach design. In a typical scenario, 16dB is sufficient. However, higher values will be required when you use longer traces on larger PCB panels.
You can utilize flex cables instead of a large PCB panel for better cost to performance benefit. You need to apply link training methodology to evaluate if such cable can apply in your setup. Validation setup uses generic jitter tolerance methodology to meet HDMI 2.1 CTS requirement.
Below is a summary of targeted loss calibration:
Table 7. Targeted loss calibration
Insertion Loss : 20.11 dB
The jitter (BUJ) interpretation varies, you must focus on entire system level with all components account for 1 UI budget. The cable loss parameter is reflected by WCM cable provided by HDMI.org. The stressed signal feeds into RX to establish jitter tolerance. Settings required are listed below:
To meet HDMI 2.1 certification, there are 2 requirements namely Protocol IP CTS and Electrical CTS.
5.1. Protocol IP Compliance Test Specification
Protocol compliance can be achieved utilizing industry developed tester. This is a functional level compliance testing.
The example test setup comprised of
Arria® 10 GX development kit with HDMI 2.1 daughtercard. The Protocol IP compliance testing is performed using a Lecroy Quantum Data (QD) Protocol Analyzer. Overall result is passing on CED (Error Detection Counters) running on 12 Gbps.
Figure 4. Protocol IP Compliance Test Specification Result
Note: Refer only to the test result: Pass.
5.2. Electrical Compliance Test Specification
Electrical compliance can be achieved by meeting all the testsuite testing from industry vendors.
To enhance overall system performance, the development kit is tested rigorously on a HDMI 2.1 CTS compliance testsuite for all electrical parameters. Overall result is a PASS on all electrical attributes. The tests were done on 2 types of PLL, ATX PLL and FPLL running on FRL 12 Gbps and TMDS modes.
5.3. Gaps and Resolution
TX FFE enabling is recommended to ensure better interoperability among various HDMI 2.1 devices.
RX Equalization performance increases with better redrivers or retimers. Redrivers that are capable to compensate higher loss profile will reduce FPGA dependency.
While external redrivers/retimers are recommended to meet CTS compliance, you must ensure these settings are able to meet the proprietary loss profile setup.
Note: If the profile setup is significantly different from this document, you can apply Link Tuning method to verify link integrity. External devices (not part of Intel) is excluded from Electrical validation optimization and coverage.
6. Future System Level Optimization
6.1. Availability of Redrivers/Retimers
The market demand dictates the availability of redrivers and retimers to support electrical reach and compliancy. You can freely adopt any available redriver depending on electrical characteristic of Source and Sink.
Intel recommends that you apply TX FFE and use compliant cables in the setup. It can be an advantage if you use better RX equalization design to recover signal on a PCB panel before feeding it into FPGA.
6.2. Agilex Platform
The card design for
Arria® 10 family works on a typical level shifters from 1.8V up to 3.3V. However, to support future (and to extended timeframe for portability) Agilex family, the daughtercard level shifter of 1.0V is suitable on GPIO (general purpose IO).
Intel recommends to have DDC lines with proper pullup termination; the signals require mitigating voltage drop along the compliant cables.
Please contact Intel Support for guidance on Agilex system level enabling.
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines