Intel FPGA Power and Thermal Calculator User Guide
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.1 |
1. Overview of the Intel FPGA Power and Thermal Calculator
This tool does not support older devices such as the Intel® Arria® 10 and Intel® Cyclone® 10 families; use the corresponding Early Power Estimator if you are working with those devices.
This user guide provides guidelines for using the PTC, and details about thermal analysis and the factors contributing to FPGA power consumption.
You can calculate FPGA power consumption using the PTC, and for more accurate power estimation, use the Power Analyzer in the Intel® Quartus® Prime software. Intel recommends that you switch from the PTC to the Power Analyzer once your design is available. The Power Analyzer produces more accurate results because it has more detailed information about your design, including routing and configuration information about each of the resources in your design.
You should treat the PTC results as an estimate of power, not as a specification. You must verify the actual power consumption during device operation, because the information is sensitive to the actual device and design input signals. See the appendix Measuring Static Power for information on how to measure device static power in a way that correlates with the way that PTC reports static power.
- The ability to estimate the power consumption of your design before creating the design or during the design process.
- The ability to import device resource information from the Intel® Quartus® Prime software into the Power and Thermal Calculator using the .qptc file generated with the Intel® Quartus® Prime software.
- The ability to perform preliminary thermal analysis of your design.
1.1. Intel FPGA PTC Power Model Status
The Main tab of the Power and Thermal Calculator shows the current power model status for the selected device. Power models may be at an advance, preliminary, or final state:
- Advance power models are based on simulation results, process model projections, and design targets. Advance power models may change over time.
- Preliminary power models include post-layout simulation results, process data, and initial silicon correlation results. Preliminary power models may change over time.
- Final power models correlate to production devices with thousands of designs, and are not expected to change.
- Power Analyzer: Within 10% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates.
- Power and Thermal Calculator: Within 15% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates.
1.2. Definitions of Power Terms Used in this Document
- Static power—the power that the configured device consumes when powered up but no user clocks are operating. Static power is dependent on device size, device grade, power characteristics, and junction temperature. For Intel® Stratix® 10 devices, this excludes DC bias power of analog blocks, such as I/O and transceiver analog circuitry.
- Dynamic power—the additional power consumption of the device due to signal activity or toggling.
- Standby power—for Intel® Stratix® 10 devices only: additional power, independent of signal activity or toggling, that is consumed only when specific circuitry is enabled through configuration RAM settings. Standby power includes, but is not limited to, I/O and transceiver DC bias power. the component of active power that is independent of signal activity or toggling. Standby power includes, but is not limited to, I/O and transceiver DC bias power.
2. Setting Up the Intel FPGA Power and Thermal Calculator
2.1. Availability
For the convenience of designers who may be working only on power estimation and not running design compilations with the Intel® Quartus® Prime software, a standalone version of the PTC is also available. The standalone version offers all the same features as the version integrated within the Intel® Quartus® Prime software.
Licensing
The Intel® FPGA Power and Thermal Calculator supports the Intel® Agilex™ and Intel® Stratix® 10 families of FPGAs. The PTC for Intel® Stratix® 10 devices does not require a license. The PTC for Intel® Agilex™ devices does require a license.
When you launch the PTC, the dialog box indicates whether you have a valid license for the Intel® Agilex™ device family. If you do not have a license, click OK. The system displays a second dialog box, from which you can access a page to purchase a license for the Intel® Agilex™ PTC. Alternatively, you can request a license from the Intel® Quartus® Prime licensing page, or contact your Intel® representative to request a PTC license.
You should run the PTC license on the same license server as your Intel® Quartus® Prime software license. If you are using the Intel® Quartus® Prime software on a local machine, you should add the PTC license feature line to the same file as the Intel® Quartus® Prime license.
To use the PTC for Intel® Agilex™ FPGAs, after you have the necessary license, set the LM_LICENSE_FILE environmental variable to your license server name or the path to your license file. To set the LM_LICENCE_FILE environment variable to your license server for the Windows standalone version of the PTC, follow these steps:
- Open the Windows Control Panel and type environment in the search box. The system displays the option to edit the environment variables for your account.
- Double click the system icon.
- In the resulting dialog box, add or edit the LM_LICENSE_FILE variable for your installation
2.2. Obtaining the Standalone Intel FPGA Power and Thermal Calculator
The standalone Power and Thermal Calculator (PTC) is available from the Additional Software tab of the Intel® Quartus® Prime Pro Edition page of the Download Center for FPGAs, here: https://fpgasoftware.intel.com/20.1/?edition=pro.
Both the standalone version and the version integrated into the Intel® Quartus® Prime software require a license for use with Intel® Agilex™ devices.
Launching the Standalone Version
- To launch the Windows version of the standalone Power and Thermal Calculator, click the icon in the Start menu.
- To launch the Linux version of the standalone Power and Thermal Calculator, navigate to the folder where you installed the PTC, and run it from there.
2.3. Estimating Power Consumption with the Intel FPGA Power and Thermal Calculator
The PTC lets you estimate the power consumption when you have not yet begun your design, or when your design is only partially complete. Although the PTC can provide a power estimate for your completed design, Intel recommends that you use the Power Analyzer in the Intel® Quartus® Prime software when the design is available, for a more accurate estimate based on the exact placement and routing information of the completed design.
2.3.1. Estimating Power Consumption Before Starting the FPGA Design
| Advantage | Constraint |
|---|---|
|
|
To estimate power consumption with the PTC before starting your FPGA design, follow these steps:
- On the Main tab of the PTC, select the target family, device, and package from the Family, Device, Device Grade, Package, and Transceiver Grade drop-down lists.
- Enter values for each tab in the PTC. Different tabs display different power-consuming FPGA resources, such as clocks and phase-locked loops (PLLs).
- The calculator displays the total estimated power consumption in the Total Power (W) cell of the Power Summary.
- Save the file as <project_name>.ptc for later use.
2.3.2. Estimating Power Consumption While Creating the FPGA Design
If your FPGA design is partially complete, you can import a .qptc file (<revision name>.qptc) generated by the Intel® Quartus® Prime software into the Power and Thermal Calculator. After importing the information from the .qptc file into the PTC, you can edit the PTC data to reflect the device resource estimates for your final design.
If you have instructed the Intel® Quartus® Prime Power Analyzer (QPA) to produce a .qptc file, the following assignment is written to the .qsf file:
POWER_AND_THERMAL_CALCULATOR_EXPORT_FILE <filename>
When you open the Power and Thermal Calculator with a Quartus project (either from the Tools menu, or if you specified a project on the quartus_ptc command line) it looks for this QSF assignment and attempts to open the specified file. If the specified file isn't found, an error message occurs. After dismissing the error message, you are free to use the PTC to enter design information. If you want, you can remove this QSF assignment to suppress the error message when opening the PTC.
| Advantage | Constraint |
|---|---|
|
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Importing a File
Importing a .qptc file saves you time and effort otherwise spent on manually entering all the information into the PTC. You can also manually change any of the values after importing a file.
Importing Data into the Power and Thermal Calculator
You must import the .qptc file into the PTC before modifying any information. Also, you must verify all your information after importing a file.
Importing a file from the Intel® Quartus® Prime software populates all input values that were specified in the Intel® Quartus® Prime software. Alternatively, you can import values exported from an earlier version of the PTC.
To import data into the PTC, follow these steps:
- On the File menu, click Open.
- Browse to an existing PTC file generated by the current or earlier version of the PTC or the Intel® Quartus® Prime software, and click Open.
- After the file is imported into the PTC, the mouse cursor changes from busy to normal. If there are any warnings during the import, the PTC displays the PTC Import Warnings dialog box. Analyze each warning carefully to understand the cause; if any of the warnings are unexpected, you must manually modify the corresponding fields in the PTC after the import is completed. You can copy all warning messages to the clipboard for future reference by clicking Copy. Click OK to dismiss the PTC Import Warnings dialog box. (Examples of warnings that could occur, would be if device ordering codes had changed such that previous values for Device Grade, Device, and Package and Transceiver Grade fields could not be imported directly, or if the VCC voltage isn't applicable to the selected device.)
Importing .qptc Data for Intel® Stratix® 10 Devices into the Power and Thermal Calculator for Intel® Agilex™ Devices
If you want to import a data file originally exported from the Intel® Quartus® Prime software based on a design targeting Intel® Stratix® 10 devices, for use in the Intel® Agilex™ version of the Intel® FPGA Power and Thermal Calculator, follow these steps:
- In the Intel® Stratix® 10 version of the Power and Thermal Calculator, open the existing .qptc file generated by the Intel® Quartus® Prime software based on a design targeting an Intel® Stratix® 10 device.
- Save the file as a .ptc file, and exit the Intel® Stratix® 10 Power and Thermal Calculator.
- Launch the Intel® Agilex™ version of the Power and Thermal Calculator, and open the .ptc file created in step 2.
- Select the appropriate Intel® Agilex™ device and modify resources and other settings to reflect your planned design targeting the Intel® Agilex™ device.
Importing an Early Power Estimator file from an Earlier Version to the Power and Thermal Calculator (For Intel® Stratix® 10 devices only)
If you want to import a .csv file originally exported from the Intel® Quartus® Prime software version 19.4, or from the Early Power Estimator spreadsheet version 19.4, for a design targeting an Intel® Stratix® 10 device, for use in the Intel® Stratix® 10 version of the Power and Thermal Calculator version 20.1, follow these steps:
- Open the Early Power Estimator .csv file exported from the 19.4 version of the Intel® Quartus® Prime software or Early Power Estimator spreadsheet in the Intel® Stratix® 10 version of the Power and Thermal Calculator.
- Save the file as a .ptc file, and exit the Intel® Stratix® 10 Power and Thermal Calculator.
Some general points about the import process:
- A .qptc file created for an Intel® Agilex™ or Intel® Stratix® 10 design, can always be imported into the PTC for use with the same device family.
- A .qptc file created for an Intel® Stratix® 10 design can be imported into the PTC for use with the similar design targeting an Intel® Agilex™ device.
- A .qptc file created for an Intel® Agilex™ design, cannot be imported into the PTC for use with an Intel® Stratix® 10 design.
- Some sources and power-consuming resources — such as transceivers — of an original Intel® Stratix® 10 design, might not be carried through the import process.
2.3.3. Estimating Power Consumption After Completing the FPGA Design
If your design is complete, Intel® strongly recommends that you do not use the Power and Thermal Calculator, and instead use the Power Analyzer in the Intel® Quartus® Prime software. The Power Analyzer uses toggle rates from simulation, user assignments, and placement-and-routing information to provide more accurate power estimates.
3. Intel FPGA Power and Thermal Calculator Graphical User Interface
3.1. Intel FPGA PTC Select Family Dialog Box
To proceed with the Power and Thermal Calculator, select the desired device family, and click Ok.
- Once you have selected a device family to model, you cannot change that selection unless you start a new PTC instance.
- Currently, the Power and Thermal Calculator supports the Intel® Agilex™ and Intel® Stratix® 10 FPGA device families. You will notice some differences on the PTC tabs, depending on the device family selected.
3.2. Intel FPGA PTC Basic GUI Components
In general, input fields are not shaded, and are editable, either by double-clicking and selecting a value from a drop-down list or by typing a value directly. Fields with a light blue background contain calculated values, based on parameters that you have entered in the data entry tabs.
Data Entry Tabs
The data entry area provides tabs for entering parameters associated with various aspects of your design.
Power Summary
The Power Summary shows the calculated power consumption of various types of resources, based on the current values in the data entry tabs. The fields of the Power Summary cannot be edited directly, and therefore are shaded in light blue as read-only.
Device and Thermal Analysis Tabs
The Device and Thermal Analysis tabs summarize device characteristics and presumed thermal operating conditions, respectively. This information is also available on the Main tab of the data entry area.
Messages Window
The Messages area at the bottom of the screen displays any warning or error messages that may occur.
3.2.1. Intel FPGA PTC Data Entry Tabs
The look and feel of the Power and Thermal Calculator is the same whether you are using the standalone version or the version integrated within the Intel® Quartus® Prime software. There are, however, differences depending on whether you are targeting Intel® Agilex™ or Intel® Stratix® 10 devices.
The following are the tabs within the Power and Thermal Calculator:
- The Main tab allows you to enter device, package, and cooling information, and displays thermal analysis information.
- The Logic tab allows you to enter logic resources for all modules in your design.
- The RAM tab represents design modules using RAM blocks. Among other information, enter RAM type, data width, RAM depth (if applicable), RAM mode, and port parameters.
- The DSP tab represents DSP design modules. Among other information, enter DSP configuration, clock frequency, toggle percentage, and register usage.
- The Clock tab represents clock networks of separate clock domains.
- The PLL tab represents one or more I/O PLLs in the device.
- The I/O tab represents design modules using general-purpose I/O pins. This tab does not apply to transceiver I/O pins. Among other information, enter I/O standard, input termination, current strength or output termination, data rate, clock frequency, output enable static probability, and capacitive load.
- The I/O-IP tab represents design modules using complex I/O IP, such as DDR.
- The Transceiver tab allows you to enter transceiver resources and their settings for all modules in your design.
- The ADC/DAC tab ( Intel® Stratix® 10 devices only).
- The HPS tab applies to devices with HPS.
- The HBM tab ( Intel® Stratix® 10 devices only).
- The Thermal tab ( Intel® Stratix® 10 devices only).
- The Report tab shows per-rail currents calculated by the Intel® FPGA Power and Thermal Calculator (PTC).
- The Intel® Enpirion® tab ( Intel® Stratix® 10 devices only).
3.2.2. Intel FPGA PTC Field Types
Field Types
Input fields let you enter information about the device and design for which you want to calculate power estimates. Some input fields let you type values directly, and others let you select from a list of values on a dropdown menu.
Output fields display estimated values for power, current, temperature, or resource utilization for a design specification that you have entered into the Power and Thermal Calculator.
Input/output fields may serve as input fields in some configurations, and output fields in others. For example, you may enter a Pin Clock Frequency value manually for some I/O modes, while in other I/O modes Pin Clock Frequency is calculated automatically, based on values of other input fields. If you enter a value into an input/output field when it is serving as an output, there is no effect; the value reverts to the calculated value.
Field Background Colors
The Power and Thermal Calculator uses background color to distinguish between input and output fields, and to help identify fields with only one allowed value.
Regular input fields, such as the Module, RAM Type, # RAM Blocks, and other columns in the above figure, have a white background. The white background also indicates input/output fields.
Input fields that currently have only one allowed value, such as Port A Read Enable %, Port B Write Enable %, and others in this example, have a gray background. A different combination of specified parameters might allow for more than one allowed value for these fields, in which case the background color would become white, to allow user input.
Output fields, such as those in the Routing Power (W), Block Power (W), and Total Power (W) columns, as well as all of the fields in the Power Summary section, have a light blue background.
3.2.3. Intel FPGA PTC Input Field Dependencies
For example, the device package that you select may determine what transceiver grades are selectable. If you change the selected device package, and the currently selected transceiver grade is still legal for the new package, the Transceiver Grade value does not change. However, if the currently selected transceiver grade is not compatible with the selected device package, the Transceiver Grade value automatically changes to one of the legal values.
Changes that you make in one tab may affect values on another tab, because of dependencies between input fields. For example, if you select a device that does not support the current I/O standard specified in the I/O tab, that I/O standard automatically changes to one of the I/O standards supported by the new device.
In general, the Intel® FPGA Power and Thermal Calculator does not automatically change an input value unless it is necessary to preserve the legality of the input. Changes in one field have minimal impact on other fields, while ensuring that overall combination of field values are legal. However, this can sometimes lead to unanticipated results. Consider the following example:
Assume that Dev1 is selected in the Main tab, and I/O standard IO1 is selected in the I/O tab. Assume also that device Dev1 supports I/O standards IO1 and IO2. Suppose that you change the device selection to Dev2, which supports only one I/O standard, IO2. As a result of you changing the device selection, the I/O standard in the I/O tab changes to IO2. If you then reverted the device selection back to Dev1, the I/O standard does not change, because IO2 is a legal I/O standard value for the device Dev1. The important point to note, is that the changing of device from Dev1 to Dev2 and back again, had the—potentially unintended—consequence of changing the I/O standard in the I/O tab.
3.2.4. Intel FPGA PTC Data Entry Error Messages
Sample Error Message: Invalid Value
In this example you have entered a temperature that is outside the allowed range for a selected family, device, transceiver grade, device grade and package combination. The error message indicates the allowed range of 0 to 100. After you click OK, the field reverts to its previous value.
Sample Error Message: Incorrect Format
Many fields require a specific type of data. If the data you enter is not of the type required, an error message will appear.
For example, if an integer value is expected and you enter a fractional value, the resulting error message indicates that the entered value cannot be converted to a valid value for the input field. After you click OK, the field reverts to its previous value.
If a numerical value is expected and you enter a text value, the resulting error message indicates that the entered value cannot be converted to a valid value for the input field. After you click OK, the field reverts to its previous value.
4. Power and Thermal Calculator Tabs
4.1. Intel FPGA PTC - Power Summary
The values displayed in the Power Summary update in real time, as you change parameters on the data entry tabs.
In addition to displaying total power consumption, the Power Summary displays power consumption values for the resource types listed in the following table.
| Intel® Agilex™ PTC Power Summary | |
| Resource Type | Description |
| AIB | Advanced Interface Bus. |
| Clock Network | The various clocks driving the synchronous portions of a design. |
| Combinational Cell | The combinational logic in a design. |
| Configuration RAM | The static RAM that configures an FPGA. |
| DSP | Specialized blocks optimized for fast math operations. |
| eSRAM | Embedded SRAM memory available to the user. |
| HBM | High-bandwidth memory. |
| HPS | The hard-processor subsystem: a dedicated CPU integrated into the FPGA. |
| HSSI Analog | The analog components of the FPGA's high-speed transceiver blocks. |
| HSSI Digital | The digital components of the FPGA's high-speed transceiver blocks. |
| I/O Analog | Power dissipated in the analog domain of the I/O subsystem, for example, I/O buffers. |
| I/O Digital | Power dissipated in the digital domain of the I/O subsystem including GPIO, EMIF controller and SerDes controller. |
| Memory LABs | Portions of logic modules configured as small memory blocks. |
| Miscellaneous | Any power that doesn't fit into any of the other categories. |
| PLL | Converts the fixed external clock to one or more high-speed on-chip clocks that drive synchronous portions of the design. |
| RAM | Specialized blocks optimized for data storage and retrieval. |
| Register Cell | The synchronous portions of a logic module. |
| Routing | The wires on the chip and all of their drivers and interconnects. |
| Static Power | The power that the configured device consumes when powered up but with no user clocks operating. The static power (PSTATIC) is the thermal power dissipated on the chip, independent of design activity. PSTATIC includes the static power from all FPGA functional blocks. PSTATIC is the only thermal power component that varies with junction temperature and power characteristics (process). PSTATIC is also the only thermal power component that varies significantly with selected device. |
| Intel® Stratix® 10 PTC Power Summary | |
| Resource Type | Description |
| Logic | The dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and associated routing. |
| RAM | The dynamic power consumed by RAMs and associated routing. |
| DSP | The dynamic power consumed by digital signal processing (DSP) blocks and associated routing. |
| Clock | The dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device. |
| PLL | The dynamic power consumed by phase-locked loops (PLLs). |
| I/O | The total power consumed by I/O pins and I/O subsystems. |
| Transceiver | The total power consumed by transceiver blocks. |
| Hard Processor | The total power consumed by the hard processor system (HPS). |
| High-Bandwidth Memory | The total power consumed by high-bandwidth memory (HBM) blocks and UIBs. |
| ADC/DAC | The total power consumed by analog-to-digital converters and digital-to-analog converters. |
| Static Power | The static power consumed regardless of clock frequency. This includes static power consumed by I/O and transceiver blocks, but does not include standby power. |
| Total Before SmartVID Savings | The total power consumption before SmartVID power savings. Includes static power (PSTATIC) and power consumed by different blocks as reported above. Does not include power dissipated in off-chip termination resistors. |
| SmartVID Savings | The total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result. The reduction reported in this field is already taken into consideration in the Total (W) field. The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum. |
| Total Power | The total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors. |
4.2. Intel FPGA PTC - Common Tab Elements
Total Thermal Power
The Total Thermal Power field estimates the total thermal power consumed by all FPGA resources in the specific tab. Some tabs may also provide a breakdown of the components contributing to the total thermal power. The total thermal power displayed in individual tabs does not include static power, which is reported in the Power Summary for the whole device.
Thermal power is the power dissipated in the device. Total thermal power is the sum of the thermal power of all the resources used in the device, including dynamic power. Total thermal power includes only the thermal component for the I/O tab and does not include external power dissipation, such as from voltage-referenced termination resistors.
Resource Utilization
Most tabs contain one or more fields that provide an estimate of the percentage resource utilization for the modules in the specific tab. Such values are calculated based on the maximum available resources of a given type for a selected device. If resource utilization exceeds 100%, it indicates that the current device may not be able to support the resources entered into the tab.
Power Rail Current Consumption
Most tabs include a table showing the dynamic current consumption for all power rails used by the FPGA resources in the specific tab. The same power rail may appear in multiple tabs, and the dynamic currents reported in the Report tab are the sums of all corresponding currents for a given rail at a given voltage in individual tabs. The Report tab also includes static currents, which are not reported in individual tabs.
4.3. Intel FPGA PTC - Device Selection and Thermal Analysis Tabs
The Device Selection and Thermal Analysis tabs can be displayed at all times, allowing you to modify device, package, and cooling information, and to view thermal analysis information, while working on a tab other than the Main tab.
4.4. Intel FPGA PTC - Main Tab
The required parameters depend on whether the junction temperature is manually entered or auto computed. (Auto-computed temperature is not supported for Intel® Agilex™ devices in version 20.1.)
| Parameter | Description |
|---|---|
| Family | Shows the selected device family. |
| Device |
Select your device. Larger devices consume more static power and have higher clock dynamic power. All other power components are unaffected by device selection. |
| Device Grade |
Select the combination of Operating Temperature, Speed Grade, and Power Option used. Refer to the device datasheet for available combinations. |
| Package |
Select the device package. Larger packages provide a larger cooling surface and more contact points to the circuit board, thus they offer lower thermal resistance. Package selection does not affect dynamic power directly. |
| Transceiver Grade | Select the transceiver grade. Note: For information on transceiver grades, refer to
the Device Overview document for a
given device family.
|
| VCC Voltage (mV) | (This field appears in the Intel® Stratix® 10 PTC only.) |
| Power Model Status | Indicates whether the power model for the device is in advance, preliminary, or final status. |
The Thermal Analysis Summary section displays the junction temperature (TJ) and other thermal parameters, depending on the thermal analysis mode.
| Column Heading | Description |
|---|---|
| Junction Temp Mode |
Select whether you provide the junction temperature, or whether detailed thermal analysis should be performed to determine junction temperature. In user-entered mode, the junction temperatures for all dies in the package are assumed to have one value, which you provide. When using a detailed thermal model, temperatures of different dies may be different, depending on the characteristics of a specific design. Tip: For faster responsiveness from the
system, you should leave this value as User Entered until you are
ready to perform detailed thermal analysis.
Note: Currently, only User Entered mode is supported for
Intel®
Agilex™
devices. The detailed thermal
model will be supported in a future release.
|
| Junction Temp, TJ (°C) | Specify the junction temperature
for all dies in the package. Note: This field is applicable only when the selected
Junction Temp Mode
value is User
Entered.
|
| Ambient Temp, TA (°C) | Specifies the temperature of the air that is cooling
the device. Note: This field is applicable only when the selected
Junction Temp Mode
value is Detailed Thermal
Model.
(This field appears in the Intel® Stratix® 10 PTC only.) |
| Max. Junction Temp TJ-MAX (°C) | Specifies the maximum junction temperature that no
part of any die in the package should exceed. Note: This field is applicable only when the selected
Junction Temp Mode
value is Detailed Thermal
Model.
(This field appears in the Intel® Stratix® 10 PTC only.) |
| Recommended ψCA(°C/W) | ψCA is the thermal resistance between the
center of the package integrated heat spreader (IHS) and ambient
temperature. The recommended ΨCA is the
highest possible thermal resistance of the cooling solution that
ensures no part of any die exceeds the specified maximum junction
temperature. Note: This field is applicable only when the selected
Junction Temp Mode
value is Detailed Thermal
Model.
(This field appears in the Intel® Stratix® 10 PTC only.) |
| Max. ψJC(°C/W) | ψJC is the thermal resistance between
each of the dies in the package and the center of the package
integrated heat spreader. This field shows the maximum ΨJC among all die, assuming the
recommended ΨCA value above. Note: This field is applicable only when the selected
Junction Temp Mode
value is Detailed Thermal
Model.
(This field appears in the Intel® Stratix® 10 PTC only.) |
| Case Temperature TCASE (°C) | The case temperature, which is the temperature at the top center of
the integrated heat spreader, assuming the recommended ΨCA value listed above. Note: This field is applicable only when the selected
Junction Temp Mode
value is Detailed Thermal
Model.
(This field appears in the Intel® Stratix® 10 PTC only.) |
You can directly enter or automatically compute junction temperatures based on the information provided. To enter the junction temperature, select User Entered in the Junction Temp Mode field, then enter the desired junction temperature in the User-Entered Junction Temp TJ (°C) field in the Thermal Analysis Summary section. In this mode, the junction temperatures for all dies in the package are assumed to have the specified value. To automatically compute junction temperatures, select Detailed Thermal Model in the same field.
4.5. Intel FPGA PTC - Logic Tab
| Input Parameter | Description |
|---|---|
| Module |
Specify a name for each module of the design. This is an optional entry. |
| #Half ALMs |
Enter twice the number of Adaptive Logic Modules (ALMs) used in your design, which you can find in the Compilation Report, by selecting . For power estimation purposes, the number of ALMs used in your design is the sum of the following values in the Compilation Report:
The adjustment for power estimation is necessary because some unused ALMs may still consume power due to Fitter optimizations. |
| # FFs |
Enter the number of Primary logic registers, plus Secondary logic registers, plus the number of registers reported as Register control circuitry for power estimation, all of which you can find in the Compilation Report, by selecting . The Register control circuitry for power estimation adjustment is necessary because some unused registers may still consume power due to fitter optimizations. Clock routing power associated with flipflops is calculated separately on the Clock tab of the PTC. |
| Clock Freq (MHz) |
Enter a clock frequency (in MHz). This value is limited by the maximum frequency specification for the device family. Note: For
Intel®
Stratix® 10
devices, when you import a design from the
Intel®
Quartus® Prime software, some imported
half ALMs and flipflops may have a clock frequency of 0 MHz;
this can occur for one of two reasons:
|
| Toggle % |
Enter the average percentage of clock cycles when the block output signals change values. Toggle percentage is multiplied by clock frequency to determine the number of transitions per second. For example, 100 MHz frequency with a 12.5% toggle rate, means that each LUT or flipflop output toggles 12.5 million times per second (100MHz × 12.5%). The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. Most logic only toggles infrequently; therefore, toggle rates of less than 50% are more realistic. To ensure you do not underestimate the toggle percentage, use a realistic toggle percentage obtained through simulation. For example, a T flipflop (TFF) with its input tied to VCC has a toggle rate of 100% because its output is changing logic state on every clock cycle. Refer to the 4-Bit Counter Example below for a more detailed analysis. For any rows containing flipflops, toggle percentage cannot exceed 100%. A small portion of ALMs in a design may experience glitching that results in toggle percentage exceeding 100% for such ALMs. Enter such ALMs into a separate row with # FFs set to 0. |
| Routing Metric |
Indicates the extent of the routing power of the outputs. Characteristics that have a large power impact and are captured by this factor include the following:
The default value for this field is typical; the actual value varies between blocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Intel® Quartus® Prime software after compiling your design, because the Intel® Quartus® Prime software has access to detailed placement and routing information. In the absence of an Intel® Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals. You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design. |
| Routing |
Indicates the power dissipation due to estimated routing (in W). Routing power depends on placement and routing, which is a function of design complexity. The values shown are representative of routing power based on observed behavior across more than 100 real-world designs. Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact routing used in your design. |
| Block |
Indicates the power dissipation due to internal toggling of the ALMs and registers (in W). Logic block power is a combination of the function implemented and the relative toggle rates of the various inputs. The PTC uses an estimate based on observed behavior across more than 100 real-world designs. Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact synthesis of your design. |
| Total |
Indicates the estimated power (in W), based on information entered into the PTC. It is equal to the sum of routing power and block power. |
| User Comment |
Enter any comments. This is an optional entry. |
The cout0 output of the first TFF has a toggle percentage of 100% because the signal toggles on every clock cycle. The toggle percentage for the cout1 output of the second TFF is 50% because the output toggles every two clock cycles. Similarly, the toggle percentage for the cout2 and cout3 outputs are 25% and 12.5%, respectively. Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.
For more information about logic block configurations, refer to the Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide.
4.6. Intel FPGA PTC - RAM Tab
Each row in the RAM tab of the PTC represents a logical RAM module that you can implement using one or more physical RAM blocks. The PTC implements each logical RAM module with the minimum number of physical RAM blocks, in the most power-efficient way possible, based on the specified logical width and depth.
You must know how your RAM is implemented by the Intel® Quartus® Prime Compiler when you are selecting the RAM block mode. For example, if a ROM is implemented with two ports, it is considered a true dual-port memory and not a ROM. Single-port and ROM implementations use only one port. Simple dual-port and true dual-port implementations use both Port A and Port B.
- The Power and Thermal Calculator reports MLAB power in the RAM tab as described above, as well as in the Power Summary table.
- In the Power Summary table, the MLAB power for Intel® Agilex™ devices is spread across four categories: Memory LAB, Miscellaneous, Register and Routing; this is done to be consistent with the reporting provided in the Intel® Quartus® Prime Power Analyzer.
| Column Heading | Description |
|---|---|
| Module |
Enter a name for the RAM module in this row. This is an optional value. |
| RAM Type |
Select the implemented RAM type. You can find the RAM type in the Type column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select . |
| # RAM Blocks |
Enter the number of RAM blocks in the module that use the same memory type and mode and have the same port parameters. The parameters for each port are as follows:
You can find the number of RAM blocks in either the MLAB cells or M20K blocks column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select . Note: The value entered into this field represents
the number of logical memory blocks. Depending on the specified
memory depth and data width, more than one physical memory block
may be required to implement one logical block. The Power and
Thermal Calculator calculates the number of physical memory
blocks based on the specified memory depth and data width, such
that the minimum number of physical blocks is used, and assuming
the most power efficient physical configuration.
|
| RAM Data Width |
Enter the width of the data for the RAM block. This value is limited based on the RAM type. You can find the width of the RAM block in the Port A Width or the Port B Width column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select . For RAM blocks that have different widths for Port A and Port B, use the larger of the two widths. |
| RAM Depth |
Enter the depth of the RAM block in number of words. You can find the depth of the RAM block in the Port A Depth or the Port B Depth column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select . |
| RAM Mode |
For MLAB and eSRAM RAM types, this field has only one possible value: Simple Dual Port. For M20K RAM type, select from the following modes:
The mode is based on how the Intel® Quartus® Prime Compiler implements the RAM. If you are unsure how your memory module is implemented, you can compile a test case in the required configuration in the Intel® Quartus® Prime software. You can find the RAM mode in the Mode column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select . A single-port RAM has one port with a read and a write control signal. A simple dual-port RAM has one read port and one write port. A true dual-port RAM has two ports, each with a read and a write control signal. ROMs are read-only single-port RAMs. A simple quad-port RAM has a total of four ports, two read ports and two write ports. |
| Port A - Clock Freq (MHz) |
Enter the clock frequency for Port A of the RAM blocks (in MHz). This value is limited by the maximum frequency specification for the RAM type and device family. |
| Port A - Clock Enable % |
The average percentage of time the Port A clock enable is active, regardless of activity on RAM data and address inputs. This number must be a percentage between 0% and 100%. RAM power is consumed primarily when a clock event occurs. Using a clock enable signal to disable a port when no read or write operation is occurring can result in significant power savings. |
| Port A - Read Enable % |
Enter the percentage of time Port A of the RAM block is in read mode. This field is applicable only for true dual port RAMs. This value must be a percentage number between 0 and 100%. |
| Port A - Write Enable % |
Enter the average percentage of time Port A of the RAM block is in write mode. This field applies only for dual port, true dual port, and quad port RAMs. This value must be a percentage number between 0 and 100%. |
| Port B - Clock Freq (MHz) |
Enter the clock frequency for Port B of the RAM blocks (in MHz). |
| Port B - Clock Enable % |
Enter the average percentage of time the input clock enable for Port B is active, regardless of the activity on the RAM data and address inputs. The enable percentage ranges from 0 to 100%. RAM power is consumed primarily when a clock event occurs. Using a clock-enable signal to disable a port when no read or write operation is occurring can result in significant power savings. |
| Port B - Read Enable % |
Enter the percentage of time Port B of the RAM block is in read mode. This field is applicable only to dual port, true dual port, and quad port RAMs and ROMs. This value must be a percentage number between 0 and 100%. |
| Port B - Write Enable % |
Enter the percentage of time Port B of the RAM block is in write mode. This field is available only for true dual-port mode. This value must be a percentage number between 0 and 100%. |
| Port C - Write Enable % |
Enter the percentage of time the RAM block is writing to this port. In Simple Quad-Port Mode, clock and clock enable for all parts are shared and the same as Port A. This value must be a percentage number between 0 and 100%. |
| Port D - Read Enable % |
Enter the percentage of time the RAM block is reading on this port. In Simple Quad-Port Mode, clock and clock enable for all parts are shared and the same as Port A. This value must be a percentage number between 0 and 100%. |
| Toggle % |
The percentage of clock cycles when the block output signal changes value. This value is multiplied by the clock frequency and the enable percentage to determine the number of transitions per second. This value affects only routing power. 50% corresponds to a randomly changing signal, since half the time the signal holds the same value and thus not transition. This is considered the highest meaningful toggle rate for a RAM block. |
| Routing Power (W) |
Indicates the power dissipation due to estimated routing (in W). Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power estimate based on observed behavior across more than 100 real-world designs. Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact routing used in your design. |
| Block Power (W) |
Indicates the power dissipation due to internal toggling of the RAM (in W). Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact RAM modes in your design. |
| Total Power (W) |
Indicates the estimated power (in W), based on information entered into the PTC. Total power is equal to the sum of routing power and block power. |
| User Comments |
Enter any comments. This is an optional entry. |
4.7. Intel FPGA PTC - DSP Tab
| Column Heading | Description |
|---|---|
| Module |
Enter a name for the DSP module in this column. This is an optional value. |
| Configuration | Select the DSP block configuration for the module. |
| # of Instances |
Enter the number of DSP block instances that have the same configuration, clock frequency, toggle percentage, and register usage. This value is not necessarily equal to the number of dedicated DSP blocks you use. For example, it is possible to use two 18 × 18 simple multipliers that are implemented in the same DSP block in the FPGA devices. In this case, the number of instances would be two. To determine the maximum number of instances you can fit in the device for any particular mode, follow these steps:
|
| Clock Freq (MHz) |
Enter the clock frequency for the module (in MHz). This value is limited by the maximum frequency specification for the device family. |
| Clock Enable % | Specifies the percentage of time that the DSP block is enabled. |
| Toggle % |
Enter the average percentage of DSP data outputs toggling on each clock cycle. The toggle percentage ranges from 0 to 50%. The default value is 12.5%. For a more conservative power estimate, use a higher toggle percentage. 50% corresponds to a randomly changing signal, since half the time the signal holds the same value and thus not transition. This is considered the highest meaningful toggle rate for a DSP block. |
| Preadder? | Select Yes if the PreAdder function of the DSP block is turned on. |
| Coefficient? | Select Yes if the Coefficient function of the DSP block is turned on. |
| Registered Stages |
Select number of the registered stages. Permitted values depend on the selected mode; some modes, such as floating-point multiply and accumulate cannot have 0 register stages..
|
| Routing |
Indicates the power dissipation due to estimated routing (in W). Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power estimate based on observed behavior across more than 100 real-world designs. |
| Block |
Indicates the estimated power consumed by the DSP blocks (in W). |
| Total |
Indicates the estimated power (in W), based on information entered into the PTC. It is the total power consumed by the DSP blocks and is equal to the routing power and block power. |
| User Comments | Enter any comments. This is an optional entry. |
4.8. Intel FPGA PTC - Clock Tab
Intel® Agilex™ and Intel® Stratix® 10 devices support global, regional, and periphery clock networks. The PTC does not distinguish between global or regional clocks because the difference in power is not significant.
| Column Heading | Description |
|---|---|
| Module | Enter a name for the clock domain in this column. This is an optional value. |
| Clock Freq (MHz) | Enter the frequency of the clock
domain. This value is limited by the maximum frequency specification
for the device family. Note:
When you import a design from the Intel® Quartus® Prime software, some imported clocks may have a frequency of 0 MHz, due to either of the following reasons:
|
| Total Fanout |
Enter the total number of flipflops, hyper-registers, RAMs, digital signal processing (DSP) blocks, and I/O pins fed by this clock. Power consumed by Intel® Stratix® 10 MLAB clocks is accounted for in the RAM tab; therefore, clock fanout on this tab does not include any MLABs driven by this clock domain, for Intel® Stratix® 10 devices. For Intel® Agilex™ devices, MLAB is included in the fanout. The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter and click Place Stage. Select Global & Other Fast Signals Summary and observe the Fan-out value. |
| Global Enable % | Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree. |
| Local Enable % |
Enter the average percentage of time that clock enable is high for destination flipflops. Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide clock is disabled, cutting clock power and the power for down-stream logic. This tab models only the impact on clock tree power. |
| Utilization Factor |
Represents the impact of the clock network configuration on power. Characteristics that have a large impact on power and are captured by this factor include the following:
The default value for this field is typical; the actual value varies between clocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Intel® Quartus® Prime software after compiling your design, because the Intel® Quartus® Prime software has access to detailed placement information. In the absence of an Intel® Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals. You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design. |
| Total Power (W) | Indicates the total power dissipation due to clock distribution (in W). |
| User Comments | Enter any comments. This is an optional entry. |
For more information about the clock networks of Intel® Agilex™ devices, refer to the Intel Agilex Clocking and PLL User Guide.
4.9. Intel FPGA PTC - PLL Tab
Supported PLL types are family dependent, as outlined in the PLL Tab Information table, below.
| Column Heading | Description |
|---|---|
| Module | Specify a name for the PLL in this column. This is an optional value. |
| PLL Type | Specifies the type of PLL.
Intel®
Agilex™
devices have I/O bank IOPLLs and fabric-feeding
IOPLLs.
Intel®
Agilex™
devices
have:
Intel®
Stratix® 10 devices have:
|
| # PLL Blocks | Enter the number of PLL blocks with the same combination of parameters. |
| XCVR Die ID |
Specify the transceiver die on which PLLs on this row are located. This field is not applicable for I/O PLLs, nor fabric-feeding I/O PLLs. |
| # Counters | Enter the number of counters of the PLL. |
| VCCR_GXB and VCCT_GXB Voltage | Specify the voltage of the VCCR_GXB and VCCT_GXB rails. This field is not applicable for I/O PLLs, nor fabric-feeding I/O PLLs. |
| Output Freq (MHz) | Specify the output frequency for CMU and ATX PLLs. |
| VCO Freq (MHz) | Specify the internal VCO operating frequency for PLLs. |
| Total Power (W) | Shows the total estimated power for this row (in W). |
| User Comments | Enter any comments. This is an optional entry. |
For more information about the PLLs available in Intel® Agilex™ devices, refer to the Intel® Agilex™ Clocking and PLL User Guide.
4.10. Intel FPGA PTC - I/O Tab
The Power and Thermal Calculator assumes that you are using external termination resistors as recommended for SSTL and high-speed transceiver logic HSTL. If your design does not use external termination resistors, choose the LVTTL/ LVCMOS I/O standard with the same VCCIO and similar current strength as the terminated I/O standard.
To use on-chip termination (OCT), select the Current Strength/Output Termination option in the PTC.
The power reported for the I/O signals includes thermal and external I/O power. The total thermal power is the sum of the thermal power consumed by the device from each power rail, as shown in the following equation.
thermal power = thermal PVCCP + thermal PVCCPT + thermal PVCCIO
The following figure shows the I/O power consumption. The ICCIO power rail includes both the thermal PIO and the external PIO.
The VREF pins consume minimal current (typically less than 10 μA), which is negligible when compared with the current consumed by the general purpose I/O (GPIO) pins; therefore, the PTC does not include the current for VREF pins in the calculations.
| Column Heading | Description |
|---|---|
| Module | Specify a name for the I/O in this column. This is an optional value. |
| Application | Specify the application for this I/O row. GPIO and SerDes interfaces can be instantiated using this field. Use the I/O-IP tab to instantiate external memory interface (EMIF) interfaces. |
| Bank Type | Specifies
the type of
Intel®
Stratix® 10
I/O
bank for this row.
|
| Data Rate |
Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a quarter rate interface means that the PHY logic in the FPGA runs at 200MHz. |
| I/O Standard | Specifies the I/O standard used by the I/O pins in this module. |
| Input Termination | Specifies the input termination setting for the input and bidirectional pins in this module. |
| Current Strength/Output Termination | Specifies the current strength or output termination setting for the output and bidirectional pins in this module. Current strength and output termination are mutually exclusive. |
| Slew Rate | Specifies the slew rate setting for the output and bidirectional pins in this module. Using a lower slew rate setting helps reduce switching noise but may increase delay. |
| VOD Setting | Specifies the differential output voltage (VOD) for the output and bidirectional pins in the module. A smaller number indicates a smaller VOD which reduces static power. |
| Pre-Emphasis Setting | Specifies the pre-emphasis setting for the output and bidirectional pins in this module. A smaller number indicates a smaller pre-emphasis which reduces dynamic power. (This column appears in the Intel® Stratix® 10 PTC only.) |
| Programmable De-Emphasis | Specifies the de-emphasis setting for the output and bidirectional pins in this module. A larger number indicates a smaller pre-emphasis which reduces dynamic power. (This column appears in the Intel® Agilex™ PTC only.) |
| Pin Direction | The pin's signal direction. Output, input, or bi-directional. ( Intel® Agilex™ devices only.) |
| # Pins | Number of pins used in the specified configuration. (This column appears in the Intel® Agilex™ PTC only.) |
| # Input Pins | Specifies the number of input-only I/O pins in this module. Differential pin pairs count as one pin. (This column appears in the Intel® Stratix® 10 PTC only.) |
| # Output Pins | Specifies the number of output-only I/O pins in this module. Differential pin pairs count as one pin. (This column appears in the Intel® Stratix® 10 PTC only.) |
| # Bidir Pins |
Specifies the number of bidirectional I/O pins in this module. Differential pin pairs count as one pin. The I/O pin is treated as an output when its output enable signal is active and is treated as an input when the output enable signal is disabled. An I/O pin configured as a bidirectional pin, but used only as an output, consumes more power than if it were configured as an output-only pin, due to the toggling of the input buffer every time the output buffer toggles (they share a common pin). (This column appears in the Intel® Stratix® 10 PTC only.) |
| Data Rate | Indicates whether I/O value changes once (Single-Data Rate) or twice (Double-Data Rate) per cycle. |
| Registered Pins | Indicates whether the pin is registered or not. |
| Toggle % | Percentage of clock cycles when the I/O signal changes value. This value is multiplied by clock frequency to determine the number of transitions per second. If DDR is selected, the toggle rate is multiplied by an additional factor of two. |
| OE % |
For modules with Input Termination set to OFF, enter the average percentage of time that:
During the remaining time:
Input Termination cannot be active while the Output I/O is enabled, so for modules with Input Termination not set to OFF, enter the average percentage of time that On-Chip Termination is inactive (that is, 1-percentage that the On-Chip Termination is active).This number must be a percentage between 0% and 100%. |
| Load (pF) | Specifies pin loading external to the chip (in pF). Applies only to outputs and bidirectional pins. Pin and package capacitance is already included in the I/O model. Include only off-chip capacitance. |
| Pin Clock Frequency (MHz) | Clock frequency (in MHz). 100 MHz with a 12.5% toggle percentage would mean that each I/O pin toggles 12.5 million times per second (100 MHz * 12.5%). |
| Periphery Clock Freq (MHz) |
The I/O subsystem internal PHY clock frequency. This is an output-only field. In SerDes applications, the PHY clock frequency is a function of the SerDes rate and serialization factor. In external memory interface (EMIF) applications, the PHY clock frequency is a function of the memory clock frequency and DDR rate of the EMIF IP. |
| VCO Clock Freq (MHz) |
The internal VCO operating frequency. This is an output-only field. In SerDes applications, VCO frequency is a function of SerDes Data rate. In external memory interface (EMIF) applications, the VCO frequency is a function of the memory clock frequency of the EMIF IP. The VCO frequency is not applicable in GPIO mode. |
| Digital Power (W) | Power dissipated in the digital domain of the I/O-subsystem including GPIO, EMIF controller and SerDes controller. |
| Analog Power (W) | Power dissipated in the analog domain of the I/O-subsystem, for example, I/O buffers. |
| Serialization Factor |
Number of parallel data bits for each serial data bit. Used for SerDes-DPA. |
| Data Rate (Mbps) | The maximum data rate of the SerDes channels in Mbps. |
| Mode | The DPA mode in which the SerDes channels are operating. |
| # of Channels | The number of channels running at the data rate of this SerDes domain. |
| User Comments | Enter any comments. This is an optional entry. |
For more information about the I/O standard termination schemes, refer to I/O and High Speed I/Os in Intel® Agilex™ Devices.
4.11. Intel FPGA PTC - I/O-IP Tab
Analog I/O power and digital power of hard memory controllers and HPS IPs entered on this tab are reported in the Analog Power and Digital Power fields of the I/O tab. If the IP uses other resource types (for example Logic or PLL), the power is reported on the corresponding tab.
I/O-IP Tab Information
| Column Heading | Description |
|---|---|
| Module | Specifies a name for the IP in this column. The module name depends on the selected IP type. It helps to cross-reference each IP module and its corresponding auto-populated entries on other tabs. This name is auto-populated when IP type is selected in the IP column and cannot be changed. |
| IP | Specifies the type of the IP in the design. |
| Voltage | Specifies the I/O voltage of the signaling between periphery device and interface. |
| Data Width (Bits) | Specifies the interface data width of the specific IP (in bits). |
| # of DQS Groups | Specifies the number of DQS groups. |
| Memory Device(s) | Specifies the number of memory devices connected to the interface. |
| Total Address Width | Specifies the total address width. This value is used to derive the total number of address pins required. |
| DDR Rate | Specifies the clock rate of user logic. Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200MHz. |
| PHY Rate | Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the PHY logic in the FPGA runs at 200MHz. |
| Memory Clock Frequency (MHz) | Specifies the frequency of memory clock (in MHz). |
| PLL Reference Clock Frequency (MHz) | Specifies the PLL Reference Clock Frequency (in MHz). |
| User Comments | Enter any comments. This is an optional entry. |
4.12. Intel FPGA PTC - Transceiver Tab
| Input Parameter | Description |
|---|---|
| Total Thermal Power (W) | Total power dissipated in all modules on this page (in watts). |
| Treatment of Unused HSSI Dies |
|
Each row in the Transceiver tab represents a separate transceiver domain. Enter the following parameters for each transceiver domain:
| Column Heading | Description |
|---|---|
| Module | Specifies a name for the module. This is an optional value. |
| Tile |
Specifies the type of transceiver die on which transceiver channels are located. Some devices may include more than one type of transceiver die. This field changes depending on the device options that you choose on the Main tab. |
| XCVR Die ID | Specify the transceiver die on which transceiver channels on this row are located. |
| Starting Channel Location | Specify the starting location within the die for the channels specified in this row. For example, if a given row contains 3 channels, and starting location is specified to be 12, channels are assumed to be in locations 12, 13, and 14. Location 0 denotes the bottom-most channel on the transceiver die. |
| # of Channels |
Specifies the number of channels used in this transceiver domain. Each row represents one transceiver domain. These channels are grouped together in one transceiver bank, or two or more adjacent transceiver banks and clocked by one or more common transmitter PLLs. For E-tile transceivers, if the selected modulation mode is High Data Rate PAM4, enter 2 physical channels to represent 1 logical channel. |
| Operation Mode |
Specifies whether the hardware is configured in full duplex transceiver mode (receiver and transmitter), Receiver Only mode, or Transmitter Only mode. Allowed values depend on the selected tile and protocol mode. |
| Protocol Mode | Specifies the protocol mode. Allowed values depend on the selected tile. |
| Data Rate (Mbps) | Specifies the data rate (in Mbps) for the transceiver. Allowed values depend on the selected protocol mode and selected device. |
| Digital/Analog Interface Width |
Specify the width of the parallel data bus between PCS and PMA. For E-tile PMA Direct, set to PMA parallel data width, even if FPGA FIFO widens the interface. As an example, for 25 Gbps PMA Direct you would typically set this value to 32. When the FEC or EHIP is used, you would set this value to 32 for NRZ mode and 64 for PAM4 mode. |
| Power Mode |
E-tile transceivers can operate at either Normal Power Mode or Low Power Mode. For thermal analysis and regulator sizing, you must set the E-tile transceivers in the Normal Power Mode, because your board design must take into consideration the maximum power conditions. Refer to the E-tile Transceiver PHY User Guide for information on how to switch transceivers from Normal Power Mode to Low Power Mode. |
| FEC | Specify the Forward Error Correction setting. This field is applicable only to E-tile transceivers. |
| EHIP | Specify the Ethernet Hard IP protocol. This field is applicable only to E-tile transceivers. |
| Modulation Mode | Specify the data modulation mode of transceiver channels. This field is applicable only to E-tile transceivers. When you select High Data Rate PAM4 for this field, 2 physical channels are paired to represent 1 logical channel. When specifying # of Channels, enter the number of physical channels (that is, in multiples of 2). |
| Digital Frequency (MHz) | Specify the digital frequency at which the digital portion of the transceiver (including FEC and EHIP) operates. This field is applicable only to E-tile transceivers. |
| # Refclks | Specify the number of reference clocks in use. If another interface on this tile is using the same reference clock, and you have already entered this clock in another row, enter 0 in this row to avoid double counting. This field is applicable only to E-tile transceivers. |
| Refclk Frequency (MHz) | Specify the reference clock frequency. This field is applicable only to E-tile transceivers. |
| Application |
Specify the application type, which determines values for advanced channel options. Select Custom to enable manual editing of advanced channel options for the current row. This field is applicable only to L-tile and H-tile transceivers. |
| Protocol Mode |
Specifies the mode in which the PCS, HIP, and PCIE blocks operate. This mode depends on the XCVR tile and the communication protocol or standard that the channels on this row implement. |
| PLD Clock Frequency (MHz) | Specifies the PLD clock frequency. This is applicable only to P-tile transceivers, and when the selected protocol is PCIe gen4. |
| VCCR_GXB and VCCT_GXB Voltage | Specifies the voltage of the VCCR_GXB and VCCT_GXB rails. Allowed values depend on the selected device and selected data rate. This field is applicable only to L-tile and H-tile transceivers. |
| VOD Setting | The output differential voltage (VOD) setting of the transmitter channel PMA. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers. |
| VOD Voltage | The output differential voltage (VOD) of the transmitter channel PMA (in mV). This voltage depends on the VOD setting and the VCCT_GXB voltage. This field is applicable only to L-tile and H-tile transceivers. |
| First Pre-Tap | Specifies the pre-emphasis setting used by the transmitter channel PMA. Set to Off if the tap value is 0; otherwise, set to On. If pre-emphasis settings are set to On, power consumption does not depend on the magnitude nor the sign (positive or negative) of individual taps. To enable these settings, select Custom in the Application column. |
| First Post-Tap | |
| DFE | Specify mode of the decision feedback equalizer (DFE). Allowed values depend on the selected data rate. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers. |
| Adaptation | Specify if the adaptation feature is used. This option should be enabled if the channels use either CTLE adaptation or DFE adaptation. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers. |
| Transmitter High-Speed Compensation | Specifies if the power distribution network (PDN) induced inter-symbol interference (ISI) compensation is enabled in the TX driver. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers. |
| Digital Power (W) | The total power of all digital circuitry associated with the channels specified on this row, such as the Embedded Multi-die Interconnect Bridge (EMIB). It excludes power of blocks whose power may be shared among multiple channels (and therefore multiple rows), such as the FEC and 100G EHIP in the case of E-tile usage. |
| Analog Power (W) | The total power of all analog circuity associated with the channels specified on this row. It excludes power of blocks whose power may be shared among multiple channels (and therefore multiple rows), such as the clock network. |
| User Comments | Enter any comments. This is an optional entry. |
For more information about the transceiver architecture of the supported device families, refer to the appropriate Transceiver PHY User Guide for Intel® Agilex™ devices.
4.13. Intel FPGA PTC - ADC/DAC Tab ( Intel Stratix 10 Devices Only)
Each row represents a port of a converter. Enter resources and their settings for all modules in your design.
| Column Heading | Description |
|---|---|
| Module | Specifies a name for the module. This is an optional value. |
| Tile | Specifies the type of die on which ADC/DACs are located. |
| ADC Die ID | Specifies the die on which the ADC/DAC port on this row is located. |
| Port ID | Specifies the port ID of the port to which the row corresponds. |
| Sample Rate (Gsps) | Specifies the sampling frequency at which the ADC/DAC is operating. |
| Sleep Level (DOWN) | Specifies the sleep level of the ADC (down conversion). |
| Active Duty Factor (DOWN) | Specifies the active duty factor of the ADC (down conversion). |
| Number of Tuners (DOWN) | Specifies the number of tuners used by this port in the ADC (down conversion). |
| Decimation Factor (DOWN) | Specifies the decimation factor of the ADC (down conversion). |
| NLEQ | N/A — Feature not offered. |
| OOB Blocker Detection | N/A — Feature not offered. |
| Sleep Level (UP) | Specifies the sleep level of the DAC (up conversion). |
| Active Duty Factor (UP) | Specifies the active duty factor of the DAC (up conversion). |
| Number of Tuners (UP) | Specifies the number of tuners used by this port in the DAC (up conversion). |
| Decimation Factor (UP) | Specifies the decimation factor of the DAC (up conversion). |
| DPD | N/A — Feature not offered. |
| Thermal Power (W) | Specifies the total power of all circuity associated with the port specified on this row. It excludes the power of blocks whose power may be shared among multiple ports (and therefore multiple rows). |
| User Comments | Enter any comments. This is an optional entry. |
4.14. Intel FPGA PTC - HPS Tab
To enable parameter entry into the HPS tab, first select a device that supports HPS in the Main tab or in Device Selection, then turn ON the HPS System Switch in the HPS tab. For Intel® Agilex™ devices, select your peripheral modules in the I/O-IP tab.
| Input Parameter | Description |
|---|---|
| HPS System Switch | Turns the HPS system on or off. This selection affects the static power. |
| Total HPS Power (W) | Specifies the total power dissipated by the active processors (in W). |
| VCCL_HPS Voltage (mV) | Specifies the core HPS voltage (in mV). |
| Parameters | Description |
|---|---|
| Frequency (MHz) | Specifies the operating frequency of all CPUs (in MHz). |
| Application |
Select a benchmark application representative of the application running on the CPUs. |
| Number of Cores | Specifies the number of cores in the CPU running the selected application. |
4.15. Intel FPGA PTC - HBM Tab ( Intel Stratix 10 Devices Only)
| Column Heading | Description |
|---|---|
| Rail | The name of the specific power rail. |
| Voltage (mV) | The voltage applied to the specified power rail (in V). |
| Dynamic Current (A) | Component of active current drawn from the specified power rail due to signal activity of all modules on this worksheet (in A). This current is independent of device size, device grade, power characteristics and junction temperature. |
| Column Heading | Description |
|---|---|
| Module | A user-editable field to name each module of the design. |
| HBM ID | Select the HBM die from the list of available HBM dies in the package. |
| Channel | Select the channel from the list of available channels in the HBM die. |
| PC0 Pattern | Select the traffic pattern that most closely matches your application. |
| PC1 Pattern | Select the traffic pattern that most closely matches your application. |
4.16. Intel FPGA PTC - Thermal Tab ( Intel Stratix 10 Devices Only)
To enable thermal calculations, you must select one of the devices that support thermal calculations, on the Main worksheet. Also on the Main worksheet, you must set Power Characteristics to Maximum, and Junction Temp Mode to Detailed Thermal Model.
| Parameter | Description |
|---|---|
| Calculation Mode | Specifies the calculation mode for the thermal
solver to use. Only one calculation mode is currently supported,
which determines the cooling solution required to not exceed the
specified maximum junction temperature TJ. Note: To enable the Thermal worksheet, set the
Junction Temp Mode
on the Main worksheet to Detailed
Thermal Model.
|
| Apply Recommended Margin |
Specifies whether to apply recommended margins to power estimates for thermal analysis. Recommended margins are based on power model maturity, as follows:
These margins apply only to thermal analysis results. Selecting Yes causes the total power to be higher on the Thermal worksheet than power reported elsewhere in the Early Power Estimator. |
| Ambient Temp, TA (°C) | Specify the temperature of the air that is cooling the device. |
| Max. Junction Temp, TJ-MAX (°C) | Specify the maximum junction temperature that no part of any die in the package should exceed. |
| Recommended ΨCA(°C/W) | ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature. |
| Max. ΨJC(°C/W) | ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all dies, assuming the recommended ΨCA value above. |
| Case Temperature TCASE (°C) | The case temperature, which is the temperature at the top center of the integrated heat spreader, assuming the recommended ΨCA value listed above. |
| Parameter | Description |
|---|---|
| HBM TOP_0 | The total power consumption of HBM TOP_0,
assuming the recommended ΨCA value. This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above. This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package. |
| HBM BOT_0 | The total power consumption of HBM BOT_0,
assuming the recommended ΨCA value. This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above. This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package. |
| FPGA Core Power (W) | The total power consumption of the main FPGA die containing core logic, assuming the recommended ΨCA value. This power is reported at the actual temperature of the core die, assuming the recommended ΨCA value. This temperature may be equal to the maximum junction temperature if the FPGA core die is at the highest temperature among all dies (also known as a hot spot). The FPGA core may also be at a lower temperature, if the hot spot is elsewhere in the package (i.e. on another die). |
| Parameter | Description |
|---|---|
| HBM TOP_0 | The thermal resistance between HBM TOP_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HBM BOT_0 | The thermal resistance between HBM BOT_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| FPGA Core ΨJC(°C/W) | The thermal resistance between the main FPGA core die and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| FPGA Core TSD Offset (°C) | The
temperature difference between the hot spot on the core die and the
temperature at the location of the core thermal sensing diode (TSD),
reported using the Intel Temperature IP
Sense software. FPGA core temperature = FPGA core TSD temperature measured using the IP sense method + FPGA core TSD offset. |
| Parameter | Description |
|---|---|
| HSSI_2_1 | The total power consumption of HSSI_2_1,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| HSSI_2_0 | The total power consumption of HSSI_2_0,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| HSSI_1_1 | The total power consumption of HSSI_1_1,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| HSSI_1_0 | The total power consumption of HSSI_1_0,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| HSSI_0_1 | The total power consumption of HSSI_0_1,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| HSSI_0_0 | The total power consumption of HSSI_0_0,
assuming the recommended ΨCA value. This
power is reported at the actual temperature of the specific die,
assuming the recommended ΨCA value
above. This temperature may be equal to the maximum junction
temperature if a specific die is the hot spot, or it may be at a
lower temperature if the hot spot is elsewhere in the package. Note: Each transceiver die in the package reports a
small amount of static power even when no channels are used in
the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of
that tile are grounded. This is an expected
result.
|
| Parameter | Description |
|---|---|
| HSSI_2_1 | The thermal resistance between HSSI_2_1 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HSSI_2_0 | The thermal resistance between HSSI_2_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HSSI_1_1 | The thermal resistance between HSSI_1_1 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HSSI_1_0 | The thermal resistance between HSSI_1_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HSSI_0_1 | The thermal resistance between HSSI_0_1 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| HSSI_0_0 | The thermal resistance between HSSI_0_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value. |
| Parameter | Description |
|---|---|
| HSSI_2_1 | The
temperature difference between the hot spot on the corresponding
transceiver die and location of the thermal sensing diode (TSD) with
the highest temperature reported using the Intel Temperature IP Sense software. (When the
IP sense method is used to read the TSDs, all the TSD locations are
read and the highest of these is reported.) FPGA transceiver temperature = FPGA transceiver TSD temperature measured using the IP sense method + Transceiver TSD offset. (If you are not using the Intel Temperature IP Sense software to read the TSD offsets, contact your Intel support representative for a workaround to get the correct TSD temperature.) |
| HSSI_2_0 | |
| HSSI_1_1 | |
| HSSI_1_0 | |
| HSSI_0_1 | |
| HSSI_0_0 |
The following table shows variations of thermal parameters and power consumption with changing junction temperature of the main FPGA core die. Three values are provided for each parameter. The middle row contains FPGA core temperature and other parameters assuming the recommended ΨCA value above. The top row provides values of all parameters when FPGA core temperature is 5 degrees lower than in the middle row. Similarly, the bottom row provides values of all parameters when FPGA core temperature is 5 degrees higher than in the middle row. It is important to realize that under the conditions in the last row at least one part of one die in the package exceeds the requested maximum junction temperature, and may even exceed the maximum allowed value for the device. Therefore the values in the last row should be used only as an estimate of power dependence on temperature for the purpose of computational fluid dynamic (CFD) simulation, and not for any other purpose.
| Parameter | Description |
|---|---|
| FPGA Core Junction Temperature (°C) | Shows the FPGA core die temperature for each of the three rows, as explained above. |
| FPGA Core Total Power (W) | Provides total power consumption of the main FPGA die containing core logic, assuming the specific core temperature in the given table row. |
| Overall Total Power (W) | Provides total power consumption of all dies in the package, assuming the specific core temperature in the given table row. |
| Case Temperature TCASE (°C) | Provides the case temperature, assuming the specific core temperature in the given table row. |
| Max. Junction Temperature (°C) | |
| ψCA (°C/W) | Provides the thermal resistance between the center of the package integrated heat spreader and the ambient temperature, assuming the specific core temperature in the given table row. For each row, this is the ΨCA value that would cause the FPGA core junction temperature to be at the specific value for a given row. |
| FPGA Core | Provides the thermal resistance, ψJC (°C/W), between each die and the center of the package integrated heat spreader, assuming the specific core temperature in the given table row. |
| HSSI_0_0 | |
| HSSI_1_0 | |
| HSSI_2_0 | |
| HSSI_0_1 | |
| HSSI_1_1 | |
| HSSI_2_1 |
In extreme cases, such as thermal runaway, it may not be possible to calculate the values for +/- 5 degrees, in which case the Thermal worksheet displays the error message: ERROR: Could not calculate parameter variation with core temperature. Try adjusting TJ-MAX to obtain temperature-dependent parameters. When this error occurs, the recommended ΨCA value and all other values above are valid, but the table showing variation of thermal parameters and power consumption with changing junction temperature of the main FPGA core die contains some invalid values. As the error text indicates, adjusting the maximum junction temperature may allow the thermal solver to calculate this dependence, albeit at a different range of FPGA core temperatures than the usual range.
For more information about thermal modeling, refer to AN-787: Thermal Modeling and Management.
4.17. Intel FPGA PTC - Report Tab
The Report tab provides current requirements for each voltage rail, expressed in terms of static current, dynamic current, and total current.
| Column Heading | Description |
|---|---|
| Rail | Name of the voltage rail. |
| Voltage (mV) | Rail voltage. |
| Leakage Current (A) | Indicates the component of current consumed from the specified power rail whenever the power is applied to the rail, independent of circuit activity (in A). This current is dependent on device size, device grade, power characteristics and junction temperature. (This column applies only to Intel® Stratix® 10 devices.) |
| Standby Current (A) | Indicates the component of active current drawn from the specified power rail by all modules on all tabs, independent of signal activity (in A). This current is independent of device grade, power characteristics and junction temperature. Standby current includes, but is not limited to, I/O and transceiver DC bias current. Device size has only a small impact on transceiver DC bias current. (This column applies only to Intel® Agilex™ devices.) |
| Static Current (A) | Indicates the component of current consumed from the specified power rail whenever the power is applied to the rail, independent of circuit activity (in A). This current is dependent on device size, device grade, power characteristics and junction temperature. (This column applies only to Intel® Agilex™ devices.) |
| Dynamic Current (A) | Indicates the component of active current drawn from the specified power rail due to signal activity of all modules on all tabs (in A). This current depends on device size, but is independent of device grade, power characteristics and junction temperature. |
| Total Current Before SmartVID Savings (A) | Indicates the total current consumed from the specified power rail before SmartVID savings (in A). The sum of static and dynamic currents. |
| Total Current (A) | Indicates the total current consumed from the specified power rail (in A). For devices and rails supporting SmartVID, this column shows total current after SmartVID power savings; otherwise, the current reported in this column should equal the sum of static and dynamic currents. |
| Margin | Indicates the recommended margin on total current for regulator sizing. The recommended margin on the Vcc rail is calculated based on the ratio of dynamic to static power. |
| Regulator Groups | Indicates the regulator group number to which this supply is assigned. Regulator group numbers correspond to the group numbers shown in the Intel® Enpirion® worksheet. If you select an automatic assignment mode in the Power Rail Configuration field, the regulator group numbers also correspond to the group numbers in the pin connection guidelines. To edit fields in this column manually, select Custom under Power Rail Configuration. ( Intel® Stratix® 10 devices only.) |
4.18. Intel FPGA PTC - Intel Enpirion Tab ( Intel Stratix 10 Devices Only)
Intel® Enpirion® power devices are available that satisfy the power requirements for the power rails on FPGA devices. Power devices are selected based on load current, input and output voltages, and power-delivery configuration.
Regulator groups are created by combining rails that can be supplied from the same voltage. Intel® Enpirion® device selection is enabled when Power Characteristics in the Main worksheet is set to Maximum, and the Regulator Group section of the Report worksheet is set up correctly with no grouping errors.
| Column Heading | Description |
|---|---|
| Regulator Group | The regulator group number for this regulator. The regulator group numbers correspond to the group numbers shown in the Report worksheet. |
| Intermediate Supply | Indicate whether the supply is an intermediate supply. An intermediate supply is driven by a regulator that is not connected to any supply rails on the FPGA. Instead, such a regulator drives other regulators. If a regulator provides power to both the FPGA and other regulators, this field should be set to No. |
| Regulator Input Voltage (V) | Specifies the input voltage for the regulator. The input voltage must be higher than the output voltage. If this regulator has a parent, its input voltage is automatically set to the parent's output voltage. |
| Regulator Current Draw (A) | Specifies the required input current to the regulator. It is assumed that all regulators have a current efficiency of 85%. |
| Output Voltage (V) | Specifies the output voltage of the regulator. The voltage equals the voltage of the supply rail connected to this regulator. |
| Output Current | Specifies the load current
required by the pins from the regulator. This current equals the sum
of all the supply currents that are connected to this regulator,
multiplied by (1 + Load Current Margin). In addition, if this regulator is a parent of other regulators, the Load Current also includes the sum of all the children's input currents. |
| Margin Entry | Choose whether load current margin is calculated automatically from recommended margins in the Report tab, or entered manually. |
| Load Current Margin | Margin added to the output current to account for component variability. |
| Parent Group | The group number of the regulator that supplies input voltage to the regulator in the current row. This value is applicable only when the input voltage is provided by another regulator on this worksheet. |
| Regulator Type | Choose the type of the regulator. |
| Power OK | Select Yes to select a regulator with a Power OK (POK) output to assist with sequencing. |
| Suggested Enpirion Part | Specifies suggested Intel® Enpirion® parts to implement regulator for a given row, which meet the voltage and current requirements for this row. To finalize regulator selection, evaluate VRM voltage ripple specification and efficiency against the FPGA device requirement from the appropriate data sheets. |
| Pin Compatible Parts | Pin compatible parts are devices with equivalent or higher current capabilities that can be placed on the same PCB footprint as the suggested Intel® Enpirion® part. Additional components or changes to component values may be required when using a pin compatible part. |
| Note | A note may be displayed here, depending on the value chosen under Suggested Enpirion Part. |
5. Factors Affecting the Accuracy of the Intel FPGA Power and Thermal Calculator
Many factors can affect the estimated values displayed in the Intel® FPGA Power and Thermal Calculator (PTC). In particular, the input parameters entered concerning toggle rates and temperature must be accurate to ensure that the system is modeled correctly in the PTC.
5.1. Toggle Rate
The toggle rates specified in the Power and Thermal Calculator (PTC) can have a large impact on the dynamic power consumption displayed. To obtain an accurate estimate, you must input toggle rates that are realistic. Determining realistic toggle rates requires knowing what kind of input the FPGA is receiving and how often it toggles.
To get an accurate estimate if the design is not complete, isolate the separate modules in the design by function, and estimate the resource usage along with the toggle rates of the resources. The easiest way to accomplish this is to use previous designs to estimate the toggle rates for modules with similar function.
The input data in the following figure is encoded for data transmission and has a roughly 50% toggle rate.
- Data toggle rate
- Mod Input toggle rate
- Resource estimate for the Decoder, RAM, Filter, Modulator, and Encoder module
- Toggle rate for the Decoder, RAM, Filter, Modulator, and Encoder module
You can generate these estimates in many ways. If you used similar modules in the past with data inputs of roughly the same toggle rates, you can use that information. If MATLAB* simulations are available for some blocks, you can obtain the toggle rate information from the simulations. If the HDL is available for some of the modules, you can simulate them to obtain toggle rates.
If the HDL is complete, the best way to determine toggle rates is to simulate the design. The accuracy of toggle rate estimates depends on the accuracy of the input vectors. Therefore, determining whether or not the simulation coverage is high gives you a good estimate of how accurate the toggle rate information is.
The Intel® Quartus® Prime software can determine toggle rates of each resource used in the design if you provide information from simulation tools. Designs can be simulated in many different tools and the information provided to the Intel® Quartus® Prime software through a Signal Activity File (.saf) or Value Change Dump (.vcd) file. The Intel® Quartus® Prime Power Analyzer provides the most accurate power estimate.
6. Intel FPGA Power and Thermal Calculator User Guide Archive
| Intel® Quartus® Prime Version | User Guide |
|---|---|
| 19.4 | Intel® FPGA Power and Thermal Calculator User Guide |
7. Document Revision History for the Intel FPGA Power and Thermal Calculator User Guide
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2020.07.24 | 20.1 | In the Power and Thermal Calculator Tabs chapter, implemented changes to the Intel® FPGA PTC - ADC/DAC Tab ( Intel® Stratix® 10 Devices Only) topic. |
| 2020.05.28 | 20.1 | In
the
Intel®
FPGA PTC -
Thermal Tab topic:
|
| 2020.04.27 | 20.1 | In the Power and Thermal Calculator Tabs chapter, updated the figure and revised the table contents, in the Intel® FPGA PTC - ADC/DAC Tab ( Intel® Stratix® 10 Devices Only) topic. |
| 2020.04.13 | 20.1 |
|
| 2020.02.14 | 19.4 | Initial release. |